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-rw-r--r--tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini25
1 files changed, 12 insertions, 13 deletions
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 395184da9..409b736b6 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -19,7 +19,8 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
-memories=system.nvram system.physmem2 system.partition_desc system.physmem system.hypervisor_desc system.rom
+memories=system.physmem2 system.nvram system.partition_desc system.rom system.physmem system.hypervisor_desc
+num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
nvram_bin=/dist/m5/system/binaries/nvram1
@@ -41,20 +42,18 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[9]
[system.bridge]
type=Bridge
delay=100
-filter_ranges_a=
-filter_ranges_b=
nack_delay=8
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
+req_size=16
+resp_size=16
write_ack=false
-side_a=system.iobus.port[14]
-side_b=system.membus.port[2]
+master=system.iobus.port[14]
+slave=system.membus.port[2]
[system.cpu]
type=AtomicSimpleCPU
@@ -84,8 +83,8 @@ simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
-dcache_port=system.membus.port[10]
-icache_port=system.membus.port[9]
+dcache_port=system.membus.port[11]
+icache_port=system.membus.port[10]
[system.cpu.dtb]
type=SparcTLB
@@ -146,7 +145,7 @@ clock=2
header_cycles=1
use_default_range=false
width=64
-port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.side_a system.disk0.pio
+port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.master system.disk0.pio
[system.membus]
type=Bus
@@ -158,7 +157,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.badaddr_responder]
type=IsaFake