diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt | 1739 |
1 files changed, 876 insertions, 863 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index e646f5b40..3b8894174 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.889223 # Number of seconds simulated -sim_ticks 1889223246000 # Number of ticks simulated -final_tick 1889223246000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.893221 # Number of seconds simulated +sim_ticks 1893220881500 # Number of ticks simulated +final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22780 # Simulator instruction rate (inst/s) -host_op_rate 22780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 766551699 # Simulator tick rate (ticks/s) -host_mem_usage 396616 # Number of bytes of host memory used -host_seconds 2464.57 # Real time elapsed on the host -sim_insts 56141873 # Number of instructions simulated -sim_ops 56141873 # Number of ops (including micro ops) simulated +host_inst_rate 15759 # Simulator instruction rate (inst/s) +host_op_rate 15759 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 531367557 # Simulator tick rate (ticks/s) +host_mem_usage 390932 # Number of bytes of host memory used +host_seconds 3562.92 # Real time elapsed on the host +sim_insts 56147815 # Number of instructions simulated +sim_ops 56147815 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859008 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1046208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860800 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25907520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory -system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388422 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25907968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1046208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1046208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7566592 # Number of bytes written to this memory +system.physmem.bytes_written::total 7566592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388450 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 554488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13158322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13713318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 554488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 554488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4005100 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4005100 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4005100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 554488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13158322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17718418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404805 # Number of read requests accepted -system.physmem.writeReqs 118227 # Number of write requests accepted -system.physmem.readBursts 404805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25907520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 404812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118228 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118228 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 552607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13131484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13684599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3996677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3996677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3996677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13131484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17681276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404812 # Number of read requests accepted +system.physmem.writeReqs 118228 # Number of write requests accepted +system.physmem.readBursts 404812 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118228 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25900544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 7565312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25907968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7566592 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25470 # Per bank write bursts -system.physmem.perBankRdBursts::1 25713 # Per bank write bursts -system.physmem.perBankRdBursts::2 25812 # Per bank write bursts -system.physmem.perBankRdBursts::3 25774 # Per bank write bursts -system.physmem.perBankRdBursts::4 25230 # Per bank write bursts -system.physmem.perBankRdBursts::5 24950 # Per bank write bursts -system.physmem.perBankRdBursts::6 24793 # Per bank write bursts -system.physmem.perBankRdBursts::7 24569 # Per bank write bursts -system.physmem.perBankRdBursts::8 25113 # Per bank write bursts -system.physmem.perBankRdBursts::9 25266 # Per bank write bursts -system.physmem.perBankRdBursts::10 25525 # Per bank write bursts -system.physmem.perBankRdBursts::11 24857 # Per bank write bursts -system.physmem.perBankRdBursts::12 24533 # Per bank write bursts -system.physmem.perBankRdBursts::13 25560 # Per bank write bursts -system.physmem.perBankRdBursts::14 25804 # Per bank write bursts -system.physmem.perBankRdBursts::15 25731 # Per bank write bursts -system.physmem.perBankWrBursts::0 7815 # Per bank write bursts -system.physmem.perBankWrBursts::1 7678 # Per bank write bursts -system.physmem.perBankWrBursts::2 8068 # Per bank write bursts -system.physmem.perBankWrBursts::3 7736 # Per bank write bursts -system.physmem.perBankWrBursts::4 7326 # Per bank write bursts -system.physmem.perBankWrBursts::5 6953 # Per bank write bursts -system.physmem.perBankWrBursts::6 6780 # Per bank write bursts -system.physmem.perBankWrBursts::7 6420 # Per bank write bursts -system.physmem.perBankWrBursts::8 7238 # Per bank write bursts -system.physmem.perBankWrBursts::9 6883 # Per bank write bursts -system.physmem.perBankWrBursts::10 7397 # Per bank write bursts -system.physmem.perBankWrBursts::11 6875 # Per bank write bursts -system.physmem.perBankWrBursts::12 7088 # Per bank write bursts -system.physmem.perBankWrBursts::13 8006 # Per bank write bursts -system.physmem.perBankWrBursts::14 7993 # Per bank write bursts -system.physmem.perBankWrBursts::15 7949 # Per bank write bursts +system.physmem.perBankRdBursts::0 25483 # Per bank write bursts +system.physmem.perBankRdBursts::1 25705 # Per bank write bursts +system.physmem.perBankRdBursts::2 25813 # Per bank write bursts +system.physmem.perBankRdBursts::3 25775 # Per bank write bursts +system.physmem.perBankRdBursts::4 25223 # Per bank write bursts +system.physmem.perBankRdBursts::5 24955 # Per bank write bursts +system.physmem.perBankRdBursts::6 24789 # Per bank write bursts +system.physmem.perBankRdBursts::7 24583 # Per bank write bursts +system.physmem.perBankRdBursts::8 25108 # Per bank write bursts +system.physmem.perBankRdBursts::9 25258 # Per bank write bursts +system.physmem.perBankRdBursts::10 25518 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24528 # Per bank write bursts +system.physmem.perBankRdBursts::13 25564 # Per bank write bursts +system.physmem.perBankRdBursts::14 25798 # Per bank write bursts +system.physmem.perBankRdBursts::15 25721 # Per bank write bursts +system.physmem.perBankWrBursts::0 7829 # Per bank write bursts +system.physmem.perBankWrBursts::1 7671 # Per bank write bursts +system.physmem.perBankWrBursts::2 8071 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts +system.physmem.perBankWrBursts::4 7318 # Per bank write bursts +system.physmem.perBankWrBursts::5 6944 # Per bank write bursts +system.physmem.perBankWrBursts::6 6788 # Per bank write bursts +system.physmem.perBankWrBursts::7 6427 # Per bank write bursts +system.physmem.perBankWrBursts::8 7237 # Per bank write bursts +system.physmem.perBankWrBursts::9 6873 # Per bank write bursts +system.physmem.perBankWrBursts::10 7386 # Per bank write bursts +system.physmem.perBankWrBursts::11 6888 # Per bank write bursts +system.physmem.perBankWrBursts::12 7081 # Per bank write bursts +system.physmem.perBankWrBursts::13 8010 # Per bank write bursts +system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankWrBursts::15 7945 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 1889214280000 # Total gap between requests +system.physmem.numWrRetry 68 # Number of times write queue was full causing retry +system.physmem.totGap 1893211891000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404805 # Read request sizes (log2) +system.physmem.readPktSize::6 404812 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118227 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118228 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,193 +149,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63746 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 524.988548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.641335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 414.335221 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14725 23.10% 23.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10901 17.10% 40.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5357 8.40% 48.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3110 4.88% 53.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2601 4.08% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 2.67% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1560 2.45% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1439 2.26% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22352 35.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63746 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.386372 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2900.765356 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5295 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 528.527867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 322.547536 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.556682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14397 22.74% 22.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11107 17.54% 40.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4705 7.43% 47.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3113 4.92% 52.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2233 3.53% 56.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2328 3.68% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1953 3.08% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1598 2.52% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21885 34.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63319 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5233 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.334798 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2918.735904 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5230 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5298 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.311250 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.880356 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.145944 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4698 88.67% 88.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.62% 89.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 235 4.44% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 22 0.42% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 12 0.23% 94.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.26% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.08% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 30 0.57% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 15 0.28% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 179 3.38% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 1 0.02% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.08% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 12 0.23% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 2 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.08% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 8 0.15% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5298 # Writes before turning the bus around for reads -system.physmem.totQLat 2164522000 # Total ticks spent queuing -system.physmem.totMemAccLat 9752647000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5348.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5233 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5233 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.588955 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.741886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.816216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4718 90.16% 90.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.63% 90.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 174 3.33% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 5 0.10% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 12 0.23% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.15% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.02% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 32 0.61% 95.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 151 2.89% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 15 0.29% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 10 0.19% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 3 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 10 0.19% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.11% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 12 0.23% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.17% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5233 # Writes before turning the bus around for reads +system.physmem.totQLat 5895300250 # Total ticks spent queuing +system.physmem.totMemAccLat 13483350250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14567.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24098.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33317.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.71 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 363251 # Number of row buffer hits during reads -system.physmem.writeRowHits 95908 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.12 # Row buffer hit rate for writes -system.physmem.avgGap 3612043.39 # Average gap between requests -system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234556560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127982250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578025800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 380868480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60772181625 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1080221277750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1266709348065 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.494357 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1796832063750 # Time in different power states -system.physmem_0.memoryStateTime::REF 63085100000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29299865000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247363200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134970000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1578634200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385099920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61856765370 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1079269896750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1266867185040 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.577899 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1795248089750 # Time in different power states -system.physmem_1.memoryStateTime::REF 63085100000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30883852750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15253451 # Number of BP lookups -system.cpu.branchPred.condPredicted 13119801 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 515637 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12113296 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4570787 # Number of BTB hits +system.physmem.avgWrQLen 24.81 # Average write queue length when enqueuing +system.physmem.readRowHits 363810 # Number of row buffer hits during reads +system.physmem.writeRowHits 95775 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes +system.physmem.avgGap 3619631.18 # Average gap between requests +system.physmem.pageHitRate 87.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 221882640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 117933420 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1444607640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4693391040.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4737017490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 303974400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10896307530 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 5550083520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 443242644240 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 471515616450 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.054730 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1881921702000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 481983250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1993748000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1843690402750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 14453321750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8706248250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23895177500 # Time in different power states +system.physmem_1.actEnergy 230215020 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122362185 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 310146300 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4816933680.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4925461770 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 303573120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11119407240 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 5660238720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 442986687510 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 471921610125 # Total energy per rank (pJ) +system.physmem_1.averagePower 249.269176 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1881622925500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 484393500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2046440000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1842500290250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 14740166500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9065047000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24384544250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15264339 # Number of BP lookups +system.cpu.branchPred.condPredicted 13122374 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 525708 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12102111 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4571092 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.733636 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 859438 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30658 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6570706 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 545483 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 6025223 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 218035 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.771030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 863726 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33596 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6525159 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 541190 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5983969 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 222121 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9316925 # DTB read hits -system.cpu.dtb.read_misses 17695 # DTB read misses +system.cpu.dtb.read_hits 9321681 # DTB read hits +system.cpu.dtb.read_misses 17691 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764827 # DTB read accesses -system.cpu.dtb.write_hits 6393212 # DTB write hits +system.cpu.dtb.read_accesses 764795 # DTB read accesses +system.cpu.dtb.write_hits 6394158 # DTB write hits system.cpu.dtb.write_misses 2442 # DTB write misses -system.cpu.dtb.write_acv 158 # DTB write access violations -system.cpu.dtb.write_accesses 298820 # DTB write accesses -system.cpu.dtb.data_hits 15710137 # DTB hits -system.cpu.dtb.data_misses 20137 # DTB misses -system.cpu.dtb.data_acv 369 # DTB access violations -system.cpu.dtb.data_accesses 1063647 # DTB accesses -system.cpu.itb.fetch_hits 4018824 # ITB hits -system.cpu.itb.fetch_misses 6310 # ITB misses -system.cpu.itb.fetch_acv 701 # ITB acv -system.cpu.itb.fetch_accesses 4025134 # ITB accesses +system.cpu.dtb.write_acv 159 # DTB write access violations +system.cpu.dtb.write_accesses 298776 # DTB write accesses +system.cpu.dtb.data_hits 15715839 # DTB hits +system.cpu.dtb.data_misses 20133 # DTB misses +system.cpu.dtb.data_acv 370 # DTB access violations +system.cpu.dtb.data_accesses 1063571 # DTB accesses +system.cpu.itb.fetch_hits 4020046 # ITB hits +system.cpu.itb.fetch_misses 6280 # ITB misses +system.cpu.itb.fetch_acv 699 # ITB acv +system.cpu.itb.fetch_accesses 4026326 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -350,27 +363,27 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12752 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281746974.905897 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439847984.325030 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281786440.323087 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439974345.162947 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 19000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 369000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 92804534000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796418712000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 185630526 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 96550538000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 193121889 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56141873 # Number of instructions committed -system.cpu.committedOps 56141873 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2958149 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 56147815 # Number of instructions committed +system.cpu.committedOps 56147815 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2978612 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3592815966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.306454 # CPI: cycles per instruction -system.cpu.ipc 0.302439 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199005 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36197195 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60822 0.11% 70.28% # Class of committed instruction +system.cpu.quiesceCycles 3593319874 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.439526 # CPI: cycles per instruction +system.cpu.ipc 0.290738 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199269 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36201024 64.47% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60831 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -398,34 +411,34 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9319321 16.60% 86.95% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6372729 11.35% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951086 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 9320403 16.60% 86.95% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6373341 11.35% 98.31% # Class of committed instruction +system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56141873 # Class of committed instruction +system.cpu.op_class_0::total 56147815 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211498 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74792 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1903 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105883 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182709 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73425 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.hwrei 211531 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74800 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105905 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182741 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73433 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1903 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73425 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148884 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1835945903000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 85568000 0.00% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 710063500 0.04% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 52480708000 2.78% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1889222242500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73433 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148902 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837683771000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 86162500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 712688000 0.04% 97.11% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54737244500 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1893219866000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693454 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814870 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693386 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814825 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -464,514 +477,514 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175546 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175574 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5128 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192434 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches +system.cpu.kern.callpal::total 192465 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2091 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches system.cpu.kern.mode_good::kernel 1905 system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324200 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324255 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080344 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36856948000 1.95% 1.95% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4192339500 0.22% 2.17% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1848172945000 97.83% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392541 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 37297482500 1.97% 1.97% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4311459500 0.23% 2.20% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1851610914000 97.80% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85233988 # Number of cycles that the object actually ticked -system.cpu.idleCycles 100396538 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394263 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980931 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13942036 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394775 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.995903 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 94238500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980931 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy +system.cpu.tickCycles 85352026 # Number of cycles that the object actually ticked +system.cpu.idleCycles 107769863 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394246 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13946627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394758 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.999317 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63909041 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63909041 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7981560 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7981560 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5577988 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5577988 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183448 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183448 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199007 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199007 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13559548 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13559548 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13559548 # number of overall hits -system.cpu.dcache.overall_hits::total 13559548 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096304 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096304 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573678 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16581 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16581 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1669982 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1669982 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1669982 # number of overall misses -system.cpu.dcache.overall_misses::total 1669982 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31558344500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31558344500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22538815500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22538815500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222577500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222577500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54097160000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54097160000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54097160000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54097160000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9077864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9077864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151666 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151666 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199007 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199007 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15229530 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15229530 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15229530 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15229530 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120767 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120767 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093256 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093256 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082893 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082893 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109654 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109654 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109654 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109654 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28786.125472 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28786.125472 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39288.268855 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39288.268855 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.647548 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13423.647548 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32393.858137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32393.858137 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63927104 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63927104 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7985415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7985415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5578562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5578562 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183593 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183593 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199022 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199022 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13563977 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13563977 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13563977 # number of overall hits +system.cpu.dcache.overall_hits::total 13563977 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096352 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096352 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573692 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573692 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16450 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16450 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670044 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670044 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670044 # number of overall misses +system.cpu.dcache.overall_misses::total 1670044 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33571810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33571810000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25337965000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25337965000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222587500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222587500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 58909775000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 58909775000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 58909775000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 58909775000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9081767 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9081767 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152254 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152254 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200043 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200043 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199022 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199022 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15234021 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15234021 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15234021 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15234021 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120720 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120720 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093249 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.109626 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109626 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109626 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109626 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35274.384986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35274.384986 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837697 # number of writebacks -system.cpu.dcache.writebacks::total 837697 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269759 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269759 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837664 # number of writebacks +system.cpu.dcache.writebacks::total 837664 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21993 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21993 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269693 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269693 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291740 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291740 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291740 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291740 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074323 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074323 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303919 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303919 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16578 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16578 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378242 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378242 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378242 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378242 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291686 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291686 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291686 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291686 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074359 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074359 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303999 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 303999 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16447 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16447 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378358 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378358 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378358 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378358 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30011433500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30011433500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11481403000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11481403000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205832000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205832000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41492836500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41492836500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41492836500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41492836500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534160500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534160500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534160500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534160500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118345 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118345 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049404 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049404 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082878 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082878 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090498 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090498 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27935.205241 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27935.205241 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37777.838832 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37777.838832 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12415.972976 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12415.972976 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.581530 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.581530 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92692.918857 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92692.918857 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1476241 # number of replacements -system.cpu.icache.tags.tagsinuse 509.437018 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19208652 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1476752 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.007365 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 33938325500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.437018 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994994 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994994 # Average percentage of cache occupancy +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32011150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32011150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12927980000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12927980000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205437000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205437000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44939130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44939130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44939130000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44939130000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534184500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534184500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534184500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534184500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118298 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118298 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049413 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049413 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082217 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082217 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090479 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090479 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1477105 # number of replacements +system.cpu.icache.tags.tagsinuse 509.256263 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19233040 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1477616 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.016264 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 36168250500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.256263 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22162507 # Number of tag accesses -system.cpu.icache.tags.data_accesses 22162507 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 19208655 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 19208655 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 19208655 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 19208655 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 19208655 # number of overall hits -system.cpu.icache.overall_hits::total 19208655 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1476926 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1476926 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1476926 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1476926 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1476926 # number of overall misses -system.cpu.icache.overall_misses::total 1476926 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20401531500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20401531500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20401531500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20401531500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20401531500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20401531500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20685581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20685581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20685581 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20685581 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20685581 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20685581 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071399 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071399 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071399 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071399 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071399 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13813.509614 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13813.509614 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13813.509614 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13813.509614 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13813.509614 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13813.509614 # average overall miss latency +system.cpu.icache.tags.tag_accesses 22188623 # Number of tag accesses +system.cpu.icache.tags.data_accesses 22188623 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 19233043 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 19233043 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 19233043 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 19233043 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 19233043 # number of overall hits +system.cpu.icache.overall_hits::total 19233043 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1477790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1477790 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1477790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1477790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1477790 # number of overall misses +system.cpu.icache.overall_misses::total 1477790 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20696583500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20696583500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20696583500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20696583500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20696583500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20696583500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20710833 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20710833 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20710833 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20710833 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20710833 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20710833 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071353 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071353 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071353 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071353 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071353 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071353 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14005.091048 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14005.091048 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14005.091048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14005.091048 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1476241 # number of writebacks -system.cpu.icache.writebacks::total 1476241 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1476926 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1476926 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1476926 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1476926 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1476926 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1476926 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18924605500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18924605500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18924605500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18924605500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18924605500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18924605500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071399 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071399 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071399 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12813.509614 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12813.509614 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12813.509614 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12813.509614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12813.509614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12813.509614 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 339622 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65416.328180 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5334629 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405144 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.167242 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6356009000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 267.504634 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5791.332200 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59357.491346 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088369 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.905723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998174 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1477105 # number of writebacks +system.cpu.icache.writebacks::total 1477105 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477790 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1477790 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1477790 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1477790 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1477790 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1477790 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19218793500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19218793500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19218793500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19218793500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19218793500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19218793500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071353 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071353 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071353 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13005.091048 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13005.091048 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 339628 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65408.612363 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5336325 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 405150 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.171233 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6812996000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 268.308875 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5785.000603 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.302886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088272 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.905690 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 631 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59330 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59344 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46327377 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46327377 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 837697 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 837697 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1475656 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1475656 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 46341016 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 46341016 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 837664 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 837664 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1476525 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1476525 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187300 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187300 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1460502 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1460502 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818651 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 818651 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1460502 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1005951 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2466453 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1460502 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1005951 # number of overall hits -system.cpu.l2cache.overall_hits::total 2466453 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116630 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116630 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272219 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 272219 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388849 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405218 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388849 # number of overall misses -system.cpu.l2cache.overall_misses::total 405218 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 249500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 249500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9053314500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9053314500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1334237500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1334237500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19962557500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 19962557500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1334237500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 29015872000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30350109500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1334237500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 29015872000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30350109500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 837697 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 837697 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1475656 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1475656 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 303930 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 303930 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1476871 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1476871 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090870 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1090870 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1476871 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1394800 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2871671 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1476871 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1394800 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2871671 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383740 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383740 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011084 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011084 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249543 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249543 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011084 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278785 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141109 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011084 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278785 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141109 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49900 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49900 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77624.234759 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77624.234759 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81510.018938 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81510.018938 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73332.711897 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73332.711897 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81510.018938 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74619.896155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74898.226387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81510.018938 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74619.896155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74898.226387 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 187358 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187358 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461386 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1461386 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818548 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 818548 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1461386 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1005906 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2467292 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1461386 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1005906 # number of overall hits +system.cpu.l2cache.overall_hits::total 2467292 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116652 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116652 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16348 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16348 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272226 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 272226 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 16348 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388878 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405226 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 16348 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388878 # number of overall misses +system.cpu.l2cache.overall_misses::total 405226 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 331000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10499091500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10499091500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1618484000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1618484000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21963269500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21963269500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1618484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 32462361000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34080845000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1618484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 32462361000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34080845000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 837664 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 837664 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1476525 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1476525 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304010 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304010 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477734 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1477734 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090774 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1090774 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1477734 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1394784 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2872518 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1477734 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1394784 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2872518 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383711 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383711 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011063 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011063 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249571 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249571 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011063 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278809 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141070 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011063 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278809 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141070 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90003.527586 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90003.527586 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 99001.957426 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 99001.957426 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80680.278519 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80680.278519 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84103.302848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84103.302848 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 76715 # number of writebacks -system.cpu.l2cache.writebacks::total 76715 # number of writebacks -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116630 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116630 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272219 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272219 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388849 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405218 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388849 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405218 # number of overall MSHR misses +system.cpu.l2cache.writebacks::writebacks 76716 # number of writebacks +system.cpu.l2cache.writebacks::total 76716 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116652 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116652 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16348 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16348 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272226 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272226 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16348 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388878 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405226 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16348 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388878 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405226 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 199500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 199500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7887014500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7887014500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1170547500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1170547500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17243377000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17243377000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170547500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25130391500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26300939000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170547500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25130391500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26300939000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383740 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383740 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011084 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249543 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249543 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141109 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141109 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39900 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39900 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67624.234759 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67624.234759 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71510.018938 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71510.018938 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63343.767334 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63343.767334 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87457.857531 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87457.857531 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5742250 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2870700 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1972 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9332571500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9332571500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1455004000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1455004000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19244147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19244147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1455004000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28576719000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30031723000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1455004000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28576719000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30031723000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447540500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447540500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447540500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447540500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383711 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383711 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011063 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249571 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249571 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141070 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141070 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5743946 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871549 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2574859 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1476241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 303930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 303930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1476926 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4430038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217161 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8647199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188999168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142932652 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 331931820 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340234 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923264 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3228320 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000974 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031197 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 2575626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 914380 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1477105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1090934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 242 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4432629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217118 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8649747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189109696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142929468 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 332039164 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340242 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923392 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3229178 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000972 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031158 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3225175 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3145 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3226040 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3138 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3228320 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5198149000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3229178 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5199830000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2215530716 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2216814740 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2103938977 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2103909988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -985,12 +998,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51173 # Transaction distribution -system.iobus.trans_dist::WriteResp 51173 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5098 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51175 # Transaction distribution +system.iobus.trans_dist::WriteResp 51175 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -999,11 +1012,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116552 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1012,50 +1025,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44332 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705940 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5405000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5417000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 800000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 803500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 182000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14495500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15637500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5973000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6005000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216181312 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216245035 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23481000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.301361 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.299106 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1731952426000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.301361 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081335 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081335 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1735874546000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.299106 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081194 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081194 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1064,14 +1077,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21934383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21934383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4859195929 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4859195929 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4881130312 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4881130312 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4881130312 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4881130312 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22024383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22024383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948308652 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4948308652 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4970333035 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4970333035 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4970333035 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4970333035 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1088,19 +1101,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126788.341040 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126788.341040 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116942.528133 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116942.528133 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116983.350797 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116983.350797 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 127308.572254 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119121.223128 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119121.223128 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1402 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 107.846154 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1112,14 +1125,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13284383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13284383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2779181979 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2779181979 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2792466362 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2792466362 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2792466362 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2792466362 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13374383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13374383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868251757 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2868251757 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2881626140 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2881626140 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2881626140 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2881626140 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1128,75 +1141,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76788.341040 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76788.341040 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66884.433457 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66884.433457 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827436 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381422 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827498 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381477 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295668 # Transaction distribution -system.membus.trans_dist::WriteReq 9621 # Transaction distribution -system.membus.trans_dist::WriteResp 9621 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution -system.membus.trans_dist::CleanEvict 262241 # Transaction distribution -system.membus.trans_dist::UpgradeReq 137 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116498 # Transaction distribution -system.membus.trans_dist::ReadExResp 116498 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288761 # Transaction distribution -system.membus.trans_dist::BadAddressError 23 # Transaction distribution +system.membus.trans_dist::ReadResp 295653 # Transaction distribution +system.membus.trans_dist::WriteReq 9623 # Transaction distribution +system.membus.trans_dist::WriteResp 9623 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118228 # Transaction distribution +system.membus.trans_dist::CleanEvict 262245 # Transaction distribution +system.membus.trans_dist::UpgradeReq 138 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 116520 # Transaction distribution +system.membus.trans_dist::ReadExResp 116520 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288747 # Transaction distribution +system.membus.trans_dist::BadAddressError 24 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148773 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181947 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44332 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860652 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1265372 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30861180 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33518380 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 433 # Total snoops (count) +system.membus.pkt_size::total 33518908 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 434 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463499 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001458 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038162 # Request fanout histogram +system.membus.snoop_fanout::samples 463510 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001463 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038218 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462823 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 676 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463499 # Request fanout histogram -system.membus.reqLayer0.occupancy 29272500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463510 # Request fanout histogram +system.membus.reqLayer0.occupancy 30461000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319341290 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319556082 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160301000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160064000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1228,28 +1241,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |