diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt | 1247 |
1 files changed, 626 insertions, 621 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index d1ad31617..4fcd96b8e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.884241 # Number of seconds simulated -sim_ticks 1884241273000 # Number of ticks simulated -final_tick 1884241273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.884236 # Number of seconds simulated +sim_ticks 1884235597000 # Number of ticks simulated +final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193195 # Simulator instruction rate (inst/s) -host_op_rate 193195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6486085343 # Simulator tick rate (ticks/s) -host_mem_usage 317148 # Number of bytes of host memory used -host_seconds 290.51 # Real time elapsed on the host -sim_insts 56124126 # Number of instructions simulated -sim_ops 56124126 # Number of ops (including micro ops) simulated +host_inst_rate 284222 # Simulator instruction rate (inst/s) +host_op_rate 284222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9542341098 # Simulator tick rate (ticks/s) +host_mem_usage 373416 # Number of bytes of host memory used +host_seconds 197.46 # Real time elapsed on the host +sim_insts 56122640 # Number of instructions simulated +sim_ops 56122640 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25914944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 25914816 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25915904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7561408 # Number of bytes written to this memory -system.physmem.bytes_written::total 7561408 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 404921 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 404919 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404936 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118147 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118147 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13753517 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13753490 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13754026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4012972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4012972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4012972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13753517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 558945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13753490 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17766999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404936 # Number of read requests accepted -system.physmem.writeReqs 159699 # Number of write requests accepted -system.physmem.readBursts 404936 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159699 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25909568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue -system.physmem.bytesWritten 10083392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25915904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10220736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2126 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 153 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25482 # Per bank write bursts +system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404934 # Number of read requests accepted +system.physmem.writeReqs 159706 # Number of write requests accepted +system.physmem.readBursts 404934 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159706 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25910208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5568 # Total number of bytes read from write queue +system.physmem.bytesWritten 10081344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25915776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10221184 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 87 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2165 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25481 # Per bank write bursts system.physmem.perBankRdBursts::1 25742 # Per bank write bursts -system.physmem.perBankRdBursts::2 25842 # Per bank write bursts -system.physmem.perBankRdBursts::3 25776 # Per bank write bursts -system.physmem.perBankRdBursts::4 25226 # Per bank write bursts +system.physmem.perBankRdBursts::2 25839 # Per bank write bursts +system.physmem.perBankRdBursts::3 25784 # Per bank write bursts +system.physmem.perBankRdBursts::4 25228 # Per bank write bursts system.physmem.perBankRdBursts::5 24953 # Per bank write bursts -system.physmem.perBankRdBursts::6 24814 # Per bank write bursts -system.physmem.perBankRdBursts::7 24563 # Per bank write bursts +system.physmem.perBankRdBursts::6 24817 # Per bank write bursts +system.physmem.perBankRdBursts::7 24560 # Per bank write bursts system.physmem.perBankRdBursts::8 25102 # Per bank write bursts -system.physmem.perBankRdBursts::9 25273 # Per bank write bursts -system.physmem.perBankRdBursts::10 25528 # Per bank write bursts -system.physmem.perBankRdBursts::11 24851 # Per bank write bursts -system.physmem.perBankRdBursts::12 24526 # Per bank write bursts +system.physmem.perBankRdBursts::9 25274 # Per bank write bursts +system.physmem.perBankRdBursts::10 25530 # Per bank write bursts +system.physmem.perBankRdBursts::11 24856 # Per bank write bursts +system.physmem.perBankRdBursts::12 24523 # Per bank write bursts system.physmem.perBankRdBursts::13 25574 # Per bank write bursts -system.physmem.perBankRdBursts::14 25842 # Per bank write bursts -system.physmem.perBankRdBursts::15 25743 # Per bank write bursts -system.physmem.perBankWrBursts::0 10288 # Per bank write bursts -system.physmem.perBankWrBursts::1 10037 # Per bank write bursts -system.physmem.perBankWrBursts::2 10678 # Per bank write bursts -system.physmem.perBankWrBursts::3 10053 # Per bank write bursts -system.physmem.perBankWrBursts::4 9806 # Per bank write bursts -system.physmem.perBankWrBursts::5 9437 # Per bank write bursts -system.physmem.perBankWrBursts::6 9137 # Per bank write bursts -system.physmem.perBankWrBursts::7 8750 # Per bank write bursts -system.physmem.perBankWrBursts::8 9885 # Per bank write bursts -system.physmem.perBankWrBursts::9 8937 # Per bank write bursts -system.physmem.perBankWrBursts::10 9881 # Per bank write bursts -system.physmem.perBankWrBursts::11 9301 # Per bank write bursts -system.physmem.perBankWrBursts::12 9770 # Per bank write bursts -system.physmem.perBankWrBursts::13 10691 # Per bank write bursts -system.physmem.perBankWrBursts::14 10395 # Per bank write bursts -system.physmem.perBankWrBursts::15 10507 # Per bank write bursts +system.physmem.perBankRdBursts::14 25845 # Per bank write bursts +system.physmem.perBankRdBursts::15 25739 # Per bank write bursts +system.physmem.perBankWrBursts::0 10323 # Per bank write bursts +system.physmem.perBankWrBursts::1 10094 # Per bank write bursts +system.physmem.perBankWrBursts::2 10597 # Per bank write bursts +system.physmem.perBankWrBursts::3 9998 # Per bank write bursts +system.physmem.perBankWrBursts::4 9794 # Per bank write bursts +system.physmem.perBankWrBursts::5 9430 # Per bank write bursts +system.physmem.perBankWrBursts::6 9122 # Per bank write bursts +system.physmem.perBankWrBursts::7 8746 # Per bank write bursts +system.physmem.perBankWrBursts::8 9866 # Per bank write bursts +system.physmem.perBankWrBursts::9 8965 # Per bank write bursts +system.physmem.perBankWrBursts::10 9841 # Per bank write bursts +system.physmem.perBankWrBursts::11 9391 # Per bank write bursts +system.physmem.perBankWrBursts::12 9895 # Per bank write bursts +system.physmem.perBankWrBursts::13 10602 # Per bank write bursts +system.physmem.perBankWrBursts::14 10396 # Per bank write bursts +system.physmem.perBankWrBursts::15 10461 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1884232486500 # Total gap between requests +system.physmem.totGap 1884226862500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404936 # Read request sizes (log2) +system.physmem.readPktSize::6 404934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159699 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159706 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -144,119 +144,119 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 547.429771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 335.789885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 418.130322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14719 22.39% 22.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10714 16.30% 38.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4807 7.31% 45.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3176 4.83% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2550 3.88% 54.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1953 2.97% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1437 2.19% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1697 2.58% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24696 37.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65749 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5738 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.553154 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2788.767091 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5735 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 547.425008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 336.336786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.790126 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14590 22.19% 22.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10813 16.45% 38.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4856 7.39% 46.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3188 4.85% 50.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2531 3.85% 54.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1959 2.98% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1455 2.21% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1675 2.55% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24680 37.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65747 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5741 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.518028 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2788.038880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5738 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5738 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5738 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.457825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.746842 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.017596 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4693 81.79% 81.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 187 3.26% 85.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 275 4.79% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 67 1.17% 91.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 92 1.60% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 47 0.82% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 24 0.42% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.19% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.33% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.12% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.24% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.10% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.07% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 17 0.30% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 47 0.82% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.30% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 17 0.30% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 79 1.38% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 32 0.56% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 20 0.35% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 19 0.33% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 15 0.26% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 7 0.12% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5738 # Writes before turning the bus around for reads -system.physmem.totQLat 2167079250 # Total ticks spent queuing -system.physmem.totMemAccLat 9757773000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024185000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5352.97 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5741 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.437903 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.774518 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.753883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4686 81.62% 81.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 175 3.05% 84.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 305 5.31% 89.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 60 1.05% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 91 1.59% 92.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 55 0.96% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 13 0.23% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 10 0.17% 93.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 19 0.33% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 16 0.28% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 10 0.17% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 11 0.19% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 17 0.30% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 40 0.70% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 20 0.35% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 16 0.28% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 94 1.64% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 33 0.57% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 16 0.28% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 17 0.30% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.16% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.09% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5741 # Writes before turning the bus around for reads +system.physmem.totQLat 2143675250 # Total ticks spent queuing +system.physmem.totMemAccLat 9734556500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5295.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24102.97 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24045.03 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s @@ -266,66 +266,71 @@ system.physmem.busUtil 0.15 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 364185 # Number of row buffer hits during reads -system.physmem.writeRowHits 132456 # Number of row buffer hits during writes +system.physmem.avgWrQLen 25.52 # Average write queue length when enqueuing +system.physmem.readRowHits 364210 # Number of row buffer hits during reads +system.physmem.writeRowHits 132411 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.06 # Row buffer hit rate for writes -system.physmem.avgGap 3337080.57 # Average gap between requests +system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes +system.physmem.avgGap 3337041.06 # Average gap between requests system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1774592996500 # Time in different power states -system.physmem.memoryStateTime::REF 62918700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 46722146000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 242668440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 254394000 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 132408375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 138806250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1578704400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1579024200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 506645280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 514298160 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 59931006120 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 60719870160 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1077969239250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1077277253250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1263429649065 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1263552623220 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.526996 # Core power per rank (mW) -system.physmem.averagePower::1 670.592261 # Core power per rank (mW) -system.cpu.branchPred.lookups 15011318 # Number of BP lookups -system.cpu.branchPred.condPredicted 13019220 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 376037 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9980368 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5204970 # Number of BTB hits +system.physmem_0.actEnergy 243152280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132672375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578751200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 506113920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 59789504475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1078093355250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1263412526700 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.517914 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1793297401750 # Time in different power states +system.physmem_0.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28017727000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 253895040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138534000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579055400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 514622160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60612218820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1077371684250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1263538986870 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.585024 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1792097761500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29217381000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 15006303 # Number of BP lookups +system.cpu.branchPred.condPredicted 13014667 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 375459 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9787101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5202858 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.152085 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808971 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32603 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.160359 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 808926 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32598 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9241438 # DTB read hits -system.cpu.dtb.read_misses 17791 # DTB read misses +system.cpu.dtb.read_hits 9241313 # DTB read hits +system.cpu.dtb.read_misses 17796 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766265 # DTB read accesses -system.cpu.dtb.write_hits 6385998 # DTB write hits -system.cpu.dtb.write_misses 2317 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298404 # DTB write accesses -system.cpu.dtb.data_hits 15627436 # DTB hits -system.cpu.dtb.data_misses 20108 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064669 # DTB accesses -system.cpu.itb.fetch_hits 4019003 # ITB hits -system.cpu.itb.fetch_misses 6884 # ITB misses -system.cpu.itb.fetch_acv 661 # ITB acv -system.cpu.itb.fetch_accesses 4025887 # ITB accesses +system.cpu.dtb.read_accesses 766310 # DTB read accesses +system.cpu.dtb.write_hits 6385986 # DTB write hits +system.cpu.dtb.write_misses 2327 # DTB write misses +system.cpu.dtb.write_acv 160 # DTB write access violations +system.cpu.dtb.write_accesses 298447 # DTB write accesses +system.cpu.dtb.data_hits 15627299 # DTB hits +system.cpu.dtb.data_misses 20123 # DTB misses +system.cpu.dtb.data_acv 371 # DTB access violations +system.cpu.dtb.data_accesses 1064757 # DTB accesses +system.cpu.itb.fetch_hits 4016976 # ITB hits +system.cpu.itb.fetch_misses 6883 # ITB misses +system.cpu.itb.fetch_acv 674 # ITB acv +system.cpu.itb.fetch_accesses 4023859 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,39 +343,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 175285694 # number of cpu cycles simulated +system.cpu.numCycles 175257245 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56124126 # Number of instructions committed -system.cpu.committedOps 56124126 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2495853 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5575 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593196852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.123179 # CPI: cycles per instruction -system.cpu.ipc 0.320187 # IPC: instructions per cycle +system.cpu.committedInsts 56122640 # Number of instructions committed +system.cpu.committedOps 56122640 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2496382 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5595 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593213949 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.122755 # CPI: cycles per instruction +system.cpu.ipc 0.320230 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211480 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74791 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211475 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105868 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182691 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73424 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73424 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148880 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833816082000 97.32% 97.32% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80474500 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 673053000 0.04% 97.36% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49670669500 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1884240279000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1833807390500 97.32% 97.32% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80545000 0.00% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 673176000 0.04% 97.36% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 49673506000 2.64% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1884234617500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693543 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814928 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693560 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814939 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -409,7 +414,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175532 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175527 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -418,28 +423,28 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192418 # number of callpals executed +system.cpu.kern.callpal::total 192413 # number of callpals executed system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325383 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393986 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36270859500 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4083023000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843886386500 97.86% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.393490 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36258202500 1.92% 1.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4079939000 0.22% 2.14% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1843896466000 97.86% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.tickCycles 84485847 # Number of cycles that the object actually ticked -system.cpu.idleCycles 90799847 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395229 # number of replacements +system.cpu.tickCycles 84474734 # Number of cycles that the object actually ticked +system.cpu.idleCycles 90782511 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395383 # number of replacements system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13773041 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395741 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.867906 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13772439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982334 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy @@ -449,72 +454,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63657366 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63657366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 7814636 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814636 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 5576637 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576637 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182736 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182736 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 7814297 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 5576378 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182732 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 13391273 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13391273 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 13391273 # number of overall hits -system.cpu.dcache.overall_hits::total 13391273 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1201532 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201532 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 573582 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20679395543 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231275750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 51714049793 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 51714049793 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 9015937 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9015937 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 6150141 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150141 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200020 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198999 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 15166387 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15166387 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 15166387 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15166387 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133264 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133264 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093262 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093262 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086411 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086411 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.117043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.117043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25830.964760 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25830.964760 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36089.083233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36089.083233 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13366.118954 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.118954 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29145.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29145.609403 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 15166078 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15166078 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 15166078 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15166078 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133280 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133280 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093293 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093293 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086431 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086431 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.117064 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117064 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.117064 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117064 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25826.915091 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36041.702834 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13377.819875 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29128.062639 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29128.062639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29128.062639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,64 +528,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838115 # number of writebacks -system.cpu.dcache.writebacks::total 838115 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127210 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127210 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269406 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269406 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838265 # number of writebacks +system.cpu.dcache.writebacks::total 838265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127268 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127268 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269487 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269487 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 396616 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396616 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 396616 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396616 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074322 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10259801597 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10259801597 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196291500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196291500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179428847 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37179428847 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179428847 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37179428847 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423887000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423887000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002910000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002910000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426797000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426797000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086396 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086396 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090892 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090892 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25057.317313 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25057.317313 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33729.819568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33729.819568 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11358.804467 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11358.804467 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196537750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196537750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37166642096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37166642096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37166642096 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37166642096 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423897500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423897500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002909000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002909000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426806500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426806500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119164 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119164 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049475 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049475 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086416 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086416 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090903 # 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Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21888154 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21888154 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18970778 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18970778 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18970778 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18970778 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18970778 # number of overall hits -system.cpu.icache.overall_hits::total 18970778 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458688 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458688 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458688 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458688 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458688 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13723.661864 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13723.661864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13723.661864 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -648,115 +653,115 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458688 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1458688 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1458688 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1458688 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1458688 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1458688 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17104729131 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17104729131 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17104729131 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17104729131 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17104729131 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17104729131 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071401 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071401 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071401 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11726.105330 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11726.105330 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11726.105330 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17111152616 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17111152616 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17111152616 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17111152616 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071489 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071489 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071489 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11718.691332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11718.691332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 339435 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65326.200893 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2981535 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404597 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.369148 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 339433 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65325.334655 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2983211 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404595 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.373326 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5873248750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54494.769777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10831.431116 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.831524 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165275 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55536 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1456 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2809 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30249203 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30249203 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2261508 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2261508 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 838115 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 838115 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 30263477 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141928 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141928 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141928 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141928 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65543.688143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65543.688143 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12617.470588 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69228.876705 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69228.876705 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66630.227883 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66630.227883 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69119.344261 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.344261 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66572.913111 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66572.913111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66572.913111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66572.913111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -765,54 +770,54 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76635 # number of writebacks -system.cpu.l2cache.writebacks::total 76635 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288693 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288693 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 76642 # number of writebacks +system.cpu.l2cache.writebacks::total 76642 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288671 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288671 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116655 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116655 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 405348 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405348 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 405348 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405348 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323296500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15323296500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116676 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21931621388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21931621388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21931621388 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21931621388 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333779000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333779000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887481500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887481500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221260500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221260500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6596786889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6596786889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21908431389 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21908431389 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21908431389 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21908431389 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333789500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333789500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887480500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887480500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221270000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221270000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113128 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113128 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383500 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383500 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.142009 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.142009 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53078.171275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53078.171275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383443 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383443 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141928 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141928 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53041.852143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15942 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56648.449599 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56648.449599 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54105.660785 # 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average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -820,42 +825,42 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2557364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558856 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838265 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304285 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917316 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662927 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6580243 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143021148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236373340 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41941 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3734307 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011173 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105112 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920255 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663385 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6583640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93446144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143040604 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236486748 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41944 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3736082 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3692582 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3694357 98.88% 98.88% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3734307 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2697490998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3736082 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698528498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191666369 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2193867384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194528153 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194759654 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -928,7 +933,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406196790 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406197789 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -937,14 +942,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.296059 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.296028 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728026020000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.296059 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081004 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081004 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1728025570000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.296028 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081002 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081002 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -960,8 +965,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635314907 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635314907 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635920906 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13635920906 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles @@ -984,17 +989,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328150.628297 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328150.628297 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206297 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206267 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23564 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23556 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.754753 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.756453 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1010,8 +1015,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474610907 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474610907 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11475216906 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11475216906 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles @@ -1026,57 +1031,57 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276150.628297 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276150.628297 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295796 # Transaction distribution -system.membus.trans_dist::ReadResp 295780 # Transaction distribution +system.membus.trans_dist::ReadReq 295774 # Transaction distribution +system.membus.trans_dist::ReadResp 295758 # Transaction distribution system.membus.trans_dist::WriteReq 9619 # Transaction distribution system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118147 # Transaction distribution +system.membus.trans_dist::Writeback 118154 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 155 # Transaction distribution -system.membus.trans_dist::UpgradeResp 155 # Transaction distribution -system.membus.trans_dist::ReadExReq 116517 # Transaction distribution -system.membus.trans_dist::ReadExResp 116517 # Transaction distribution +system.membus.trans_dist::UpgradeReq 156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 156 # Transaction distribution +system.membus.trans_dist::ReadExReq 116537 # Transaction distribution +system.membus.trans_dist::ReadExResp 116537 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887063 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920193 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044997 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30863900 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30864220 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36180956 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36181276 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 565237 # Request fanout histogram +system.membus.snoop_fanout::samples 565243 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 565237 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 565243 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 565237 # Request fanout histogram -system.membus.reqLayer0.occupancy 30298500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 565243 # Request fanout histogram +system.membus.reqLayer0.occupancy 30308000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1878232500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1878196000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3792450097 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3792332596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |