diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt | 1647 |
1 files changed, 824 insertions, 823 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 6d2c4821a..4852a1186 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.893221 # Number of seconds simulated -sim_ticks 1893220881500 # Number of ticks simulated -final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.893228 # Number of seconds simulated +sim_ticks 1893227633000 # Number of ticks simulated +final_tick 1893227633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25399 # Simulator instruction rate (inst/s) -host_op_rate 25399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 856404595 # Simulator tick rate (ticks/s) -host_mem_usage 393548 # Number of bytes of host memory used -host_seconds 2210.66 # Real time elapsed on the host -sim_insts 56147815 # Number of instructions simulated -sim_ops 56147815 # Number of ops (including micro ops) simulated +host_inst_rate 25790 # Simulator instruction rate (inst/s) +host_op_rate 25790 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 869674472 # Simulator tick rate (ticks/s) +host_mem_usage 393476 # Number of bytes of host memory used +host_seconds 2176.94 # Real time elapsed on the host +sim_insts 56143729 # Number of instructions simulated +sim_ops 56143729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1046208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25907968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7566592 # Number of bytes written to this memory -system.physmem.bytes_written::total 7566592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388450 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25908864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7567040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7567040 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118228 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118228 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 552607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13131484 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404826 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 553315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13131201 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13684599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3996677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3996677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3996677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13131484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13685023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 553315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 553315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3996899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3996899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3996899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 553315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13131201 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17681276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404812 # Number of read requests accepted -system.physmem.writeReqs 118228 # Number of write requests accepted -system.physmem.readBursts 404812 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118228 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25900544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25907968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7566592 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17681922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404826 # Number of read requests accepted +system.physmem.writeReqs 118235 # Number of write requests accepted +system.physmem.readBursts 404826 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118235 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25901888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7565888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25908864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7567040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25483 # Per bank write bursts -system.physmem.perBankRdBursts::1 25705 # Per bank write bursts +system.physmem.perBankRdBursts::0 25487 # Per bank write bursts +system.physmem.perBankRdBursts::1 25708 # Per bank write bursts system.physmem.perBankRdBursts::2 25813 # Per bank write bursts -system.physmem.perBankRdBursts::3 25775 # Per bank write bursts -system.physmem.perBankRdBursts::4 25223 # Per bank write bursts +system.physmem.perBankRdBursts::3 25780 # Per bank write bursts +system.physmem.perBankRdBursts::4 25224 # Per bank write bursts system.physmem.perBankRdBursts::5 24955 # Per bank write bursts system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24583 # Per bank write bursts -system.physmem.perBankRdBursts::8 25108 # Per bank write bursts +system.physmem.perBankRdBursts::7 24580 # Per bank write bursts +system.physmem.perBankRdBursts::8 25111 # Per bank write bursts system.physmem.perBankRdBursts::9 25258 # Per bank write bursts -system.physmem.perBankRdBursts::10 25518 # Per bank write bursts -system.physmem.perBankRdBursts::11 24875 # Per bank write bursts -system.physmem.perBankRdBursts::12 24528 # Per bank write bursts -system.physmem.perBankRdBursts::13 25564 # Per bank write bursts -system.physmem.perBankRdBursts::14 25798 # Per bank write bursts -system.physmem.perBankRdBursts::15 25721 # Per bank write bursts -system.physmem.perBankWrBursts::0 7829 # Per bank write bursts -system.physmem.perBankWrBursts::1 7671 # Per bank write bursts -system.physmem.perBankWrBursts::2 8071 # Per bank write bursts -system.physmem.perBankWrBursts::3 7745 # Per bank write bursts -system.physmem.perBankWrBursts::4 7318 # Per bank write bursts -system.physmem.perBankWrBursts::5 6944 # Per bank write bursts -system.physmem.perBankWrBursts::6 6788 # Per bank write bursts -system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7237 # Per bank write bursts -system.physmem.perBankWrBursts::9 6873 # Per bank write bursts -system.physmem.perBankWrBursts::10 7386 # Per bank write bursts -system.physmem.perBankWrBursts::11 6888 # Per bank write bursts -system.physmem.perBankWrBursts::12 7081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8010 # Per bank write bursts -system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankRdBursts::10 25520 # Per bank write bursts +system.physmem.perBankRdBursts::11 24876 # Per bank write bursts +system.physmem.perBankRdBursts::12 24529 # Per bank write bursts +system.physmem.perBankRdBursts::13 25563 # Per bank write bursts +system.physmem.perBankRdBursts::14 25801 # Per bank write bursts +system.physmem.perBankRdBursts::15 25723 # Per bank write bursts +system.physmem.perBankWrBursts::0 7828 # Per bank write bursts +system.physmem.perBankWrBursts::1 7672 # Per bank write bursts +system.physmem.perBankWrBursts::2 8070 # Per bank write bursts +system.physmem.perBankWrBursts::3 7747 # Per bank write bursts +system.physmem.perBankWrBursts::4 7316 # Per bank write bursts +system.physmem.perBankWrBursts::5 6943 # Per bank write bursts +system.physmem.perBankWrBursts::6 6787 # Per bank write bursts +system.physmem.perBankWrBursts::7 6421 # Per bank write bursts +system.physmem.perBankWrBursts::8 7240 # Per bank write bursts +system.physmem.perBankWrBursts::9 6874 # Per bank write bursts +system.physmem.perBankWrBursts::10 7389 # Per bank write bursts +system.physmem.perBankWrBursts::11 6891 # Per bank write bursts +system.physmem.perBankWrBursts::12 7084 # Per bank write bursts +system.physmem.perBankWrBursts::13 8012 # Per bank write bursts +system.physmem.perBankWrBursts::14 7998 # Per bank write bursts system.physmem.perBankWrBursts::15 7945 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 68 # Number of times write queue was full causing retry -system.physmem.totGap 1893211891000 # Total gap between requests +system.physmem.numWrRetry 56 # Number of times write queue was full causing retry +system.physmem.totGap 1893218679000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404812 # Read request sizes (log2) +system.physmem.readPktSize::6 404826 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118228 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118235 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,206 +149,205 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 528.527867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 322.547536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.556682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14397 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11107 17.54% 40.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4705 7.43% 47.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3113 4.92% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2233 3.53% 56.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2328 3.68% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1953 3.08% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1598 2.52% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21885 34.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63319 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5233 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.334798 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2918.735904 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5230 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 528.007825 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 321.906071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.488828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14518 22.90% 22.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11005 17.36% 40.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4663 7.36% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3176 5.01% 52.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2328 3.67% 56.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2299 3.63% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1937 3.06% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1572 2.48% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21887 34.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63385 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.176964 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2915.674794 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5241 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5233 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5233 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.588955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.741886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.816216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4718 90.16% 90.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.63% 90.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 174 3.33% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 5 0.10% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 12 0.23% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1 0.02% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.61% 95.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 151 2.89% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 15 0.29% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 10 0.19% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 3 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 10 0.19% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 12 0.23% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.17% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 5 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5233 # Writes before turning the bus around for reads -system.physmem.totQLat 5895300250 # Total ticks spent queuing -system.physmem.totMemAccLat 13483350250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14567.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5244 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.543288 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.756988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.319215 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4714 89.89% 89.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 44 0.84% 90.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 176 3.36% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 4 0.08% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 4 0.08% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 12 0.23% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 7 0.13% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 32 0.61% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.10% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 158 3.01% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.27% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 6 0.11% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.08% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 11 0.21% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 14 0.27% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.17% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5244 # Writes before turning the bus around for reads +system.physmem.totQLat 5894702000 # Total ticks spent queuing +system.physmem.totMemAccLat 13483145750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023585000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14565.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33317.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33315.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.81 # Average write queue length when enqueuing -system.physmem.readRowHits 363810 # Number of row buffer hits during reads -system.physmem.writeRowHits 95775 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads +system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing +system.physmem.readRowHits 363769 # Number of row buffer hits during reads +system.physmem.writeRowHits 95780 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes -system.physmem.avgGap 3619631.18 # Average gap between requests -system.physmem.pageHitRate 87.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 221882640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117933420 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1444607640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4693391040.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4737017490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 303974400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10896307530 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 5550083520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 443242644240 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 471515616450 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.054730 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1881921702000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 481983250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1993748000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1843690402750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 14453321750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8706248250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23895177500 # Time in different power states -system.physmem_1.actEnergy 230215020 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122362185 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 310146300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4816933680.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4925461770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 303573120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11119407240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 5660238720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 442986687510 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 471921610125 # Total energy per rank (pJ) -system.physmem_1.averagePower 249.269176 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1881622925500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 484393500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2046440000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1842500290250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 14740166500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9065047000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24384544250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15264339 # Number of BP lookups -system.cpu.branchPred.condPredicted 13122374 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 525708 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12102111 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4571092 # Number of BTB hits +system.physmem.avgGap 3619498.83 # Average gap between requests +system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 221604180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 117785415 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1444679040 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 306852480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4717362000.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4796151000 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 296411520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10938570180 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 5566653120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 443189598645 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 471596477220 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.096553 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1881819292000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 462054000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2003948000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1843451492500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 14496450250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8825649500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23988038750 # Time in different power states +system.physmem_1.actEnergy 230964720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122760660 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1445000340 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 310240260 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4792348080.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4813778250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 297177120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11174584380 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 5627937120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 443035577925 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 471852130095 # Total energy per rank (pJ) +system.physmem_1.averagePower 249.231588 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1881891335250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 468372250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2035962000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1842731534750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 14656099500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8829934000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24505730500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15259378 # Number of BP lookups +system.cpu.branchPred.condPredicted 13119579 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 525820 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12061992 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4569562 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.771030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 863726 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33596 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6525159 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 541190 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5983969 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 222121 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.883975 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 862888 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32219 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6522078 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 538261 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5983817 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 225046 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9321681 # DTB read hits -system.cpu.dtb.read_misses 17691 # DTB read misses +system.cpu.dtb.read_hits 9322510 # DTB read hits +system.cpu.dtb.read_misses 17386 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764795 # DTB read accesses -system.cpu.dtb.write_hits 6394158 # DTB write hits -system.cpu.dtb.write_misses 2442 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298776 # DTB write accesses -system.cpu.dtb.data_hits 15715839 # DTB hits -system.cpu.dtb.data_misses 20133 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1063571 # DTB accesses -system.cpu.itb.fetch_hits 4020046 # ITB hits -system.cpu.itb.fetch_misses 6280 # ITB misses -system.cpu.itb.fetch_acv 699 # ITB acv -system.cpu.itb.fetch_accesses 4026326 # ITB accesses +system.cpu.dtb.read_accesses 764595 # DTB read accesses +system.cpu.dtb.write_hits 6393584 # DTB write hits +system.cpu.dtb.write_misses 2379 # DTB write misses +system.cpu.dtb.write_acv 158 # DTB write access violations +system.cpu.dtb.write_accesses 298734 # DTB write accesses +system.cpu.dtb.data_hits 15716094 # DTB hits +system.cpu.dtb.data_misses 19765 # DTB misses +system.cpu.dtb.data_acv 369 # DTB access violations +system.cpu.dtb.data_accesses 1063329 # DTB accesses +system.cpu.itb.fetch_hits 4018414 # ITB hits +system.cpu.itb.fetch_misses 6313 # ITB misses +system.cpu.itb.fetch_acv 710 # ITB acv +system.cpu.itb.fetch_accesses 4024727 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -361,29 +360,29 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12752 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281786440.323087 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439974345.162947 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 369000 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12750 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281835914.509804 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 440008281.220830 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6375 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 224500 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 96550538000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193121889 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 96523678000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796703955000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 193068084 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56147815 # Number of instructions committed -system.cpu.committedOps 56147815 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2978612 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593319874 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.439526 # CPI: cycles per instruction -system.cpu.ipc 0.290738 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199269 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36201024 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60831 0.11% 70.28% # Class of committed instruction +system.cpu.committedInsts 56143729 # Number of instructions committed +system.cpu.committedOps 56143729 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2983109 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 6375 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593387182 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.438818 # CPI: cycles per instruction +system.cpu.ipc 0.290798 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199033 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36198718 64.48% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60825 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -413,36 +412,36 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9175906 16.34% 86.70% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6235361 11.11% 97.80% # Class of committed instruction +system.cpu.op_class_0::MemRead 9175039 16.34% 86.70% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6234994 11.11% 97.80% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 950928 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56147815 # Class of committed instruction +system.cpu.op_class_0::total 56143729 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211531 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74800 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211453 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74770 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105905 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182741 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73433 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105857 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182663 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73403 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73433 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148902 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837683771000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 86162500 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 712688000 0.04% 97.11% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54737244500 2.89% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1893219866000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73403 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148842 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837707081000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 86418000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 712034000 0.04% 97.11% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54721100500 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1893226633500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981717 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693386 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814825 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693417 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814845 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -450,7 +449,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175574 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175496 91.22% 93.42% # number of callpals executed system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -459,31 +458,31 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192465 # number of callpals executed +system.cpu.kern.callpal::total 192387 # number of callpals executed system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1905 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324255 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324596 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392541 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 37297482500 1.97% 1.97% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4311459500 0.23% 2.20% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1851610914000 97.80% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 37288586500 1.97% 1.97% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4317914500 0.23% 2.20% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1851620122500 97.80% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85352026 # Number of cycles that the object actually ticked -system.cpu.idleCycles 107769863 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394246 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13946627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394758 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.999317 # Average number of references to valid blocks. +system.cpu.tickCycles 85319079 # Number of cycles that the object actually ticked +system.cpu.idleCycles 107749005 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394486 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980102 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13946466 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.997481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980102 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -491,153 +490,153 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63927104 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63927104 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7985415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7985415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183593 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183593 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199022 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199022 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13563977 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563977 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13563977 # number of overall hits -system.cpu.dcache.overall_hits::total 13563977 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096352 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096352 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573692 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573692 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16450 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16450 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1670044 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1670044 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1670044 # number of overall misses -system.cpu.dcache.overall_misses::total 1670044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33571810000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33571810000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25337965000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25337965000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222587500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222587500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 58909775000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 58909775000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 58909775000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 58909775000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9081767 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9081767 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152254 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152254 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200043 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200043 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199022 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199022 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15234021 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15234021 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15234021 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15234021 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120720 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120720 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093249 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109626 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109626 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109626 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109626 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35274.384986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35274.384986 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63927467 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63927467 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7985618 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7985618 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5578297 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5578297 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183538 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183538 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198978 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198978 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13563915 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13563915 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13563915 # number of overall hits +system.cpu.dcache.overall_hits::total 13563915 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096590 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096590 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573634 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573634 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16462 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16462 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670224 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670224 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670224 # number of overall misses +system.cpu.dcache.overall_misses::total 1670224 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33587119500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33587119500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25315634500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25315634500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222567500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222567500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 58902754000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 58902754000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 58902754000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 58902754000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9082208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9082208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151931 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151931 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200000 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200000 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198978 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198978 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15234139 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15234139 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15234139 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15234139 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120740 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120740 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093245 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082310 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082310 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.109637 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109637 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109637 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109637 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30628.693951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30628.693951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44132.032794 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44132.032794 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13520.076540 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13520.076540 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35266.379839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35266.379839 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837664 # number of writebacks -system.cpu.dcache.writebacks::total 837664 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21993 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21993 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269693 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269693 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837775 # number of writebacks +system.cpu.dcache.writebacks::total 837775 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21966 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21966 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269674 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269674 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291686 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291686 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291686 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291686 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074359 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074359 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303999 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303999 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16447 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16447 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378358 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378358 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378358 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378358 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291640 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291640 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291640 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291640 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074624 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074624 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303960 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 303960 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16459 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16459 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378584 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378584 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378584 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378584 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32011150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32011150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12927980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12927980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44939130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44939130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44939130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44939130000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534184500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534184500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534184500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534184500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049413 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049413 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082217 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082217 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090479 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090479 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1477105 # number of replacements -system.cpu.icache.tags.tagsinuse 509.256263 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19233040 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1477616 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.016264 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 36168250500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.256263 # Average occupied blocks per requestor +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32024640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32024640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12912591500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12912591500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44937231500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44937231500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44937231500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44937231500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534181500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534181500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534181500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534181500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049409 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049409 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082295 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082295 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090493 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090493 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29800.786135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29800.786135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42481.219568 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42481.219568 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.798287 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.798287 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221382.611833 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221382.611833 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92682.987978 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92682.987978 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1476860 # number of replacements +system.cpu.icache.tags.tagsinuse 509.256241 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19221452 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1477371 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.010579 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 36168783500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.256241 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -645,319 +644,320 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 104 system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22188623 # Number of tag accesses -system.cpu.icache.tags.data_accesses 22188623 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 19233043 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 19233043 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 19233043 # 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miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071353 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071353 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071353 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071353 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14005.091048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14005.091048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14005.091048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14005.091048 # average overall miss latency +system.cpu.icache.tags.tag_accesses 22176547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 22176547 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 19221455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 19221455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 19221455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 19221455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 19221455 # number of overall hits +system.cpu.icache.overall_hits::total 19221455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1477546 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1477546 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1477546 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1477546 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1477546 # 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mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011063 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249571 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249571 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141070 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141070 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5743946 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871549 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383729 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383729 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249510 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249510 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141075 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141075 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45250 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79881.457794 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79881.457794 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88744.455984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88744.455984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70727.555578 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70727.555578 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208879.653680 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208879.653680 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.559174 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.559174 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5743935 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871442 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2575626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2575661 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914380 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1477105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 914498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1476860 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819632 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1090934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 242 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4432629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217118 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8649747 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189109696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142929468 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332039164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340242 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923392 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3229178 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031158 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 303970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 303970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4431899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8649734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189078592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142951868 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 332030460 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340255 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923648 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3229187 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001046 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032331 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3226040 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3138 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3225808 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3379 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3229178 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5199830000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3229187 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5199690500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 292383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2216814740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2216461215 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2103909988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2104266491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -971,7 +971,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51175 # Transaction distribution @@ -1002,46 +1002,46 @@ system.iobus.pkt_size_system.bridge.master::total 44348 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5417000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5413000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 803500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 807000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 181000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15637500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15127500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6005000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5984000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216245035 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216248283 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.299106 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.299538 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1735874546000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.299106 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081194 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081194 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1735874305000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.299538 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081221 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081221 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1050,14 +1050,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22024383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22024383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948308652 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4948308652 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4970333035 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4970333035 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4970333035 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4970333035 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931902900 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4931902900 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4961787283 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4961787283 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4961787283 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4961787283 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1074,19 +1074,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127308.572254 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119121.223128 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119121.223128 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1402 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118692.310839 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118692.310839 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118916.411815 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118916.411815 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 107.846154 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 111.625000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1098,14 +1098,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13374383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13374383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868251757 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2868251757 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2881626140 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2881626140 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2881626140 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2881626140 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851851307 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2851851307 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2873085690 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2873085690 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2873085690 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2873085690 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1114,75 +1114,76 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827498 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381477 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68633.310238 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68633.310238 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827515 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381393 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295653 # Transaction distribution +system.membus.trans_dist::ReadResp 295677 # Transaction distribution system.membus.trans_dist::WriteReq 9623 # Transaction distribution system.membus.trans_dist::WriteResp 9623 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118228 # Transaction distribution -system.membus.trans_dist::CleanEvict 262245 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118235 # Transaction distribution +system.membus.trans_dist::CleanEvict 262254 # Transaction distribution system.membus.trans_dist::UpgradeReq 138 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 116520 # Transaction distribution -system.membus.trans_dist::ReadExResp 116520 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288747 # Transaction distribution -system.membus.trans_dist::BadAddressError 24 # Transaction distribution +system.membus.trans_dist::ReadExReq 116510 # Transaction distribution +system.membus.trans_dist::ReadExResp 116510 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288770 # Transaction distribution +system.membus.trans_dist::BadAddressError 23 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 127 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181947 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148837 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181989 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265414 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30861180 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30818176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30862524 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33518908 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 434 # Total snoops (count) +system.membus.pkt_size::total 33520252 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 561 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463510 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001463 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038218 # Request fanout histogram +system.membus.snoop_fanout::samples 463523 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001461 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038189 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462846 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463510 # Request fanout histogram -system.membus.reqLayer0.occupancy 30461000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463523 # Request fanout histogram +system.membus.reqLayer0.occupancy 29930000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319556082 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319547835 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160064000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160176250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1081022 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1214,28 +1215,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |