diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor')
5 files changed, 0 insertions, 3156 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini deleted file mode 100644 index 961681a43..000000000 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini +++ /dev/null @@ -1,1784 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:134217727:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr deleted file mode 100755 index a8a3639b1..000000000 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout deleted file mode 100755 index 98915ba59..000000000 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28076 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-minor - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1893220881500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt deleted file mode 100644 index 75078a9be..000000000 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ /dev/null @@ -1,1243 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.893228 # Number of seconds simulated -sim_ticks 1893227678500 # Number of ticks simulated -final_tick 1893227678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31053 # Simulator instruction rate (inst/s) -host_op_rate 31053 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1047239405 # Simulator tick rate (ticks/s) -host_mem_usage 384600 # Number of bytes of host memory used -host_seconds 1807.83 # Real time elapsed on the host -sim_insts 56138739 # Number of instructions simulated -sim_ops 56138739 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1046400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25907712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory -system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404808 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 552707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13131200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13684414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3996629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3996629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3996629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13131200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17681043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404808 # Number of read requests accepted -system.physmem.writeReqs 118227 # Number of write requests accepted -system.physmem.readBursts 404808 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue -system.physmem.bytesWritten 7564480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25907712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25487 # Per bank write bursts -system.physmem.perBankRdBursts::1 25708 # Per bank write bursts -system.physmem.perBankRdBursts::2 25811 # Per bank write bursts -system.physmem.perBankRdBursts::3 25775 # Per bank write bursts -system.physmem.perBankRdBursts::4 25223 # Per bank write bursts -system.physmem.perBankRdBursts::5 24955 # Per bank write bursts -system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24582 # Per bank write bursts -system.physmem.perBankRdBursts::8 25110 # Per bank write bursts -system.physmem.perBankRdBursts::9 25258 # Per bank write bursts -system.physmem.perBankRdBursts::10 25516 # Per bank write bursts -system.physmem.perBankRdBursts::11 24876 # Per bank write bursts -system.physmem.perBankRdBursts::12 24528 # Per bank write bursts -system.physmem.perBankRdBursts::13 25560 # Per bank write bursts -system.physmem.perBankRdBursts::14 25799 # Per bank write bursts -system.physmem.perBankRdBursts::15 25723 # Per bank write bursts -system.physmem.perBankWrBursts::0 7831 # Per bank write bursts -system.physmem.perBankWrBursts::1 7673 # Per bank write bursts -system.physmem.perBankWrBursts::2 8069 # Per bank write bursts -system.physmem.perBankWrBursts::3 7745 # Per bank write bursts -system.physmem.perBankWrBursts::4 7318 # Per bank write bursts -system.physmem.perBankWrBursts::5 6942 # Per bank write bursts -system.physmem.perBankWrBursts::6 6789 # Per bank write bursts -system.physmem.perBankWrBursts::7 6426 # Per bank write bursts -system.physmem.perBankWrBursts::8 7239 # Per bank write bursts -system.physmem.perBankWrBursts::9 6872 # Per bank write bursts -system.physmem.perBankWrBursts::10 7384 # Per bank write bursts -system.physmem.perBankWrBursts::11 6889 # Per bank write bursts -system.physmem.perBankWrBursts::12 7081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8010 # Per bank write bursts -system.physmem.perBankWrBursts::14 7995 # Per bank write bursts -system.physmem.perBankWrBursts::15 7932 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 72 # Number of times write queue was full causing retry -system.physmem.totGap 1893218795000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404808 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118227 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 189 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63391 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 527.918474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 322.301426 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.348187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14401 22.72% 22.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11109 17.52% 40.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4782 7.54% 47.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3159 4.98% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2221 3.50% 56.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2316 3.65% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1932 3.05% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1599 2.52% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21872 34.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63391 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.317348 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2918.457754 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5231 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5234 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5234 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.582155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.722612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.927693 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4724 90.26% 90.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 39 0.75% 91.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 163 3.11% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 4 0.08% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 11 0.21% 94.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 33 0.63% 95.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 144 2.75% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 23 0.44% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 9 0.17% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.06% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 7 0.13% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 10 0.19% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.10% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 14 0.27% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.19% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.06% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 5 0.10% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-359 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5234 # Writes before turning the bus around for reads -system.physmem.totQLat 5912751750 # Total ticks spent queuing -system.physmem.totMemAccLat 13500876750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14610.21 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33360.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing -system.physmem.readRowHits 363798 # Number of row buffer hits during reads -system.physmem.writeRowHits 95706 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.95 # Row buffer hit rate for writes -system.physmem.avgGap 3619678.98 # Average gap between requests -system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 222139680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 118070040 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1444636200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4706913120.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4768209600 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 303610560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10937646210 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 5541404160 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 443214367815 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 471564552855 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.079684 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1881862215000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 479498250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1999510000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1843562153500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 14430696500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8769616250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23986204000 # Time in different power states -system.physmem_1.actEnergy 230472060 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122498805 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 310078440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4819392240.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4890695190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 314585760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11137759530 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 5641159680 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 443008801920 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 471922426215 # Total energy per rank (pJ) -system.physmem_1.averagePower 249.268712 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1881676600250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 514596250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2047516000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1842563195250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 14690458500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8987140500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24424772000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15251875 # Number of BP lookups -system.cpu.branchPred.condPredicted 13114549 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 526465 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12070936 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4577345 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.920382 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 863154 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33512 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6526029 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 541717 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5984312 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 221941 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9319487 # DTB read hits -system.cpu.dtb.read_misses 17755 # DTB read misses -system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764786 # DTB read accesses -system.cpu.dtb.write_hits 6392965 # DTB write hits -system.cpu.dtb.write_misses 2560 # DTB write misses -system.cpu.dtb.write_acv 158 # DTB write access violations -system.cpu.dtb.write_accesses 298884 # DTB write accesses -system.cpu.dtb.data_hits 15712452 # DTB hits -system.cpu.dtb.data_misses 20315 # DTB misses -system.cpu.dtb.data_acv 369 # DTB access violations -system.cpu.dtb.data_accesses 1063670 # DTB accesses -system.cpu.itb.fetch_hits 4023125 # ITB hits -system.cpu.itb.fetch_misses 6293 # ITB misses -system.cpu.itb.fetch_acv 687 # ITB acv -system.cpu.itb.fetch_accesses 4029418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12752 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281784609.786700 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439970621.768515 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 121000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 96569006500 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796658672000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193159059 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56138739 # Number of instructions committed -system.cpu.committedOps 56138739 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2973387 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593296298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.440745 # CPI: cycles per instruction -system.cpu.ipc 0.290635 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199075 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36194440 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60814 0.11% 70.28% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::MemRead 9174678 16.34% 86.70% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6234348 11.11% 97.80% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951192 1.69% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56138739 # Class of committed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211522 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74796 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105900 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182732 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73429 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73429 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148894 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837688968000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 86405500 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 711997500 0.04% 97.11% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54739315500 2.89% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1893226686500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693381 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814822 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175565 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192456 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches -system.cpu.kern.mode_switch::user 1736 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1904 -system.cpu.kern.mode_good::user 1736 -system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324085 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392375 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 37303090500 1.97% 1.97% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4315388500 0.23% 2.20% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1851608197500 97.80% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85358190 # Number of cycles that the object actually ticked -system.cpu.idleCycles 107800869 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394352 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13943564 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394864 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.996361 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63916074 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63916074 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7983580 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7983580 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5577346 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5577346 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183586 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183586 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199016 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199016 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13560926 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13560926 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13560926 # number of overall hits -system.cpu.dcache.overall_hits::total 13560926 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096421 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096421 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573901 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573901 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16452 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16452 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1670322 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1670322 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1670322 # number of overall misses -system.cpu.dcache.overall_misses::total 1670322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33580747500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33580747500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25364054000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25364054000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223095000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 223095000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 58944801500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 58944801500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 58944801500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 58944801500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9080001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9080001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151247 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151247 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200038 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200038 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199016 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199016 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15231248 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15231248 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15231248 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15231248 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120751 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093298 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093298 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082244 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082244 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109664 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109664 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109664 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109664 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30627.603357 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30627.603357 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44195.870019 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44195.870019 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.357403 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.357403 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35289.484004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35289.484004 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837673 # number of writebacks -system.cpu.dcache.writebacks::total 837673 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269878 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269878 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291859 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291859 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291859 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291859 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074440 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074440 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304023 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304023 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16449 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16449 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378463 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378463 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378463 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378463 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32016506000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32016506000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12938125500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12938125500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205942500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205942500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44954631500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44954631500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44954631500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44954631500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534159000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534159000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534159000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534159000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118330 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118330 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049425 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049425 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082229 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082229 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090502 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090502 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29798.319124 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29798.319124 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42556.403627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42556.403627 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12520.062010 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12520.062010 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.365079 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.365079 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92681.628708 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92681.628708 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1477259 # number of replacements -system.cpu.icache.tags.tagsinuse 509.256262 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19240724 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1477770 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.020107 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 36168160500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.256262 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22196619 # Number of tag accesses -system.cpu.icache.tags.data_accesses 22196619 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 19240727 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 19240727 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 19240727 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 19240727 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 19240727 # number of overall hits -system.cpu.icache.overall_hits::total 19240727 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1477946 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1477946 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1477946 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1477946 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1477946 # number of overall misses -system.cpu.icache.overall_misses::total 1477946 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20694155000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20694155000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20694155000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20694155000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20694155000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20694155000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20718673 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20718673 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20718673 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20718673 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20718673 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20718673 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071334 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071334 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071334 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071334 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071334 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14001.969625 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14001.969625 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14001.969625 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14001.969625 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1477259 # number of writebacks -system.cpu.icache.writebacks::total 1477259 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477946 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1477946 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1477946 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1477946 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1477946 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1477946 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19216209000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19216209000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19216209000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19216209000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19216209000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19216209000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071334 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071334 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071334 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13001.969625 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13001.969625 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 339629 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65408.640121 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5336861 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.172523 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6812650000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 268.308507 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5784.509565 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.822049 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088265 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.905698 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59336 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46345268 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46345268 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 837673 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 837673 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1476684 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1476684 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187384 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187384 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461541 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 32476404000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34090306000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 837673 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 837673 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1476684 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1476684 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304034 # 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miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.272727 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383674 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383674 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011064 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011064 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249548 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249548 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011064 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278783 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141056 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011064 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278783 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141056 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55250 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90087.132447 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90087.132447 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98703.565531 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98703.565531 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80698.182727 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80698.182727 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84127.480739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84127.480739 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 76715 # number of writebacks -system.cpu.l2cache.writebacks::total 76715 # number of writebacks -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16351 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16351 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272221 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272221 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16351 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405222 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16351 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388871 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405222 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9342164000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9342164000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1450392000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1450392000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19248668000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19248668000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1450392000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28590832000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30041224000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1450392000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28590832000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30041224000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383674 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383674 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011064 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249548 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249548 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141056 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141056 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45250 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80087.132447 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80087.132447 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88703.565531 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88703.565531 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70709.710125 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70709.710125 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87447.290521 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87447.290521 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5744469 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871707 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2575864 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914388 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1477259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819593 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433097 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217440 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8650537 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189129664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142936828 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332066492 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340239 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923200 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3229438 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001049 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032373 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3226050 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3229438 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5200254500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2217065706 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2104067991 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51175 # Transaction distribution -system.iobus.trans_dist::WriteResp 51175 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5413500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 792000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15611000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5971500 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216263272 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.299521 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1735874841000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.299521 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081220 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081220 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948356889 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4948356889 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4978241272 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4978241272 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4978241272 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4978241272 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119088.296327 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119088.296327 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119310.755470 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119310.755470 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1846 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 14 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 131.857143 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868303297 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2868303297 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2889537680 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2889537680 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2889537680 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2889537680 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69029.247617 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69029.247617 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827499 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381391 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295651 # Transaction distribution -system.membus.trans_dist::WriteReq 9623 # Transaction distribution -system.membus.trans_dist::WriteResp 9623 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution -system.membus.trans_dist::CleanEvict 262247 # Transaction distribution -system.membus.trans_dist::UpgradeReq 138 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 116518 # Transaction distribution -system.membus.trans_dist::ReadExResp 116518 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution -system.membus.trans_dist::BadAddressError 24 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 124 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181940 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265365 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33518588 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 558 # Total snoops (count) -system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463506 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001454 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038105 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 674 0.15% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463506 # Request fanout histogram -system.membus.reqLayer0.occupancy 30386000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319436087 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160035750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1079521 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal deleted file mode 100644 index b49f55c8a..000000000 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal +++ /dev/null @@ -1,108 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 -
Got Configuration 623 -
memsize 8000000 pages 4000 -
First free page after ROM 0xFFFFFC0000018000 -
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 -
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 -
CPU Clock at 2000 MHz IntrClockFrequency=1024 -
Booting with 1 processor(s) -
KSP: 0x20043FE8 PTBR 0x20 -
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 -
Memory cluster 0 [0 - 392] -
Memory cluster 1 [392 - 15992] -
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 -
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 -
unix_boot_mem ends at FFFFFC0000076000 -
k_argc = 0 -
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) -
CallbackFixup 0 18000, t7=FFFFFC000070C000 -
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 -
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM -
Major Options: SMP LEGACY_START VERBOSE_MCHECK -
Command line: root=/dev/hda1 console=ttyS0 -
memcluster 0, usage 1, start 0, end 392 -
memcluster 1, usage 0, start 392, end 16384 -
freeing pages 1069:16384 -
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles -
SMP: 1 CPUs probed -- cpu_present_mask = 1 -
Built 1 zonelists -
Kernel command line: root=/dev/hda1 console=ttyS0 -
PID hash table entries: 1024 (order: 10, 32768 bytes) -
Using epoch = 1900 -
Console: colour dummy device 80x25 -
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) -
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) -
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) -
Mount-cache hash table entries: 512 -
SMP mode deactivated. -
Brought up 1 CPUs -
SMP: Total of 1 processors activated (4002.20 BogoMIPS). -
NET: Registered protocol family 16 -
EISA bus registered -
pci: enabling save/restore of SRM state -
SCSI subsystem initialized -
srm_env: version 0.0.5 loaded successfully -
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -
Initializing Cryptographic API -
rtc: Standard PC (1900) epoch (1900) detected -
Real Time Clock Driver v1.12 -
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled -
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 -
io scheduler noop registered -
io scheduler anticipatory registered -
io scheduler deadline registered -
io scheduler cfq registered -
loop: loaded (max 8 devices) -
nbd: registered device at major 43 -
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. -
PCI: Setting latency timer of device 0000:00:01.0 to 64 -
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 -
eth0: enabling optical transceiver -
eth0: using 64 bit addressing. -
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg -
tun: Universal TUN/TAP device driver, 1.6 -
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> -
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 -
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -
PIIX4: IDE controller at PCI slot 0000:00:00.0 -
PIIX4: chipset revision 0 -
PIIX4: 100% native mode on irq 31 -
PCI: Setting latency timer of device 0000:00:00.0 to 64 -
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA -
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA -
hda: M5 IDE Disk, ATA DISK drive -
hdb: M5 IDE Disk, ATA DISK drive -
ide0 at 0x8410-0x8417,0x8422 on irq 31 -
hda: max request size: 128KiB -
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) -
hda: cache flushes not supported -
hda: hda1 -
hdb: max request size: 128KiB -
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) -
hdb: cache flushes not supported -
hdb: unknown partition table -
mice: PS/2 mouse device common for all mice -
NET: Registered protocol family 2 -
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) -
TCP established hash table entries: 16384 (order: 5, 262144 bytes) -
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) -
TCP: Hash tables configured (established 16384 bind 16384) -
TCP reno registered -
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack -
ip_tables: (C) 2000-2002 Netfilter core team -
arp_tables: (C) 2002 David S. Miller -
TCP bic registered -
Initializing IPsec netlink socket -
NET: Registered protocol family 1 -
NET: Registered protocol family 17 -
NET: Registered protocol family 15 -
Bridge firewalling registered -
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> -
All bugs added by David S. Miller <davem@redhat.com> -
VFS: Mounted root (ext2 filesystem) readonly. -
Freeing unused kernel memory: 224k freed -
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script...
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