diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3976 |
1 files changed, 1993 insertions, 1983 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index dad37454b..e5b1b4540 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.904438 # Number of seconds simulated -sim_ticks 1904437574000 # Number of ticks simulated -final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.907980 # Number of seconds simulated +sim_ticks 1907980084000 # Number of ticks simulated +final_tick 1907980084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149880 # Simulator instruction rate (inst/s) -host_op_rate 149880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5044505517 # Simulator tick rate (ticks/s) -host_mem_usage 380636 # Number of bytes of host memory used -host_seconds 377.53 # Real time elapsed on the host -sim_insts 56583768 # Number of instructions simulated -sim_ops 56583768 # Number of ops (including micro ops) simulated +host_inst_rate 144634 # Simulator instruction rate (inst/s) +host_op_rate 144633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4918211693 # Simulator tick rate (ticks/s) +host_mem_usage 381420 # Number of bytes of host memory used +host_seconds 387.94 # Real time elapsed on the host +sim_insts 56109384 # Number of instructions simulated +sim_ops 56109384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 744000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 236608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1227584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26394240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory -system.physmem.bytes_written::total 7983616 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26347648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 744000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 236608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7952896 # Number of bytes written to this memory +system.physmem.bytes_written::total 7952896 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 19181 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412410 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory -system.physmem.num_writes::total 124744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412410 # Number of read requests accepted -system.physmem.writeReqs 166296 # Number of write requests accepted -system.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25681 # Per bank write bursts -system.physmem.perBankRdBursts::1 26031 # Per bank write bursts -system.physmem.perBankRdBursts::2 26262 # Per bank write bursts -system.physmem.perBankRdBursts::3 25929 # Per bank write bursts -system.physmem.perBankRdBursts::4 25778 # Per bank write bursts -system.physmem.perBankRdBursts::5 25597 # Per bank write bursts -system.physmem.perBankRdBursts::6 26273 # Per bank write bursts -system.physmem.perBankRdBursts::7 25295 # Per bank write bursts -system.physmem.perBankRdBursts::8 25970 # Per bank write bursts -system.physmem.perBankRdBursts::9 26150 # Per bank write bursts -system.physmem.perBankRdBursts::10 25721 # Per bank write bursts -system.physmem.perBankRdBursts::11 25208 # Per bank write bursts -system.physmem.perBankRdBursts::12 25640 # Per bank write bursts -system.physmem.perBankRdBursts::13 25768 # Per bank write bursts +system.physmem.num_reads::total 411682 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124264 # Number of write requests responded to by this memory +system.physmem.num_writes::total 124264 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 389941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12651335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 124010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 643395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13809184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 124010 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4168228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4168228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4168228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12651335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 124010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 643395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17977412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411682 # Number of read requests accepted +system.physmem.writeReqs 124264 # Number of write requests accepted +system.physmem.readBursts 411682 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 124264 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26340672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7951552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26347648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7952896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 45002 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25908 # Per bank write bursts +system.physmem.perBankRdBursts::1 25789 # Per bank write bursts +system.physmem.perBankRdBursts::2 26010 # Per bank write bursts +system.physmem.perBankRdBursts::3 25614 # Per bank write bursts +system.physmem.perBankRdBursts::4 25643 # Per bank write bursts +system.physmem.perBankRdBursts::5 25797 # Per bank write bursts +system.physmem.perBankRdBursts::6 25922 # Per bank write bursts +system.physmem.perBankRdBursts::7 25550 # Per bank write bursts +system.physmem.perBankRdBursts::8 25897 # Per bank write bursts +system.physmem.perBankRdBursts::9 25701 # Per bank write bursts +system.physmem.perBankRdBursts::10 25484 # Per bank write bursts +system.physmem.perBankRdBursts::11 25508 # Per bank write bursts +system.physmem.perBankRdBursts::12 25696 # Per bank write bursts +system.physmem.perBankRdBursts::13 25817 # Per bank write bursts system.physmem.perBankRdBursts::14 25547 # Per bank write bursts -system.physmem.perBankRdBursts::15 25457 # Per bank write bursts -system.physmem.perBankWrBursts::0 9358 # Per bank write bursts -system.physmem.perBankWrBursts::1 9077 # Per bank write bursts -system.physmem.perBankWrBursts::2 9200 # Per bank write bursts -system.physmem.perBankWrBursts::3 8756 # Per bank write bursts -system.physmem.perBankWrBursts::4 8419 # Per bank write bursts -system.physmem.perBankWrBursts::5 8251 # Per bank write bursts -system.physmem.perBankWrBursts::6 9072 # Per bank write bursts -system.physmem.perBankWrBursts::7 8046 # Per bank write bursts -system.physmem.perBankWrBursts::8 8692 # Per bank write bursts -system.physmem.perBankWrBursts::9 8978 # Per bank write bursts -system.physmem.perBankWrBursts::10 8574 # Per bank write bursts -system.physmem.perBankWrBursts::11 8968 # Per bank write bursts -system.physmem.perBankWrBursts::12 8555 # Per bank write bursts -system.physmem.perBankWrBursts::13 9260 # Per bank write bursts -system.physmem.perBankWrBursts::14 8896 # Per bank write bursts -system.physmem.perBankWrBursts::15 8762 # Per bank write bursts +system.physmem.perBankRdBursts::15 25690 # Per bank write bursts +system.physmem.perBankWrBursts::0 7970 # Per bank write bursts +system.physmem.perBankWrBursts::1 7556 # Per bank write bursts +system.physmem.perBankWrBursts::2 7711 # Per bank write bursts +system.physmem.perBankWrBursts::3 7606 # Per bank write bursts +system.physmem.perBankWrBursts::4 7633 # Per bank write bursts +system.physmem.perBankWrBursts::5 7951 # Per bank write bursts +system.physmem.perBankWrBursts::6 7934 # Per bank write bursts +system.physmem.perBankWrBursts::7 7815 # Per bank write bursts +system.physmem.perBankWrBursts::8 8060 # Per bank write bursts +system.physmem.perBankWrBursts::9 8044 # Per bank write bursts +system.physmem.perBankWrBursts::10 7565 # Per bank write bursts +system.physmem.perBankWrBursts::11 7446 # Per bank write bursts +system.physmem.perBankWrBursts::12 7634 # Per bank write bursts +system.physmem.perBankWrBursts::13 8000 # Per bank write bursts +system.physmem.perBankWrBursts::14 7754 # Per bank write bursts +system.physmem.perBankWrBursts::15 7564 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 1904433039500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1907975777500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412410 # Read request sizes (log2) +system.physmem.readPktSize::6 411682 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 166296 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124264 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,200 +158,204 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 46 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65129 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.524774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.940318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.518091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14691 22.56% 22.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11476 17.62% 40.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5283 8.11% 48.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3332 5.12% 53.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2563 3.94% 57.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1696 2.60% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1442 2.21% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1386 2.13% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23260 35.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65129 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5620 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.233096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2814.761745 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5617 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads -system.physmem.totQLat 4111304500 # Total ticks spent queuing -system.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5620 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.107295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.769658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.265728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4863 86.53% 86.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 151 2.69% 89.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 190 3.38% 92.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 20 0.36% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 26 0.46% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 52 0.93% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.25% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.04% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.04% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.11% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.12% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.14% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.05% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.14% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 8 0.14% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 26 0.46% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 16 0.28% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 144 2.56% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.21% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.04% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 7 0.12% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5620 # Writes before turning the bus around for reads +system.physmem.totQLat 4128600500 # Total ticks spent queuing +system.physmem.totMemAccLat 11845594250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2057865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10031.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28781.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing -system.physmem.readRowHits 371693 # Number of row buffer hits during reads -system.physmem.writeRowHits 115102 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes -system.physmem.avgGap 3290847.23 # Average gap between requests -system.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.325620 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states -system.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 2.21 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.72 # Average write queue length when enqueuing +system.physmem.readRowHits 370844 # Number of row buffer hits during reads +system.physmem.writeRowHits 99842 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.35 # Row buffer hit rate for writes +system.physmem.avgGap 3560014.96 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1608188400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 402589440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57486510675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1094357699250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278853275255 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.267627 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1820391723000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63711440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23872193000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.317995 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states -system.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states +system.physmem_1.actEnergy 247287600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134928750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1601652000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 402194160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57648050955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1094215997250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278869687355 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.276229 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1820158780750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63711440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24103898000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16050181 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits +system.cpu0.branchPred.lookups 11788808 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10301623 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 235567 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7623393 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4144660 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.367655 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 590548 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 12472 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9185685 # DTB read hits -system.cpu0.dtb.read_misses 31794 # DTB read misses -system.cpu0.dtb.read_acv 464 # DTB read access violations -system.cpu0.dtb.read_accesses 674724 # DTB read accesses -system.cpu0.dtb.write_hits 5856177 # DTB write hits -system.cpu0.dtb.write_misses 6642 # DTB write misses -system.cpu0.dtb.write_acv 308 # DTB write access violations -system.cpu0.dtb.write_accesses 220970 # DTB write accesses -system.cpu0.dtb.data_hits 15041862 # DTB hits -system.cpu0.dtb.data_misses 38436 # DTB misses -system.cpu0.dtb.data_acv 772 # DTB access violations -system.cpu0.dtb.data_accesses 895694 # DTB accesses -system.cpu0.itb.fetch_hits 1413849 # ITB hits -system.cpu0.itb.fetch_misses 27924 # ITB misses -system.cpu0.itb.fetch_acv 522 # ITB acv -system.cpu0.itb.fetch_accesses 1441773 # ITB accesses +system.cpu0.dtb.read_hits 7021210 # DTB read hits +system.cpu0.dtb.read_misses 28922 # DTB read misses +system.cpu0.dtb.read_acv 549 # DTB read access violations +system.cpu0.dtb.read_accesses 680178 # DTB read accesses +system.cpu0.dtb.write_hits 4516223 # DTB write hits +system.cpu0.dtb.write_misses 6969 # DTB write misses +system.cpu0.dtb.write_acv 383 # DTB write access violations +system.cpu0.dtb.write_accesses 234540 # DTB write accesses +system.cpu0.dtb.data_hits 11537433 # DTB hits +system.cpu0.dtb.data_misses 35891 # DTB misses +system.cpu0.dtb.data_acv 932 # DTB access violations +system.cpu0.dtb.data_accesses 914718 # DTB accesses +system.cpu0.itb.fetch_hits 1192769 # ITB hits +system.cpu0.itb.fetch_misses 29243 # ITB misses +system.cpu0.itb.fetch_acv 632 # ITB acv +system.cpu0.itb.fetch_accesses 1222012 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -364,595 +368,598 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 115311619 # number of cpu cycles simulated +system.cpu0.numCycles 94258709 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18560589 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 53027757 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11788808 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4735208 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 69979824 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 806070 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 422 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1456351 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 296845 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 178 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6342869 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 170274 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 90723047 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.584501 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.854201 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 80634947 88.88% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 672953 0.74% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1448081 1.60% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 584574 0.64% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2111688 2.33% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 463915 0.51% 94.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 450869 0.50% 95.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 614781 0.68% 95.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3741239 4.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6621677 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 90723047 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.125069 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.562577 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 14977569 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 67686915 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6257157 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1423439 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 377966 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 370983 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 25389 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 46677806 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 79994 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 377966 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 15660908 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 46083028 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14369152 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6948168 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7283823 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 45068314 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 191995 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1547824 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 115834 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4229403 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 30289226 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 55138176 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 55047778 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 82793 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26689501 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 3599717 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1126936 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 168790 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10038208 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7066684 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4739993 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1073845 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 760534 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 40346624 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1418133 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 39715880 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 51531 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 4979263 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2318512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 978590 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 90723047 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.437771 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.168840 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74240349 81.83% 81.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7278177 8.02% 89.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3014429 3.32% 93.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2002130 2.21% 95.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2057446 2.27% 97.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1059416 1.17% 98.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 709655 0.78% 99.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 273899 0.30% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 87546 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 90723047 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 128942 17.20% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 362987 48.42% 65.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 257779 34.38% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 27155018 68.37% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 40485 0.10% 68.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.48% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25259 0.06% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7282480 18.34% 86.89% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4576355 11.52% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 630612 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued -system.cpu0.iq.rate 0.453068 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61357419 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 279378 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 39715880 # Type of FU issued +system.cpu0.iq.rate 0.421350 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 749708 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018877 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 170597233 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 46586090 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38643243 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 358812 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 172505 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 165745 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 40269961 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 191839 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 469267 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 864378 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3380 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 14864 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 401917 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 11804 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 365714 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 377966 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 43619498 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 675796 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 44202753 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 88904 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7066684 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4739993 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1257449 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 23012 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 538948 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 14864 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 117466 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 265776 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 383242 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 39342618 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7067139 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 373261 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3391780 # number of nop insts executed -system.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8225133 # Number of branches executed -system.cpu0.iew.exec_stores 5876205 # Number of stores executed -system.cpu0.iew.exec_rate 0.448685 # Inst execution rate -system.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26435135 # num instructions producing a value -system.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value +system.cpu0.iew.exec_nop 2437996 # number of nop insts executed +system.cpu0.iew.exec_refs 11599884 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6171265 # Number of branches executed +system.cpu0.iew.exec_stores 4532745 # Number of stores executed +system.cpu0.iew.exec_rate 0.417390 # Inst execution rate +system.cpu0.iew.wb_sent 38908729 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38808988 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 20149850 # num instructions producing a value +system.cpu0.iew.wb_consumers 27578035 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.411728 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.730649 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5183738 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 439543 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 349838 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 89803768 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.433386 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.354442 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 76032999 84.67% 84.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5542678 6.17% 90.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2869062 3.19% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1578965 1.76% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1284314 1.43% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 412798 0.46% 97.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 324191 0.36% 98.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 314453 0.35% 98.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1444308 1.61% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51332073 # Number of instructions committed -system.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 89803768 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 38919724 # Number of instructions committed +system.cpu0.commit.committedOps 38919724 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13832347 # Number of memory references committed -system.cpu0.commit.loads 8208434 # Number of loads committed -system.cpu0.commit.membars 200823 # Number of memory barriers committed -system.cpu0.commit.branches 7767218 # Number of branches committed -system.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47526784 # Number of committed integer instructions. -system.cpu0.commit.function_calls 660195 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction +system.cpu0.commit.refs 10540382 # Number of memory references committed +system.cpu0.commit.loads 6202306 # Number of loads committed +system.cpu0.commit.membars 144405 # Number of memory barriers committed +system.cpu0.commit.branches 5839773 # Number of branches committed +system.cpu0.commit.fp_insts 162063 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 36166381 # Number of committed integer instructions. +system.cpu0.commit.function_calls 471449 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2138002 5.49% 5.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 25394964 65.25% 70.74% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39484 0.10% 70.84% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24801 0.06% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6346711 16.31% 87.22% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 4343267 11.16% 98.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 630612 1.62% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 165216916 # The number of ROB reads -system.cpu0.rob.rob_writes 117798939 # The number of ROB writes -system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48375955 # Number of Instructions Simulated -system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67964697 # number of integer regfile reads -system.cpu0.int_regfile_writes 37032803 # number of integer regfile writes -system.cpu0.fp_regfile_reads 135608 # number of floating regfile reads -system.cpu0.fp_regfile_writes 136877 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads -system.cpu0.misc_regfile_writes 821150 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1283357 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits -system.cpu0.dcache.overall_hits::total 10231407 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses -system.cpu0.dcache.overall_misses::total 3310446 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked +system.cpu0.commit.op_class_0::total 38919724 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1444308 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 132264444 # The number of ROB reads +system.cpu0.rob.rob_writes 89122078 # The number of ROB writes +system.cpu0.timesIdled 337516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3535662 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3721701460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 36785489 # Number of Instructions Simulated +system.cpu0.committedOps 36785489 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.562388 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.562388 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.390261 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390261 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 51878765 # number of integer regfile reads +system.cpu0.int_regfile_writes 28204778 # number of integer regfile writes +system.cpu0.fp_regfile_reads 81728 # number of floating regfile reads +system.cpu0.fp_regfile_writes 81429 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1387632 # number of misc regfile reads +system.cpu0.misc_regfile_writes 636485 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 898491 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.994698 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 8012262 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 899003 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.912386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.994698 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.941396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 43230678 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 43230678 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5046736 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5046736 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 2679789 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2679789 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129628 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 129628 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149296 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149296 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7726525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7726525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7726525 # number of overall hits +system.cpu0.dcache.overall_hits::total 7726525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1067598 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1067598 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1496200 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1496200 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12202 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12202 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 769 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 769 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2563798 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2563798 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2563798 # number of overall misses +system.cpu0.dcache.overall_misses::total 2563798 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 32014122500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 32014122500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69455032918 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 69455032918 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 190587000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 190587000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5445000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5445000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 101469155418 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 101469155418 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6114334 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6114334 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4175989 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4175989 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 141830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 141830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150065 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 150065 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10290323 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10290323 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10290323 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10290323 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.174606 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.174606 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358286 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.358286 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086033 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086033 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005124 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005124 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249147 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249147 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249147 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249147 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7080.624187 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7080.624187 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4094264 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5021 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 103728 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 39.471155 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 53.414894 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks -system.cpu0.dcache.writebacks::total 752753 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7039 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17071 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 40869593877 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 40869593877 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 40869593877 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 40869593877 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1464167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1464167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129748498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2129748498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3593915498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3593915498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125567 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125567 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048051 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048051 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086139 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086139 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094555 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094555 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28410.661747 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28410.661747 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45663.186464 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45663.186464 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208007.813610 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208007.813610 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212295.504187 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212295.504187 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210527.531955 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210527.531955 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 426068 # number of writebacks +system.cpu0.dcache.writebacks::total 426068 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 384761 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 384761 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1282051 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1282051 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3514 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3514 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1666812 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1666812 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1666812 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1666812 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 682837 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 682837 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 214149 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 214149 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8688 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8688 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 769 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 769 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 896986 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 896986 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 896986 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 896986 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4777 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8020 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 12797 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25205904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25205904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10851652245 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10851652245 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107603000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107603000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4676000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4676000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36057556745 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 36057556745 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36057556745 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 36057556745 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1013290500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1013290500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1707574498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1707574498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2720864998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2720864998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111678 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111678 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051281 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051281 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005124 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005124 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.087168 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.087168 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6080.624187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6080.624187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 911417 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994958 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994958 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 615978 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.684225 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5692804 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 616490 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.234220 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28149663500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.684225 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993524 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993524 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9022750 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9022750 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7153262 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7153262 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7153262 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7153262 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7153262 # number of overall hits -system.cpu0.icache.overall_hits::total 7153262 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 957376 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 957376 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 957376 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 957376 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 957376 # number of overall misses -system.cpu0.icache.overall_misses::total 957376 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13452406105 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13452406105 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13452406105 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13452406105 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13452406105 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13452406105 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8110638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8110638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8110638 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8110638 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8110638 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8110638 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118040 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118040 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118040 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118040 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 6959538 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 6959538 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5692804 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5692804 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5692804 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5692804 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5692804 # number of overall hits +system.cpu0.icache.overall_hits::total 5692804 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 650065 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 650065 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 650065 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 650065 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 650065 # number of overall misses +system.cpu0.icache.overall_misses::total 650065 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9309214992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9309214992 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9309214992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9309214992 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9309214992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9309214992 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6342869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6342869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6342869 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6342869 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6342869 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6342869 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102488 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.102488 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102488 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.102488 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102488 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.102488 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14320.437175 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14320.437175 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3481 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 166 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.164103 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.969880 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33396 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 33396 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 33396 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 33396 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 33396 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 33396 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 616669 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 616669 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 616669 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 616669 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 616669 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 616669 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8251915495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8251915495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8251915495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8251915495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8251915495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8251915495 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097222 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.097222 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.097222 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3445639 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 836162 # Number of BTB hits +system.cpu1.branchPred.lookups 7710185 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6710334 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 163097 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4502045 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2070765 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 45.996097 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 394984 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 11166 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1858276 # DTB read hits -system.cpu1.dtb.read_misses 10905 # DTB read misses -system.cpu1.dtb.read_acv 64 # DTB read access violations -system.cpu1.dtb.read_accesses 300263 # DTB read accesses -system.cpu1.dtb.write_hits 1193771 # DTB write hits -system.cpu1.dtb.write_misses 2902 # DTB write misses -system.cpu1.dtb.write_acv 104 # DTB write access violations -system.cpu1.dtb.write_accesses 125157 # DTB write accesses -system.cpu1.dtb.data_hits 3052047 # DTB hits -system.cpu1.dtb.data_misses 13807 # DTB misses -system.cpu1.dtb.data_acv 168 # DTB access violations -system.cpu1.dtb.data_accesses 425420 # DTB accesses -system.cpu1.itb.fetch_hits 529068 # ITB hits -system.cpu1.itb.fetch_misses 7485 # ITB misses -system.cpu1.itb.fetch_acv 158 # ITB acv -system.cpu1.itb.fetch_accesses 536553 # ITB accesses +system.cpu1.dtb.read_hits 4026297 # DTB read hits +system.cpu1.dtb.read_misses 14233 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 293572 # DTB read accesses +system.cpu1.dtb.write_hits 2497972 # DTB write hits +system.cpu1.dtb.write_misses 2408 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 109195 # DTB write accesses +system.cpu1.dtb.data_hits 6524269 # DTB hits +system.cpu1.dtb.data_misses 16641 # DTB misses +system.cpu1.dtb.data_acv 43 # DTB access violations +system.cpu1.dtb.data_accesses 402767 # DTB accesses +system.cpu1.itb.fetch_hits 750930 # ITB hits +system.cpu1.itb.fetch_misses 5383 # ITB misses +system.cpu1.itb.fetch_acv 53 # ITB acv +system.cpu1.itb.fetch_accesses 756313 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -965,570 +972,564 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14296923 # number of cpu cycles simulated +system.cpu1.numCycles 34369930 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 13361598 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 30714280 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7710185 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2465749 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 18120966 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 547594 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 46 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 23797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 211021 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 198154 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 3304195 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 117193 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 32189433 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.954173 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.349586 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 26750456 83.10% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 307184 0.95% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 618506 1.92% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 382121 1.19% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 801179 2.49% 89.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 249293 0.77% 90.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 334783 1.04% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 403446 1.25% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 2342465 7.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1564088 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 32189433 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.224329 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.893638 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 11124412 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16339992 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3934359 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 534571 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 256098 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 250042 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 17822 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 25897409 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 55799 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 256098 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 11423416 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 4918911 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 9329125 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 4131002 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2130879 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 24789451 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 5724 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 540758 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 43054 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 820253 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 16289258 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 29487961 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 29391972 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 88964 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 13777657 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2511601 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 753305 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 82405 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4252225 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4127805 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2629581 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 507300 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 331297 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21789875 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 948507 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21283611 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28389 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3414486 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1484281 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 680406 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 32189433 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.661199 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.387208 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 23533399 73.11% 73.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 3630192 11.28% 84.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1573878 4.89% 89.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1186258 3.69% 92.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 1178148 3.66% 96.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 546160 1.70% 98.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 337865 1.05% 99.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 151957 0.47% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 51576 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 32189433 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 80499 16.46% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 246874 50.47% 66.92% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 161807 33.08% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 14071465 66.11% 66.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 30174 0.14% 66.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 13456 0.06% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4194422 19.71% 86.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 2532925 11.90% 97.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 435892 2.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued -system.cpu1.iq.rate 0.633233 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11259293 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 80938 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 21283611 # Type of FU issued +system.cpu1.iq.rate 0.619251 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 489180 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.022984 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 74907239 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 25989017 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20583813 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 366985 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 171482 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 168729 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 21571772 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 197501 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 207443 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 572592 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 7837 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 247159 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 7441 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 131088 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 256098 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4050515 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 319306 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 24169619 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 59065 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 4127805 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2629581 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 846465 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 33159 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 202940 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 7837 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 80858 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 187737 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 268595 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 21021510 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4051663 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 262101 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 503606 # number of nop insts executed -system.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1318456 # Number of branches executed -system.cpu1.iew.exec_stores 1202277 # Number of stores executed -system.cpu1.iew.exec_rate 0.624860 # Inst execution rate -system.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4148200 # num instructions producing a value -system.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value +system.cpu1.iew.exec_nop 1431237 # number of nop insts executed +system.cpu1.iew.exec_refs 6560061 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3322997 # Number of branches executed +system.cpu1.iew.exec_stores 2508398 # Number of stores executed +system.cpu1.iew.exec_rate 0.611625 # Inst execution rate +system.cpu1.iew.wb_sent 20805592 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20752542 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10210202 # num instructions producing a value +system.cpu1.iew.wb_consumers 14612629 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.603799 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.698725 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3582987 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 268101 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 243613 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31565232 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.650241 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.623237 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 24282945 76.93% 76.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2976975 9.43% 86.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1587723 5.03% 91.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 771361 2.44% 93.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 532421 1.69% 95.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 258990 0.82% 96.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 207817 0.66% 97.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 189047 0.60% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 757953 2.40% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8615735 # Number of instructions committed -system.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 31565232 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 20524993 # Number of instructions committed +system.cpu1.commit.committedOps 20524993 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2763276 # Number of memory references committed -system.cpu1.commit.loads 1626761 # Number of loads committed -system.cpu1.commit.membars 39485 # Number of memory barriers committed -system.cpu1.commit.branches 1225974 # Number of branches committed -system.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7995429 # Number of committed integer instructions. -system.cpu1.commit.function_calls 135018 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction +system.cpu1.commit.refs 5937635 # Number of memory references committed +system.cpu1.commit.loads 3555213 # Number of loads committed +system.cpu1.commit.membars 92415 # Number of memory barriers committed +system.cpu1.commit.branches 3082130 # Number of branches committed +system.cpu1.commit.fp_insts 166998 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 18893824 # Number of committed integer instructions. +system.cpu1.commit.function_calls 318960 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 1204616 5.87% 5.87% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12808497 62.40% 68.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 29745 0.14% 68.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13451 0.07% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3647628 17.77% 86.26% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 2383405 11.61% 97.88% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 435892 2.12% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction -system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 23176968 # The number of ROB reads -system.cpu1.rob.rob_writes 20704388 # The number of ROB writes -system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8207813 # Number of Instructions Simulated -system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11535994 # number of integer regfile reads -system.cpu1.int_regfile_writes 6250844 # number of integer regfile writes -system.cpu1.fp_regfile_reads 43175 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42684 # number of floating regfile writes -system.cpu1.misc_regfile_reads 891820 # number of misc regfile reads -system.cpu1.misc_regfile_writes 203240 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 102439 # number of replacements -system.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits -system.cpu1.dcache.overall_hits::total 2349874 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses -system.cpu1.dcache.overall_misses::total 425658 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 20524993 # Class of committed instruction +system.cpu1.commit.bw_lim_events 757953 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 54833276 # The number of ROB reads +system.cpu1.rob.rob_writes 48835744 # The number of ROB writes +system.cpu1.timesIdled 276866 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2180497 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3780899978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 19323895 # Number of Instructions Simulated +system.cpu1.committedOps 19323895 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.778623 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.778623 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.562233 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.562233 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 27142723 # number of integer regfile reads +system.cpu1.int_regfile_writes 14810250 # number of integer regfile writes +system.cpu1.fp_regfile_reads 88193 # number of floating regfile reads +system.cpu1.fp_regfile_writes 88824 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1272248 # number of misc regfile reads +system.cpu1.misc_regfile_writes 377130 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 561653 # number of replacements +system.cpu1.dcache.tags.tagsinuse 496.197725 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4717582 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 561970 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 8.394722 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 37149185000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.197725 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.969136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.969136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 317 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.619141 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24916279 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24916279 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2844065 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2844065 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1751257 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1751257 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 62172 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 62172 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69860 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 69860 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4595322 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4595322 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4595322 # number of overall hits +system.cpu1.dcache.overall_hits::total 4595322 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 792097 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 792097 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 552973 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 552973 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14160 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14160 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1345070 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1345070 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1345070 # number of overall misses +system.cpu1.dcache.overall_misses::total 1345070 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10154789500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 10154789500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16820667860 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 16820667860 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 217520000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 217520000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6395000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6395000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 26975457360 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 26975457360 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 26975457360 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 26975457360 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3636162 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3636162 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2304230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2304230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 76332 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 76332 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70646 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 70646 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5940392 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5940392 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 5940392 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 5940392 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.217839 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.217839 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.239982 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.239982 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.185505 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.185505 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.011126 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.011126 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.226428 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.226428 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.226428 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.226428 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8136.132316 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8136.132316 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 765854 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 810 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 36939 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.732938 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 45 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks -system.cpu1.dcache.writebacks::total 70134 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2893 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3051 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185632.911392 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185632.911392 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218110.266160 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 218110.266160 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 216428.384136 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 216428.384136 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 435263 # number of writebacks +system.cpu1.dcache.writebacks::total 435263 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332265 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 332265 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 455576 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 455576 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2707 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2707 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 787841 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 787841 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 787841 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 787841 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 459832 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 459832 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 97397 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 97397 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11453 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 557229 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 557229 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 557229 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 557229 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2425 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4340 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6765 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5761115500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5761115500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2818212839 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2818212839 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 135759000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 135759000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5609000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5609000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8579328339 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8579328339 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8579328339 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8579328339 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 499447000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 499447000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 957710500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 957710500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1457157500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1457157500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.126461 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.126461 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042269 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042269 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.150042 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.150042 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.011126 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.093803 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.093803 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7136.132316 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7136.132316 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 211356 # number of replacements -system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits -system.cpu1.icache.overall_hits::total 1331062 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses -system.cpu1.icache.overall_misses::total 219986 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 499853 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.618896 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 2783346 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 500364 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.562642 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 48744804500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.618896 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985584 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.985584 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 3804626 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 3804626 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 2783351 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2783351 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2783351 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2783351 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2783351 # number of overall hits +system.cpu1.icache.overall_hits::total 2783351 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 520843 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 520843 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 520843 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 520843 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 520843 # number of overall misses +system.cpu1.icache.overall_misses::total 520843 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7005360499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7005360499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7005360499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7005360499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7005360499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7005360499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 3304194 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 3304194 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 3304194 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 3304194 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 3304194 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 3304194 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.157631 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.157631 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.157631 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.157631 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.157631 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.157631 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13450.042525 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13450.042525 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 65 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.461538 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 20411 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 20411 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 20411 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 20411 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 20411 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 20411 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500432 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 500432 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 500432 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 500432 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 500432 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 500432 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6297993499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6297993499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6297993499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6297993499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6297993499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6297993499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.151454 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.151454 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1542,54 +1543,53 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7375 # Transaction distribution -system.iobus.trans_dist::ReadResp 7375 # Transaction distribution -system.iobus.trans_dist::WriteReq 54477 # Transaction distribution -system.iobus.trans_dist::WriteResp 12925 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 53912 # Transaction distribution +system.iobus.trans_dist::WriteResp 53912 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122578 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68315 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2729939 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 9868000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1601,285 +1601,291 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216085248 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26764000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use +system.iocache.tags.replacements 41701 # number of replacements +system.iocache.tags.tagsinuse 0.804902 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711319254000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.804902 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.050306 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.050306 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses -system.iocache.demand_misses::total 178 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 178 # number of overall misses -system.iocache.overall_misses::total 178 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 25392883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 25392883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907312365 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907312365 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 25392883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 25392883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 25392883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 25392883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145102.188571 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145102.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145102.188571 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 41526 # number of writebacks +system.iocache.writebacks::total 41526 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 16642883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16642883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829712365 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2829712365 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 16642883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16642883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 16642883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16642883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # 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average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 346915 # number of replacements -system.l2c.tags.tagsinuse 65246.496404 # Cycle average of tags in use -system.l2c.tags.total_refs 2614060 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 412065 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.343805 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7589002750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53536.501359 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5301.488199 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6124.882413 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 215.988746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 67.635688 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080894 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003296 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995583 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2446 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7744 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49345 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27379617 # Number of tag accesses -system.l2c.tags.data_accesses 27379617 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 898215 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 742471 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 210198 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 63927 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1914811 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822887 # number of Writeback hits -system.l2c.Writeback_hits::total 822887 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 246 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 422 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 53 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 152332 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25116 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 177448 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 898215 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 894803 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 210198 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 89043 # number of demand (read+write) hits -system.l2c.demand_hits::total 2092259 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 898215 # number of overall hits -system.l2c.overall_hits::cpu0.data 894803 # number of overall hits -system.l2c.overall_hits::cpu1.inst 210198 # number of overall hits -system.l2c.overall_hits::cpu1.data 89043 # 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number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948238 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870550 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.933872 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.644860 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735294 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.695473 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.478216 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.182684 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.388754 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013719 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.402714 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.004884 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244531 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.161474 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.161474 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20852.301587 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20599.442379 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20808.713553 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.362319 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20680 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20718.934911 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78361.429330 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93376.543916 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80497.372617 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73434.281799 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62941.831619 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90528.925620 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63160.898146 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 199618.589073 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193457.525773 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197544.084976 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 201393.453865 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208745.391705 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296650 # Transaction distribution -system.membus.trans_dist::ReadResp 296572 # Transaction distribution -system.membus.trans_dist::WriteReq 12925 # Transaction distribution -system.membus.trans_dist::WriteResp 12925 # Transaction distribution -system.membus.trans_dist::Writeback 124744 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9402 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4742 # Transaction distribution -system.membus.trans_dist::ReadExReq 123808 # Transaction distribution -system.membus.trans_dist::ReadExResp 123481 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10437 # Total snoops (count) -system.membus.snoop_fanout::samples 614132 # Request fanout histogram +system.membus.trans_dist::ReadReq 7202 # Transaction distribution +system.membus.trans_dist::ReadResp 296546 # Transaction distribution +system.membus.trans_dist::WriteReq 12360 # Transaction distribution +system.membus.trans_dist::WriteResp 12360 # Transaction distribution +system.membus.trans_dist::Writeback 124264 # Transaction distribution +system.membus.trans_dist::CleanEvict 262871 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5279 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1481 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3452 # Transaction distribution +system.membus.trans_dist::ReadExReq 122900 # Transaction distribution +system.membus.trans_dist::ReadExResp 122774 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289774 # Transaction distribution +system.membus.trans_dist::BadAddressError 430 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1219526 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1344359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68315 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31641920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31710235 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34368859 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3872 # Total snoops (count) +system.membus.snoop_fanout::samples 867863 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 614132 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 867863 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 614132 # Request fanout histogram -system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 867863 # Request fanout histogram +system.membus.reqLayer0.occupancy 35224999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1361324691 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 531000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2190703579 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72073655 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 72565 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3425693 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012192 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109741 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7202 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2275897 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12360 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12360 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 985613 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1602095 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5338 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1555 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6893 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 317171 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 317171 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1117101 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1152039 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 430 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1728214 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2704934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1334787 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1622621 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7390556 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39458944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84672718 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32025024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 62527373 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 218684059 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 464381 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5618153 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.076464 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.265739 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3383928 98.78% 98.78% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41765 1.22% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 5188566 92.35% 92.35% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 429587 7.65% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3425693 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5618153 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3461836914 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 240000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 925515973 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1363977262 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 751744303 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 856189885 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2154,171 +2174,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4815 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 139340 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 45519 38.89% 38.89% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.11% 39.01% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.65% 40.65% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 40.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 69446 59.33% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 117041 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 44932 48.88% 48.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.14% 49.02% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 2.10% 51.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 44917 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 91925 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1870471244000 98.03% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61392000 0.00% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 548913500 0.03% 98.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8511500 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36889187000 1.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907979248000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.987104 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed -system.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed -system.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed -system.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 215 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.646790 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.785409 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed +system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed -system.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed -system.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170714 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1181 # number of protection mode switches +system.cpu0.kern.callpal::wripir 104 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2293 1.85% 1.93% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.04% 1.97% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed +system.cpu0.kern.callpal::swpipl 110963 89.30% 91.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6296 5.07% 96.35% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.35% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.35% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.36% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.36% # number of callpals executed +system.cpu0.kern.callpal::rti 4002 3.22% 99.58% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.31% 99.89% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.11% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 124254 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5723 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1181 -system.cpu0.kern.mode_good::user 1181 +system.cpu0.kern.mode_good::kernel 1341 +system.cpu0.kern.mode_good::user 1342 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.234318 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.379759 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1905987592000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1991648000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3503 # number of times the context was actually changed +system.cpu0.kern.swap_context 2294 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3855 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 98215 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 36112 40.36% 40.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 2.15% 42.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.12% 42.63% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 51325 57.37% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 89466 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 35322 48.67% 48.67% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 2.65% 51.33% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.14% 51.47% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 35218 48.53% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 72569 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870768654000 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 540231000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 48911000 0.00% 98.10% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36277143500 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907634939500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978124 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed -system.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed -system.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed -system.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed -system.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 111 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.686176 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.811135 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed +system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed +system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed -system.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed -system.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed -system.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1949 2.12% 2.14% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.14% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.15% # number of callpals executed +system.cpu1.kern.callpal::swpipl 84230 91.49% 93.64% # number of callpals executed +system.cpu1.kern.callpal::rdps 2466 2.68% 96.32% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.32% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 96.32% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.33% # number of callpals executed +system.cpu1.kern.callpal::rti 3206 3.48% 99.81% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.14% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 46904 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches -system.cpu1.kern.mode_switch::user 554 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 733 -system.cpu1.kern.mode_good::user 554 -system.cpu1.kern.mode_good::idle 179 -system.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 92064 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2331 # number of protection mode switches +system.cpu1.kern.mode_switch::user 395 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 461 +system.cpu1.kern.mode_good::user 395 +system.cpu1.kern.mode_good::idle 66 +system.cpu1.kern.mode_switch_good::kernel 0.197769 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1024 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.192887 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 42837305000 2.25% 2.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 697376000 0.04% 2.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1863790118000 97.72% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1950 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |