diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3952 |
1 files changed, 1986 insertions, 1966 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 4b8dc4618..7d7e06664 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.929078 # Number of seconds simulated -sim_ticks 1929077876500 # Number of ticks simulated -final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.908652 # Number of seconds simulated +sim_ticks 1908652088000 # Number of ticks simulated +final_tick 1908652088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169237 # Simulator instruction rate (inst/s) -host_op_rate 169237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5749129790 # Simulator tick rate (ticks/s) -host_mem_usage 339544 # Number of bytes of host memory used -host_seconds 335.54 # Real time elapsed on the host -sim_insts 56786201 # Number of instructions simulated -sim_ops 56786201 # Number of ops (including micro ops) simulated +host_inst_rate 169428 # Simulator instruction rate (inst/s) +host_op_rate 169428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5757307258 # Simulator tick rate (ticks/s) +host_mem_usage 336708 # Number of bytes of host memory used +host_seconds 331.52 # Real time elapsed on the host +sim_insts 56168509 # Number of instructions simulated +sim_ops 56168509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 856320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24603328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 123072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 684608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 873216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24648192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 103232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 582976 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26268288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 856320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 123072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 979392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7871488 # Number of bytes written to this memory -system.physmem.bytes_written::total 7871488 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13380 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384427 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10697 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26208576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 873216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 103232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7849920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7849920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13644 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385128 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9109 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122992 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122992 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 443901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12753932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 354889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13617018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 443901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 507700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4080441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4080441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4080441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 443901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12753932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 354889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17697459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410442 # Number of read requests accepted -system.physmem.writeReqs 122992 # Number of write requests accepted -system.physmem.readBursts 410442 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122992 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7869440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26268288 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7871488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 409509 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122655 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122655 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 457504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12913926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 305439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13731458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 511590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4112808 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4112808 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4112808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12913926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 305439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17844266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 409509 # Number of read requests accepted +system.physmem.writeReqs 122655 # Number of write requests accepted +system.physmem.readBursts 409509 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122655 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26200320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue +system.physmem.bytesWritten 7848512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26208576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7849920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26358 # Per bank write bursts -system.physmem.perBankRdBursts::1 25853 # Per bank write bursts -system.physmem.perBankRdBursts::2 25982 # Per bank write bursts -system.physmem.perBankRdBursts::3 25455 # Per bank write bursts -system.physmem.perBankRdBursts::4 25391 # Per bank write bursts -system.physmem.perBankRdBursts::5 25779 # Per bank write bursts -system.physmem.perBankRdBursts::6 25718 # Per bank write bursts -system.physmem.perBankRdBursts::7 25362 # Per bank write bursts -system.physmem.perBankRdBursts::8 25502 # Per bank write bursts -system.physmem.perBankRdBursts::9 25880 # Per bank write bursts -system.physmem.perBankRdBursts::10 25847 # Per bank write bursts -system.physmem.perBankRdBursts::11 25125 # Per bank write bursts -system.physmem.perBankRdBursts::12 25573 # Per bank write bursts -system.physmem.perBankRdBursts::13 25368 # Per bank write bursts -system.physmem.perBankRdBursts::14 25415 # Per bank write bursts -system.physmem.perBankRdBursts::15 25720 # Per bank write bursts -system.physmem.perBankWrBursts::0 8608 # Per bank write bursts -system.physmem.perBankWrBursts::1 7821 # Per bank write bursts -system.physmem.perBankWrBursts::2 8027 # Per bank write bursts -system.physmem.perBankWrBursts::3 7496 # Per bank write bursts -system.physmem.perBankWrBursts::4 7316 # Per bank write bursts -system.physmem.perBankWrBursts::5 7320 # Per bank write bursts -system.physmem.perBankWrBursts::6 7241 # Per bank write bursts -system.physmem.perBankWrBursts::7 6937 # Per bank write bursts -system.physmem.perBankWrBursts::8 7156 # Per bank write bursts -system.physmem.perBankWrBursts::9 7588 # Per bank write bursts -system.physmem.perBankWrBursts::10 7741 # Per bank write bursts -system.physmem.perBankWrBursts::11 7304 # Per bank write bursts -system.physmem.perBankWrBursts::12 7945 # Per bank write bursts -system.physmem.perBankWrBursts::13 8097 # Per bank write bursts -system.physmem.perBankWrBursts::14 8174 # Per bank write bursts -system.physmem.perBankWrBursts::15 8189 # Per bank write bursts +system.physmem.perBankRdBursts::0 25687 # Per bank write bursts +system.physmem.perBankRdBursts::1 26129 # Per bank write bursts +system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::3 25363 # Per bank write bursts +system.physmem.perBankRdBursts::4 24824 # Per bank write bursts +system.physmem.perBankRdBursts::5 25086 # Per bank write bursts +system.physmem.perBankRdBursts::6 25117 # Per bank write bursts +system.physmem.perBankRdBursts::7 24738 # Per bank write bursts +system.physmem.perBankRdBursts::8 25651 # Per bank write bursts +system.physmem.perBankRdBursts::9 26257 # Per bank write bursts +system.physmem.perBankRdBursts::10 25842 # Per bank write bursts +system.physmem.perBankRdBursts::11 26258 # Per bank write bursts +system.physmem.perBankRdBursts::12 25994 # Per bank write bursts +system.physmem.perBankRdBursts::13 25940 # Per bank write bursts +system.physmem.perBankRdBursts::14 25679 # Per bank write bursts +system.physmem.perBankRdBursts::15 25213 # Per bank write bursts +system.physmem.perBankWrBursts::0 7897 # Per bank write bursts +system.physmem.perBankWrBursts::1 8119 # Per bank write bursts +system.physmem.perBankWrBursts::2 8345 # Per bank write bursts +system.physmem.perBankWrBursts::3 7678 # Per bank write bursts +system.physmem.perBankWrBursts::4 7188 # Per bank write bursts +system.physmem.perBankWrBursts::5 7302 # Per bank write bursts +system.physmem.perBankWrBursts::6 7389 # Per bank write bursts +system.physmem.perBankWrBursts::7 6798 # Per bank write bursts +system.physmem.perBankWrBursts::8 7376 # Per bank write bursts +system.physmem.perBankWrBursts::9 7907 # Per bank write bursts +system.physmem.perBankWrBursts::10 7738 # Per bank write bursts +system.physmem.perBankWrBursts::11 7709 # Per bank write bursts +system.physmem.perBankWrBursts::12 7797 # Per bank write bursts +system.physmem.perBankWrBursts::13 7971 # Per bank write bursts +system.physmem.perBankWrBursts::14 7878 # Per bank write bursts +system.physmem.perBankWrBursts::15 7541 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1929076824500 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times write queue was full causing retry +system.physmem.totGap 1908647739500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410442 # Read request sizes (log2) +system.physmem.readPktSize::6 409509 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122992 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122655 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -158,194 +158,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 522.399241 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.882184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 410.899985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14976 22.92% 22.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11360 17.39% 40.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5432 8.31% 48.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2850 4.36% 52.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2530 3.87% 56.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1671 2.56% 59.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3857 5.90% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1188 1.82% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21470 32.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65334 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5522 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.304962 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2840.771031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5519 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64693 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.314006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.672506 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.720496 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14759 22.81% 22.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11414 17.64% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5700 8.81% 49.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2716 4.20% 53.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2485 3.84% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1481 2.29% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1583 2.45% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1463 2.26% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23092 35.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64693 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5538 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.921271 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2818.439252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5535 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5522 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.267294 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.111227 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.252131 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4917 89.04% 89.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 44 0.80% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 22 0.40% 90.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 38 0.69% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 207 3.75% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.11% 94.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 12 0.22% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 27 0.49% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 186 3.37% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 8 0.14% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 8 0.14% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.11% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.07% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.09% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5522 # Writes before turning the bus around for reads -system.physmem.totQLat 4416821750 # Total ticks spent queuing -system.physmem.totMemAccLat 12110471750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10764.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5538 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5538 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.143915 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.892939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.348287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4779 86.29% 86.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 158 2.85% 89.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 16 0.29% 89.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 27 0.49% 89.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 200 3.61% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 23 0.42% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.27% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.13% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 3 0.05% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.11% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 11 0.20% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.13% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 10 0.18% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 30 0.54% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.04% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 13 0.23% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 169 3.05% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.05% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 7 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.04% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 12 0.22% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 9 0.16% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5538 # Writes before turning the bus around for reads +system.physmem.totQLat 3969590750 # Total ticks spent queuing +system.physmem.totMemAccLat 11645465750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2046900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9696.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29514.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.08 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28446.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.77 # Average write queue length when enqueuing -system.physmem.readRowHits 369361 # Number of row buffer hits during reads -system.physmem.writeRowHits 98593 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.16 # Row buffer hit rate for writes -system.physmem.avgGap 3616336.46 # Average gap between requests -system.physmem.pageHitRate 87.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 246047760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134252250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1606004400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 393763680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63271865610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1101943260750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1293592968690 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.576874 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1832974418500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64416040000 # Time in different power states +system.physmem.avgRdQLen 2.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing +system.physmem.readRowHits 368832 # Number of row buffer hits during reads +system.physmem.writeRowHits 98488 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.30 # Row buffer hit rate for writes +system.physmem.avgGap 3586578.08 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 244233360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133262250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 393439680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57966073335 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1094343472500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1279324161285 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.276452 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1820370973000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63734060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31684384000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24546489500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247877280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135250500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1594554000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 403017120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 63221156415 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1101987750750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1293587380305 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.573972 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1833051648500 # Time in different power states -system.physmem_1.memoryStateTime::REF 64416040000 # Time in different power states +system.physmem_1.actEnergy 244845720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133596375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1613305200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 401222160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57268583145 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1094955297750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1279280671710 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.253671 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1821389841500 # Time in different power states +system.physmem_1.memoryStateTime::REF 63734060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31607167750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23527607250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 17100345 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14625316 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 474432 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10759421 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4832502 # Number of BTB hits +system.cpu0.branchPred.lookups 18555851 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15805635 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 543843 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 11677993 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5178603 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.914145 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 945329 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34555 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5020643 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 507910 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4512733 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 209375 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.344974 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 1050126 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 41449 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5562960 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 527221 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 5035739 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 249629 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9634816 # DTB read hits -system.cpu0.dtb.read_misses 36704 # DTB read misses -system.cpu0.dtb.read_acv 586 # DTB read access violations -system.cpu0.dtb.read_accesses 618265 # DTB read accesses -system.cpu0.dtb.write_hits 5807101 # DTB write hits -system.cpu0.dtb.write_misses 8981 # DTB write misses +system.cpu0.dtb.read_hits 10426157 # DTB read hits +system.cpu0.dtb.read_misses 39598 # DTB read misses +system.cpu0.dtb.read_acv 591 # DTB read access violations +system.cpu0.dtb.read_accesses 665311 # DTB read accesses +system.cpu0.dtb.write_hits 6323119 # DTB write hits +system.cpu0.dtb.write_misses 9829 # DTB write misses system.cpu0.dtb.write_acv 421 # DTB write access violations -system.cpu0.dtb.write_accesses 195454 # DTB write accesses -system.cpu0.dtb.data_hits 15441917 # DTB hits -system.cpu0.dtb.data_misses 45685 # DTB misses -system.cpu0.dtb.data_acv 1007 # DTB access violations -system.cpu0.dtb.data_accesses 813719 # DTB accesses -system.cpu0.itb.fetch_hits 1375653 # ITB hits -system.cpu0.itb.fetch_misses 7396 # ITB misses -system.cpu0.itb.fetch_acv 601 # ITB acv -system.cpu0.itb.fetch_accesses 1383049 # ITB accesses +system.cpu0.dtb.write_accesses 221072 # DTB write accesses +system.cpu0.dtb.data_hits 16749276 # DTB hits +system.cpu0.dtb.data_misses 49427 # DTB misses +system.cpu0.dtb.data_acv 1012 # DTB access violations +system.cpu0.dtb.data_accesses 886383 # DTB accesses +system.cpu0.itb.fetch_hits 1503637 # ITB hits +system.cpu0.itb.fetch_misses 7915 # ITB misses +system.cpu0.itb.fetch_acv 722 # ITB acv +system.cpu0.itb.fetch_accesses 1511552 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -358,590 +370,590 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 146500468 # number of cpu cycles simulated +system.cpu0.numCycles 120614537 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26225748 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 74880065 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 17100345 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6285741 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 112740313 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1369370 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 398 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 30412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 147220 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 425638 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 504 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8642043 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 322305 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 140254918 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.533885 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.795707 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 28910287 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 80847463 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 18555851 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6755950 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 84571652 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1544806 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 27521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 158722 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 425179 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 9281945 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 366954 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 114866072 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.703841 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.035887 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 126345960 90.08% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 903115 0.64% 90.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1906918 1.36% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 803345 0.57% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2649453 1.89% 94.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 589849 0.42% 94.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 700559 0.50% 95.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 843084 0.60% 96.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5512635 3.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 99921621 86.99% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 978753 0.85% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2003703 1.74% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 871619 0.76% 90.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2763119 2.41% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 643273 0.56% 93.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 756873 0.66% 93.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 980520 0.85% 94.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5946591 5.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 140254918 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.116726 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.511125 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20974212 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 107876486 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8907132 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1841497 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 655590 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 626155 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 29675 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 64967024 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 87739 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 655590 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21855511 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 78567360 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18275925 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9798485 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11102045 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62456562 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 201631 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2042440 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 306402 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7083961 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 42144620 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 75447660 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 75312247 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 126226 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34366321 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7778299 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1457881 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 236313 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12541674 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10026235 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6171298 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1512964 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 977849 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55240015 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1897630 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 53565100 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 74212 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9657224 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4199823 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1322202 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 140254918 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.381912 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.107336 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 114866072 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.153844 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.670296 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23249023 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 79273649 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9681952 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1921768 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 739679 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 692177 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33362 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 69931495 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 102843 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 739679 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24188488 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 52133494 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18507080 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10598824 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8698505 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 67143844 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 198929 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2037542 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 235156 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4634826 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 45210033 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 80787031 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 80633489 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 143553 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36399823 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8810210 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1599007 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 262557 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 13124305 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10911287 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6742479 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1608349 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1040811 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 59252141 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2087306 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 57311786 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 84500 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10900957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4754694 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1456877 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 114866072 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.498944 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.243932 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 118450817 84.45% 84.45% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9324559 6.65% 91.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3896910 2.78% 93.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2805800 2.00% 95.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2901850 2.07% 97.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1433856 1.02% 98.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 954902 0.68% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 366563 0.26% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 119661 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 91593251 79.74% 79.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9917884 8.63% 88.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4171968 3.63% 92.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2987675 2.60% 94.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 3091850 2.69% 97.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1551239 1.35% 98.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1031605 0.90% 99.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 391084 0.34% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 129516 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 140254918 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 114866072 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 172960 16.73% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 530801 51.33% 68.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 330287 31.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 177618 15.88% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 580154 51.88% 67.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 360585 32.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3306 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36704403 68.52% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56318 0.11% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 27375 0.05% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 10076531 18.81% 87.50% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5896825 11.01% 98.51% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 798690 1.49% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 38999657 68.05% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 59968 0.10% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28473 0.05% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 10921462 19.06% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6423481 11.21% 98.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 873773 1.52% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 53565100 # Type of FU issued -system.cpu0.iq.rate 0.365631 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1034048 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019305 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 247915569 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 66533789 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51792941 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 577809 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 279350 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 262536 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 54284218 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 311624 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 608466 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 57311786 # Type of FU issued +system.cpu0.iq.rate 0.475165 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1118357 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019514 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 230030260 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 71938879 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 55311420 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 662241 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 320414 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 300136 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 58069335 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 357492 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 651404 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2001818 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4069 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18629 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 679305 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2319887 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3968 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19302 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 772094 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18387 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 376944 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18487 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 403076 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 655590 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 75078561 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 955285 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 60714699 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 160012 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10026235 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6171298 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1682472 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42874 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 711273 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18629 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 185912 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 515422 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 701334 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52870028 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9698038 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 695072 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 739679 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 48919856 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 836899 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 65195890 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 175652 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10911287 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6742479 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1850250 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 42611 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 592619 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19302 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 209624 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 584555 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 794179 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 56526207 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 10495265 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 785579 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3577054 # number of nop insts executed -system.cpu0.iew.exec_refs 15531241 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8401878 # Number of branches executed -system.cpu0.iew.exec_stores 5833203 # Number of stores executed -system.cpu0.iew.exec_rate 0.360886 # Inst execution rate -system.cpu0.iew.wb_sent 52244753 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 52055477 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26703720 # num instructions producing a value -system.cpu0.iew.wb_consumers 36905470 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.355326 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723571 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10154720 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 575428 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 626255 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 138489248 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.363854 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.249176 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3856443 # number of nop insts executed +system.cpu0.iew.exec_refs 16847340 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8962761 # Number of branches executed +system.cpu0.iew.exec_stores 6352075 # Number of stores executed +system.cpu0.iew.exec_rate 0.468652 # Inst execution rate +system.cpu0.iew.wb_sent 55828896 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 55611556 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 28259375 # num instructions producing a value +system.cpu0.iew.wb_consumers 39130384 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.461068 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.722185 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 11491140 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 630429 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 709660 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112872616 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.474349 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.409733 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 120648787 87.12% 87.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7115506 5.14% 92.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3823437 2.76% 95.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2034446 1.47% 96.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1589267 1.15% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 580000 0.42% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 430694 0.31% 98.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 453916 0.33% 98.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1813195 1.31% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 93942624 83.23% 83.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7580066 6.72% 89.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4021065 3.56% 93.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2150933 1.91% 95.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1669707 1.48% 96.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 619428 0.55% 97.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 456360 0.40% 97.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 507616 0.45% 98.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1924817 1.71% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 138489248 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50389922 # Number of instructions committed -system.cpu0.commit.committedOps 50389922 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112872616 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 53540971 # Number of instructions committed +system.cpu0.commit.committedOps 53540971 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13516410 # Number of memory references committed -system.cpu0.commit.loads 8024417 # Number of loads committed -system.cpu0.commit.membars 195679 # Number of memory barriers committed -system.cpu0.commit.branches 7630866 # Number of branches committed -system.cpu0.commit.fp_insts 253714 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46654336 # Number of committed integer instructions. -system.cpu0.commit.function_calls 644656 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2912807 5.78% 5.78% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32876835 65.24% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54961 0.11% 71.13% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.13% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 26901 0.05% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1652 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8220096 16.31% 87.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5497981 10.91% 98.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 798689 1.59% 100.00% # Class of committed instruction +system.cpu0.commit.refs 14561785 # Number of memory references committed +system.cpu0.commit.loads 8591400 # Number of loads committed +system.cpu0.commit.membars 215482 # Number of memory barriers committed +system.cpu0.commit.branches 8090306 # Number of branches committed +system.cpu0.commit.fp_insts 289534 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49542263 # Number of committed integer instructions. +system.cpu0.commit.function_calls 699437 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 3105795 5.80% 5.80% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 34689949 64.79% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 58544 0.11% 70.70% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28001 0.05% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8806882 16.45% 87.21% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5976371 11.16% 98.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 873773 1.63% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 50389922 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1813195 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 197034230 # The number of ROB reads -system.cpu0.rob.rob_writes 122856265 # The number of ROB writes -system.cpu0.timesIdled 490676 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6245550 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3710936476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47480420 # Number of Instructions Simulated -system.cpu0.committedOps 47480420 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 3.085492 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.085492 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.324097 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.324097 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 69229174 # number of integer regfile reads -system.cpu0.int_regfile_writes 37925510 # number of integer regfile writes -system.cpu0.fp_regfile_reads 125098 # number of floating regfile reads -system.cpu0.fp_regfile_writes 133204 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1692059 # number of misc regfile reads -system.cpu0.misc_regfile_writes 801866 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1263704 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.064166 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10905904 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1264137 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.627154 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.064166 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988407 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988407 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 433 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.845703 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 58069444 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 58069444 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6953524 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6953524 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3586613 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3586613 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 178977 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 178977 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184325 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 184325 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10540137 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10540137 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10540137 # number of overall hits -system.cpu0.dcache.overall_hits::total 10540137 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1569058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1569058 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1703592 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1703592 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20226 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20226 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2959 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2959 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3272650 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3272650 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3272650 # number of overall misses -system.cpu0.dcache.overall_misses::total 3272650 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54620758000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54620758000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110116261626 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 110116261626 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 348212000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 348212000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46063500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46063500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 164737019626 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 164737019626 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 164737019626 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 164737019626 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8522582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8522582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5290205 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5290205 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 199203 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 199203 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187284 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187284 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13812787 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13812787 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13812787 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13812787 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184106 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.184106 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322028 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322028 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101535 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101535 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015800 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015800 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236929 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.236929 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236929 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.236929 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34811.178427 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34811.178427 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64637.695895 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64637.695895 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17216.058539 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17216.058539 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15567.252450 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15567.252450 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50337.500077 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6721817 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 17671 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 111036 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks -system.cpu0.dcache.writebacks::total 741086 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 559859 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449235 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449235 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5567 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5567 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2009094 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2009094 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2009094 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2009094 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1009199 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1009199 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254357 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 254357 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14659 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14659 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2959 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2959 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263556 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1263556 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263556 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1263556 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10105 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10105 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17136 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17136 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43480023500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43480023500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17474692057 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17474692057 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 173733500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 173733500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 43104500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 43104500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60954715557 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 60954715557 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048081 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.073588 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.073588 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015800 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015800 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.091477 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.091477 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43083.696575 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43083.696575 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68701.439540 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68701.439540 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11851.661096 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11851.661096 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 911237 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 911749 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.418764 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42368821500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.249711 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992675 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992675 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 53540971 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1924817 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 175788251 # The number of ROB reads +system.cpu0.rob.rob_writes 132059822 # The number of ROB writes +system.cpu0.timesIdled 545123 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5748465 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3696064399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 50438489 # Number of Instructions Simulated +system.cpu0.committedOps 50438489 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.391319 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.391319 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.418179 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.418179 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 73773620 # number of integer regfile reads +system.cpu0.int_regfile_writes 40428970 # number of integer regfile writes +system.cpu0.fp_regfile_reads 142673 # number of floating regfile reads +system.cpu0.fp_regfile_writes 153221 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1866400 # number of misc regfile reads +system.cpu0.misc_regfile_writes 877434 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1337856 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.906059 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11855471 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1338256 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.858896 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.906059 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988098 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988098 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 62973100 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 62973100 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7528886 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7528886 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3919891 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3919891 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 201495 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 201495 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 204000 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 204000 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11448777 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11448777 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11448777 # number of overall hits +system.cpu0.dcache.overall_hits::total 11448777 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1699683 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1699683 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1831149 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1831149 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21973 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21973 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 873 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 873 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3530832 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3530832 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3530832 # number of overall misses +system.cpu0.dcache.overall_misses::total 3530832 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40671315500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40671315500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77312811875 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77312811875 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331728000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 331728000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6457500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 6457500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117984127375 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117984127375 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117984127375 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117984127375 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9228569 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9228569 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5751040 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5751040 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223468 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 223468 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 204873 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 204873 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14979609 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14979609 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14979609 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14979609 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184176 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.184176 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318403 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.318403 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098327 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098327 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004261 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004261 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.235709 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.235709 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.235709 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.235709 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23928.765246 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23928.765246 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.928977 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42220.928977 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15097.073681 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15097.073681 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7396.907216 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7396.907216 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33415.389737 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33415.389737 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4312836 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 8080 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119422 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 127 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.114250 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 63.622047 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 792748 # number of writebacks +system.cpu0.dcache.writebacks::total 792748 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 643460 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 643460 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1557660 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1557660 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6525 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6525 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2201120 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2201120 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2201120 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2201120 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1056223 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1056223 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273489 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 273489 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15448 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15448 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 873 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 873 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1329712 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1329712 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1329712 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1329712 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7053 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7053 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9807 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9807 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16860 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16860 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30297527500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30297527500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12178891856 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12178891856 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 190480500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 190480500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5584500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5584500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42476419356 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 42476419356 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42476419356 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 42476419356 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1570178500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1570178500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1570178500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1570178500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047555 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047555 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069128 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.069128 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004261 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004261 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.088768 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.088768 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28684.782948 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28684.782948 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44531.560158 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44531.560158 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12330.431124 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.431124 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6396.907216 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6396.907216 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222625.620303 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222625.620303 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93130.397390 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93130.397390 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1021310 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.519684 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 8197716 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1021822 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.022646 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28452447500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.519684 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995156 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995156 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 196 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9554008 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9554008 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7675800 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7675800 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7675800 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7675800 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7675800 # number of overall hits -system.cpu0.icache.overall_hits::total 7675800 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 966240 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 966240 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 966240 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 966240 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 966240 # number of overall misses -system.cpu0.icache.overall_misses::total 966240 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14731064486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14731064486 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14731064486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14731064486 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14731064486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14731064486 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8642040 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8642040 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8642040 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8642040 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8642040 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8642040 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111807 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111807 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111807 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111807 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111807 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111807 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15245.761391 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15245.761391 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15245.761391 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15245.761391 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11439 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 10303980 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 10303980 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 8197716 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 8197716 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 8197716 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 8197716 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 8197716 # number of overall hits +system.cpu0.icache.overall_hits::total 8197716 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1084226 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1084226 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1084226 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1084226 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1084226 # number of overall misses +system.cpu0.icache.overall_misses::total 1084226 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15369093993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 15369093993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 15369093993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 15369093993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 15369093993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 15369093993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 9281942 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 9281942 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 9281942 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 9281942 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 9281942 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 9281942 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116810 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116810 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116810 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116810 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116810 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116810 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.175649 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.175649 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14175.175649 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14175.175649 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5565 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 223 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.955157 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks -system.cpu0.icache.writebacks::total 911237 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54272 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54272 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54272 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54272 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54272 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 911968 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 911968 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 911968 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 911968 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 911968 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 911968 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12931897989 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12931897989 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12931897989 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12931897989 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12931897989 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12931897989 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105527 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105527 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105527 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4129053 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2303722 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 822541 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 1021310 # number of writebacks +system.cpu0.icache.writebacks::total 1021310 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 62188 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 62188 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 62188 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 62188 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 62188 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 62188 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1022038 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1022038 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1022038 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1022038 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1022038 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1022038 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13659780995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13659780995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13659780995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13659780995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13659780995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13659780995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110110 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.110110 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.110110 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13365.237883 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency +system.cpu1.branchPred.lookups 2642221 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2286827 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 62241 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1292185 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 477042 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 35.704872 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 211273 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8217 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1287279 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 153619 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1133660 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 37557 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 36.917469 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 126491 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4205 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 709163 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 105030 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 604133 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 17634 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2247369 # DTB read hits -system.cpu1.dtb.read_misses 13283 # DTB read misses -system.cpu1.dtb.read_acv 72 # DTB read access violations -system.cpu1.dtb.read_accesses 382556 # DTB read accesses -system.cpu1.dtb.write_hits 1356336 # DTB write hits -system.cpu1.dtb.write_misses 3091 # DTB write misses -system.cpu1.dtb.write_acv 71 # DTB write access violations -system.cpu1.dtb.write_accesses 152961 # DTB write accesses -system.cpu1.dtb.data_hits 3603705 # DTB hits -system.cpu1.dtb.data_misses 16374 # DTB misses -system.cpu1.dtb.data_acv 143 # DTB access violations -system.cpu1.dtb.data_accesses 535517 # DTB accesses -system.cpu1.itb.fetch_hits 615373 # ITB hits -system.cpu1.itb.fetch_misses 3011 # ITB misses -system.cpu1.itb.fetch_acv 117 # ITB acv -system.cpu1.itb.fetch_accesses 618384 # ITB accesses +system.cpu1.dtb.read_hits 1454361 # DTB read hits +system.cpu1.dtb.read_misses 11674 # DTB read misses +system.cpu1.dtb.read_acv 55 # DTB read access violations +system.cpu1.dtb.read_accesses 336696 # DTB read accesses +system.cpu1.dtb.write_hits 804644 # DTB write hits +system.cpu1.dtb.write_misses 2787 # DTB write misses +system.cpu1.dtb.write_acv 46 # DTB write access violations +system.cpu1.dtb.write_accesses 125975 # DTB write accesses +system.cpu1.dtb.data_hits 2259005 # DTB hits +system.cpu1.dtb.data_misses 14461 # DTB misses +system.cpu1.dtb.data_acv 101 # DTB access violations +system.cpu1.dtb.data_accesses 462671 # DTB accesses +system.cpu1.itb.fetch_hits 472443 # ITB hits +system.cpu1.itb.fetch_misses 2661 # ITB misses +system.cpu1.itb.fetch_acv 95 # ITB acv +system.cpu1.itb.fetch_accesses 475104 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -954,558 +966,567 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16726806 # number of cpu cycles simulated +system.cpu1.numCycles 10299543 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6696452 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16370488 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4129053 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1187433 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 8741861 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 347188 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 25893 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 58137 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 49356 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1820963 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 76422 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15745356 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.039703 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.449166 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 3708105 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 10416725 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2642221 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 708563 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 5867887 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 223660 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 23709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 51632 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 40219 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1189367 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 46143 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9803421 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.062560 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.469546 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12876670 81.78% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 185062 1.18% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 297924 1.89% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 209767 1.33% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 372753 2.37% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 143050 0.91% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 159866 1.02% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 207293 1.32% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1292971 8.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7976409 81.36% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 98791 1.01% 82.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 205509 2.10% 84.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 143569 1.46% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 244577 2.49% 88.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 96035 0.98% 89.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 110446 1.13% 90.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 69630 0.71% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 858455 8.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15745356 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.246852 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.978698 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5498623 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7777976 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2045729 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 256320 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 166707 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 143442 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7016 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 13354105 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22028 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 166707 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5670233 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 826473 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5769862 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2131801 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1180278 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 12651091 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3750 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 88341 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 32960 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 615086 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 8374295 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 15046844 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 14984377 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 56291 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6609856 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1764431 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 476570 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 48769 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2080322 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2346654 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1454994 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 292964 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 152733 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11085695 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 541496 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10671183 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 25309 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2321405 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1075261 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 398456 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15745356 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.677735 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.406788 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9803421 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.256538 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.011377 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3120035 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 5128574 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1274002 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 173173 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 107636 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 84669 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4317 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8395667 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13790 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 107636 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3236399 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 505262 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3781107 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1330090 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 842925 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7927045 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 866 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 80988 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18891 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 445625 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 5308652 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9558760 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9526496 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 27580 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4111841 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1196803 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 316905 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22710 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1429971 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1508631 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 873340 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 185286 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 107493 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6977977 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 344578 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6652421 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 19333 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1592530 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 796148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 266679 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9803421 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.678582 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.403550 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11382155 72.29% 72.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1870956 11.88% 84.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 802175 5.09% 89.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 575742 3.66% 92.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 534921 3.40% 96.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 285738 1.81% 98.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 185455 1.18% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 78165 0.50% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 30049 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 7053571 71.95% 71.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1194265 12.18% 84.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 509519 5.20% 89.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 375157 3.83% 93.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 322481 3.29% 96.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 169260 1.73% 98.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 99294 1.01% 99.19% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 57333 0.58% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 22541 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15745356 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9803421 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 27488 9.05% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 170713 56.19% 65.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 105586 34.76% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24978 11.96% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 116023 55.55% 67.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 67859 32.49% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3991 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6611083 61.95% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16524 0.15% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12068 0.11% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1990 0.02% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2360403 22.12% 84.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1384355 12.97% 97.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 280769 2.63% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3973 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 4085085 61.41% 61.47% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10572 0.16% 61.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10292 0.15% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1521104 22.87% 84.68% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 824727 12.40% 97.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 194682 2.93% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10671183 # Type of FU issued -system.cpu1.iq.rate 0.637969 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 303787 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 37199457 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 13849868 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10195275 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 217360 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 103372 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 100900 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10854739 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 116240 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 112250 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6652421 # Type of FU issued +system.cpu1.iq.rate 0.645895 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 208860 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.031396 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 23247701 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8874149 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6353252 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 88754 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 44866 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 42405 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6811194 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 46114 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 75849 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 494389 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1075 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4794 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 168808 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 328260 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 949 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4058 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 119869 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 442 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 89761 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 415 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 72546 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 166707 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 440216 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 341566 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 12247032 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 53191 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2346654 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1454994 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 491166 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 5461 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 335179 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4794 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 42007 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 137108 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 179115 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10495256 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2269179 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 175926 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 107636 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 325014 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 147509 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7654698 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 36160 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1508631 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 873340 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 319432 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4857 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 141756 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4058 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 24786 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 89639 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 114425 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6540293 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1470121 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 112127 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 619841 # number of nop insts executed -system.cpu1.iew.exec_refs 3634984 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1567515 # Number of branches executed -system.cpu1.iew.exec_stores 1365805 # Number of stores executed -system.cpu1.iew.exec_rate 0.627451 # Inst execution rate -system.cpu1.iew.wb_sent 10344393 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 10296175 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4904906 # num instructions producing a value -system.cpu1.iew.wb_consumers 6922372 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.615549 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708559 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2337439 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 143040 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 155210 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 15327667 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.637432 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.616488 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 332143 # number of nop insts executed +system.cpu1.iew.exec_refs 2281164 # number of memory reference insts executed +system.cpu1.iew.exec_branches 956130 # Number of branches executed +system.cpu1.iew.exec_stores 811043 # Number of stores executed +system.cpu1.iew.exec_rate 0.635008 # Inst execution rate +system.cpu1.iew.wb_sent 6430736 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6395657 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3121788 # num instructions producing a value +system.cpu1.iew.wb_consumers 4363189 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.620965 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.715483 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1558734 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 77899 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 97361 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9525282 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.626287 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.584809 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11807980 77.04% 77.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1622081 10.58% 87.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 578152 3.77% 91.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 357481 2.33% 93.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 274261 1.79% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 117588 0.77% 96.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 104376 0.68% 96.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 117710 0.77% 97.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 348038 2.27% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 7314942 76.80% 76.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1051446 11.04% 87.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 355573 3.73% 91.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 228997 2.40% 93.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 163534 1.72% 95.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 72316 0.76% 96.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 75781 0.80% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 55973 0.59% 97.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 206720 2.17% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 15327667 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9770342 # Number of instructions committed -system.cpu1.commit.committedOps 9770342 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 9525282 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 5965556 # Number of instructions committed +system.cpu1.commit.committedOps 5965556 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3138451 # Number of memory references committed -system.cpu1.commit.loads 1852265 # Number of loads committed -system.cpu1.commit.membars 45725 # Number of memory barriers committed -system.cpu1.commit.branches 1397481 # Number of branches committed -system.cpu1.commit.fp_insts 99132 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9064844 # Number of committed integer instructions. -system.cpu1.commit.function_calls 152839 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 468541 4.80% 4.80% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5805964 59.42% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16275 0.17% 64.39% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 12061 0.12% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1990 0.02% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1897990 19.43% 83.96% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1286752 13.17% 97.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 280769 2.87% 100.00% # Class of committed instruction +system.cpu1.commit.refs 1933842 # Number of memory references committed +system.cpu1.commit.loads 1180371 # Number of loads committed +system.cpu1.commit.membars 21608 # Number of memory barriers committed +system.cpu1.commit.branches 842250 # Number of branches committed +system.cpu1.commit.fp_insts 40666 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5575941 # Number of committed integer instructions. +system.cpu1.commit.function_calls 91630 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 239508 4.01% 4.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 3553035 59.56% 63.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 10403 0.17% 63.75% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10285 0.17% 63.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1201979 20.15% 84.10% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 753678 12.63% 96.74% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 194682 3.26% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 9770342 # Class of committed instruction -system.cpu1.commit.bw_lim_events 348038 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 26989101 # The number of ROB reads -system.cpu1.rob.rob_writes 24630830 # The number of ROB writes -system.cpu1.timesIdled 131471 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 981450 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3841428948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9305781 # Number of Instructions Simulated -system.cpu1.committedOps 9305781 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.797464 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.797464 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556339 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556339 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13488576 # number of integer regfile reads -system.cpu1.int_regfile_writes 7349661 # number of integer regfile writes -system.cpu1.fp_regfile_reads 55714 # number of floating regfile reads -system.cpu1.fp_regfile_writes 55051 # number of floating regfile writes -system.cpu1.misc_regfile_reads 538402 # number of misc regfile reads -system.cpu1.misc_regfile_writes 228232 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 120114 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.559727 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2854712 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 120626 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.665810 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 62007957000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.559727 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950312 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.950312 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 5965556 # Class of committed instruction +system.cpu1.commit.bw_lim_events 206720 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 16752551 # The number of ROB reads +system.cpu1.rob.rob_writes 15324043 # The number of ROB writes +system.cpu1.timesIdled 69166 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 496122 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3807004634 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5730020 # Number of Instructions Simulated +system.cpu1.committedOps 5730020 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.797471 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.797471 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556337 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556337 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8470716 # number of integer regfile reads +system.cpu1.int_regfile_writes 4619691 # number of integer regfile writes +system.cpu1.fp_regfile_reads 26922 # number of floating regfile reads +system.cpu1.fp_regfile_writes 25344 # number of floating regfile writes +system.cpu1.misc_regfile_reads 302216 # number of misc regfile reads +system.cpu1.misc_regfile_writes 137559 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 64410 # number of replacements +system.cpu1.dcache.tags.tagsinuse 463.614906 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1794834 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 64922 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.646006 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1880101020500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.614906 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905498 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.905498 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13510694 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13510694 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1801260 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1801260 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 972413 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 972413 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 37246 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 37246 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 33039 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 33039 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2773673 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2773673 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2773673 # number of overall hits -system.cpu1.dcache.overall_hits::total 2773673 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 221542 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 221542 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 271468 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 271468 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5109 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5109 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3089 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3089 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 493010 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 493010 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 493010 # number of overall misses -system.cpu1.dcache.overall_misses::total 493010 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2936746000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2936746000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12570320655 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12570320655 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51167000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 51167000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47352500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 47352500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15507066655 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15507066655 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15507066655 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15507066655 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2022802 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2022802 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1243881 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1243881 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 42355 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 42355 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 36128 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 36128 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3266683 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3266683 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3266683 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3266683 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109522 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.109522 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218243 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.218243 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120623 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120623 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085502 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085502 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.150921 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.150921 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.150921 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.150921 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13255.933412 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13255.933412 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46304.981269 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 46304.981269 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10015.071443 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10015.071443 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15329.394626 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15329.394626 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 31453.858248 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 759613 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1583 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 22564 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks -system.cpu1.dcache.writebacks::total 79554 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 136401 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 226329 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 226329 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 689 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 689 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 362730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 362730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 362730 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 362730 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 85141 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 85141 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45139 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 45139 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4420 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4420 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3085 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3085 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 130280 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 130280 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 130280 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 130280 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2990 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2990 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3152 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3152 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1075350000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1075350000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2078906462 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2078906462 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39137500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39137500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44267500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44267500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3154256462 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3154256462 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036289 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104356 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104356 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085391 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085391 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039881 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039881 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12630.225156 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12630.225156 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46055.660560 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46055.660560 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8854.638009 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8854.638009 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 244089 # number of replacements -system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 244601 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.398997 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1896682174500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 469.435893 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.916867 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.916867 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2065632 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2065632 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1565201 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1565201 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1565201 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1565201 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1565201 # number of overall hits -system.cpu1.icache.overall_hits::total 1565201 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 255762 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 255762 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 255762 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 255762 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 255762 # number of overall misses -system.cpu1.icache.overall_misses::total 255762 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3690348499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3690348499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3690348499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3690348499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3690348499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3690348499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1820963 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1820963 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1820963 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1820963 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1820963 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1820963 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.140454 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.140454 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.140454 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.140454 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.140454 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.140454 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14428.838135 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14428.838135 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14428.838135 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14428.838135 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 721 # number of cycles access was blocked +system.cpu1.dcache.tags.tag_accesses 8336582 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 8336582 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1188882 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1188882 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 570377 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 570377 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16198 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16198 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15147 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15147 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1759259 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1759259 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1759259 # number of overall hits +system.cpu1.dcache.overall_hits::total 1759259 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 111545 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 111545 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 161954 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 161954 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1739 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1739 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 840 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 840 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 273499 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 273499 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 273499 # number of overall misses +system.cpu1.dcache.overall_misses::total 273499 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1447207500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1447207500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7450335261 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7450335261 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 18882500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 18882500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6469000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6469000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 34500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 34500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8897542761 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8897542761 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8897542761 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8897542761 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1300427 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1300427 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 732331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 732331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 17937 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 17937 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15987 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15987 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2032758 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2032758 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2032758 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2032758 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.085776 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.085776 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221149 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.221149 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.096950 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.096950 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.052543 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.052543 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134546 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134546 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134546 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134546 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12974.203236 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12974.203236 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46002.786353 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46002.786353 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10858.251869 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10858.251869 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7701.190476 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7701.190476 # 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average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 49 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 38002 # number of writebacks +system.cpu1.dcache.writebacks::total 38002 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 65961 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 65961 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137427 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 137427 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 372 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 372 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 203388 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 203388 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 203388 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 203388 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 45584 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 45584 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24527 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 24527 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1367 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1367 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 840 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 840 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 70111 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 70111 # 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number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1170679567 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13141000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13141000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5630000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5630000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 33500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 33500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1745879567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1745879567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1745879567 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1745879567 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29635500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29635500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 29635500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 29635500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035053 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035053 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033492 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033492 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076211 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076211 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.052543 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.052543 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034491 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034491 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.462618 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12618.462618 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47730.238798 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47730.238798 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9613.021214 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9613.021214 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6702.380952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6702.380952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202982.876712 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202982.876712 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10855.494505 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10855.494505 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 125381 # number of replacements +system.cpu1.icache.tags.tagsinuse 466.454678 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1056750 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 125892 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.394100 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880706304500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.454678 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911044 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.911044 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1315314 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1315314 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1056751 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1056751 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1056751 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1056751 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1056751 # number of overall hits +system.cpu1.icache.overall_hits::total 1056751 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 132616 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 132616 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 132616 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 132616 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 132616 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14229.278518 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14229.278518 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.193548 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 244669 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 244669 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3289647499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3289647499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3289647499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3289647499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3289647499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3289647499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.134362 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.134362 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.134362 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 125381 # number of writebacks +system.cpu1.icache.writebacks::total 125381 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6669 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6669 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6669 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6669 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6669 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6669 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 125947 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 125947 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 125947 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 125947 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 125947 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 125947 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1682313500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1682313500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1682313500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1682313500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1682313500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1682313500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105894 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.105894 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.105894 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.312997 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1518,98 +1539,98 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7368 # Transaction distribution -system.iobus.trans_dist::ReadResp 7368 # Transaction distribution -system.iobus.trans_dist::WriteReq 54647 # Transaction distribution -system.iobus.trans_dist::WriteResp 54647 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11984 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7381 # Transaction distribution +system.iobus.trans_dist::ReadResp 7381 # Transaction distribution +system.iobus.trans_dist::WriteReq 53943 # Transaction distribution +system.iobus.trans_dist::WriteResp 53943 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10586 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 124030 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122648 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 74130 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735754 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12444500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68539 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661680 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661680 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2730219 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 10864500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 814000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 814501 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 176000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14015000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14057500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6047501 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6034500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215709165 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216209541 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27481000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26789000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41964000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.551900 # Cycle average of tags in use +system.iocache.tags.replacements 41702 # number of replacements +system.iocache.tags.tagsinuse 0.516326 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41718 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1726981964000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.551900 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.034494 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.034494 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712300449000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.516326 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.032270 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.032270 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375606 # Number of tag accesses +system.iocache.tags.data_accesses 375606 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 182 # number of ReadReq misses +system.iocache.ReadReq_misses::total 182 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41734 # number of demand (read+write) misses +system.iocache.demand_misses::total 41734 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41734 # number of overall misses +system.iocache.overall_misses::total 41734 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22913883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22913883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4860118658 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4860118658 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4883032541 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4883032541 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4883032541 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4883032541 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 182 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 182 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41734 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41734 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41734 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41734 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1618,38 +1639,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125900.456044 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125900.456044 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116964.734742 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116964.734742 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 117003.703000 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 117003.703000 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 117003.703000 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 117003.703000 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 37 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 182 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3179057867 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3179057867 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3179057867 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3179057867 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41734 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41734 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41734 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41734 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13813883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13813883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2780093407 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2780093407 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2793907290 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2793907290 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2793907290 # 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miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014676 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.305308 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007930 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.091192 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.162116 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 959.240133 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15228.125000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5130.775255 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6697.004608 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 875.838926 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3743.473326 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138400.156420 # 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average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 158658.284709 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 129335.602509 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 134408.197579 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 128301.446866 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 136366.752577 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 158658.284709 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 129335.602509 # average overall miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75900.456044 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75900.456044 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66906.368093 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66906.368093 # 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mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013294 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.259785 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.018459 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250594 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.289149 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.143788 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.161097 # 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average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210123.422657 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190482.876712 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209725.100708 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87900.385528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10186.996337 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77070.495151 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 843888 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 393117 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 439 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 297053 # Transaction distribution +system.membus.trans_dist::WriteReq 12391 # Transaction distribution +system.membus.trans_dist::WriteResp 12391 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122655 # Transaction distribution +system.membus.trans_dist::CleanEvict 262560 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5361 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1592 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121253 # Transaction distribution -system.membus.trans_dist::ReadExResp 120834 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290100 # Transaction distribution -system.membus.trans_dist::BadAddressError 46 # Transaction distribution +system.membus.trans_dist::ReadExReq 120253 # Transaction distribution +system.membus.trans_dist::ReadExResp 120107 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289902 # Transaction distribution +system.membus.trans_dist::BadAddressError 48 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182230 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1222898 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306335 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 74130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31481536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31555666 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1169885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 96 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1209161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83451 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83451 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1292612 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68539 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31400256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31468795 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34213906 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 12142 # Total snoops (count) -system.membus.snoop_fanout::samples 875570 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 34127035 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 4109 # Total snoops (count) +system.membus.snoop_fanout::samples 478250 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001409 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037514 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 875570 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 477576 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 674 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 875570 # Request fanout histogram -system.membus.reqLayer0.occupancy 36438999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 478250 # Request fanout histogram +system.membus.reqLayer0.occupancy 34894499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1356482971 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1351079796 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2177455750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2171993250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 936113 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 976613 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 5114760 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2557108 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 345514 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1336 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5115302 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2557070 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 337938 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1067 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2266679 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13095 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13095 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 943643 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1155325 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 827144 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10512 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6044 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16556 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 299688 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 299688 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1156637 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1102911 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 46 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2735017 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3843601 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 733385 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 384537 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7696540 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116675136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128186756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31277824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12692238 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288831954 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 463427 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3024601 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.120612 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.326035 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2263337 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12391 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12391 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 911885 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1146691 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 834780 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5446 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1712 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 7158 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 303166 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 303166 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1147985 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1108204 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 48 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 217 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3065153 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4053991 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 377239 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 207014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7703397 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 130759360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 136128589 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16082688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6548014 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 289518651 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 362547 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2930720 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.118515 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.323634 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2660134 87.95% 87.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 364147 12.04% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 303 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 17 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2583760 88.16% 88.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 346605 11.83% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 335 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3024601 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4550078915 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2930720 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4551122919 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 295885 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 306385 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1369499398 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1534824957 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1926492121 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2028150819 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 368355265 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 190444943 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 200907831 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 107558787 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2131,170 +2160,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 180918 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 63985 40.38% 40.38% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.47% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1935 1.22% 41.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 191 0.12% 41.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92196 58.19% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158438 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 62993 49.19% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1935 1.51% 50.81% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 191 0.15% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 62802 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128052 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1871632607000 97.04% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 66355000 0.00% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 578065000 0.03% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 91849500 0.00% 97.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56349581000 2.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1928718457500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984496 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 198541 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71138 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.08% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1928 1.10% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 20 0.01% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 101928 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 175147 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69801 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.09% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 20 0.01% 50.74% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 69782 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141664 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864307233500 97.69% 97.69% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 66845500 0.00% 97.70% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 580922500 0.03% 97.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 11315500 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 43373119000 2.27% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1908339436000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981206 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681179 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808215 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.68% 3.68% # number of syscalls executed -system.cpu0.kern.syscall::3 15 7.89% 11.58% # number of syscalls executed -system.cpu0.kern.syscall::4 4 2.11% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 28 14.74% 28.42% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.53% 28.95% # number of syscalls executed -system.cpu0.kern.syscall::17 8 4.21% 33.16% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.68% 36.84% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.11% 38.95% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.53% 39.47% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.58% 41.05% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.16% 44.21% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.05% 45.26% # number of syscalls executed -system.cpu0.kern.syscall::45 31 16.32% 61.58% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.58% 63.16% # number of syscalls executed -system.cpu0.kern.syscall::48 8 4.21% 67.37% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.74% 72.11% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.53% 72.63% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.63% 75.26% # number of syscalls executed -system.cpu0.kern.syscall::71 21 11.05% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.58% 87.89% # number of syscalls executed -system.cpu0.kern.syscall::74 5 2.63% 90.53% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.53% 91.05% # number of syscalls executed -system.cpu0.kern.syscall::90 2 1.05% 92.11% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.68% 95.79% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.05% 96.84% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.05% 97.89% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.53% 98.42% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.53% 98.95% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.05% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 190 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684621 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808829 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.70% 3.70% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.33% 12.04% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.85% 13.89% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.81% 28.70% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.46% 29.17% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.70% 32.87% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.63% 37.50% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.78% 40.28% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.46% 40.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.39% 42.13% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.78% 44.91% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.93% 45.83% # number of syscalls executed +system.cpu0.kern.syscall::45 33 15.28% 61.11% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.39% 62.50% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.63% 67.13% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.63% 71.76% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.46% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.78% 75.00% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.65% 85.65% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.39% 87.04% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.78% 89.81% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.46% 90.28% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.39% 91.67% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.17% 95.83% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.93% 96.76% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.93% 97.69% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.46% 98.15% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 216 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 292 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3426 2.05% 2.23% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151781 91.02% 93.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6336 3.80% 97.08% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.08% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.08% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.09% # number of callpals executed -system.cpu0.kern.callpal::rti 4399 2.64% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 318 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 166759 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6855 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1159 # number of protection mode switches +system.cpu0.kern.callpal::wripir 116 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3824 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpipl 168401 91.54% 93.72% # number of callpals executed +system.cpu0.kern.callpal::rdps 6369 3.46% 97.18% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::rti 4665 2.54% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 183960 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7174 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1159 -system.cpu0.kern.mode_good::user 1159 +system.cpu0.kern.mode_good::kernel 1257 +system.cpu0.kern.mode_good::user 1257 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.169074 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175216 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.289244 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1925885387000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1988942000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298185 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1906404052500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1926707500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3427 # number of times the context was actually changed +system.cpu0.kern.swap_context 3825 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2571 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 58929 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18404 37.04% 37.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1933 3.89% 40.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 292 0.59% 41.51% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 29063 58.49% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49692 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 18019 47.45% 47.45% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1933 5.09% 52.55% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 292 0.77% 53.31% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17727 46.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37971 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1882485952500 97.58% 97.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 565596500 0.03% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 145516500 0.01% 97.62% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45879988500 2.38% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1929077054000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979081 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2309 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39314 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10555 33.51% 33.51% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 6.11% 39.62% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 116 0.37% 39.99% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18905 60.01% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 31502 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10515 45.81% 45.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 8.39% 54.19% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 116 0.51% 54.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10399 45.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22956 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1877342030500 98.36% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 564972500 0.03% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 56160500 0.00% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 30688096500 1.61% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1908651260000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.996210 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.609951 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.764127 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.74% 0.74% # number of syscalls executed -system.cpu1.kern.syscall::3 15 11.03% 11.76% # number of syscalls executed -system.cpu1.kern.syscall::6 14 10.29% 22.06% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.74% 22.79% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.15% 27.94% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.21% 30.15% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.47% 31.62% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.21% 33.82% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.21% 36.03% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.68% 39.71% # number of syscalls executed -system.cpu1.kern.syscall::45 23 16.91% 56.62% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.21% 58.82% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.47% 60.29% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.74% 61.03% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.47% 62.50% # number of syscalls executed -system.cpu1.kern.syscall::71 33 24.26% 86.76% # number of syscalls executed -system.cpu1.kern.syscall::74 11 8.09% 94.85% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.74% 95.59% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.47% 97.06% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.21% 99.26% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.74% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 136 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.550066 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.728716 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 12 10.91% 10.91% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.09% 20.00% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.91% 20.91% # number of syscalls executed +system.cpu1.kern.syscall::17 7 6.36% 27.27% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.73% 30.00% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.73% 32.73% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.55% 37.27% # number of syscalls executed +system.cpu1.kern.syscall::45 21 19.09% 56.36% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.73% 59.09% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.91% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::71 31 28.18% 88.18% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.09% 97.27% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.73% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 110 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 191 0.37% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1171 2.27% 2.65% # number of callpals executed -system.cpu1.kern.callpal::tbi 5 0.01% 2.66% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed -system.cpu1.kern.callpal::swpipl 44279 85.92% 88.59% # number of callpals executed -system.cpu1.kern.callpal::rdps 2440 4.73% 93.33% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.33% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.34% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.34% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.34% # number of callpals executed -system.cpu1.kern.callpal::rti 3187 6.18% 99.53% # number of callpals executed -system.cpu1.kern.callpal::callsys 197 0.38% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 20 0.06% 0.06% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu1.kern.callpal::swpctx 440 1.35% 1.42% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.43% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.45% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26890 82.68% 84.13% # number of callpals executed +system.cpu1.kern.callpal::rdps 2393 7.36% 91.49% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.50% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.51% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.52% # number of callpals executed +system.cpu1.kern.callpal::rti 2569 7.90% 99.42% # number of callpals executed +system.cpu1.kern.callpal::callsys 144 0.44% 99.86% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 51536 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1550 # number of protection mode switches -system.cpu1.kern.mode_switch::user 578 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 794 -system.cpu1.kern.mode_good::user 578 -system.cpu1.kern.mode_good::idle 216 -system.cpu1.kern.mode_switch_good::kernel 0.512258 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 32523 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 900 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2082 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 529 +system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_good::idle 41 +system.cpu1.kern.mode_switch_good::kernel 0.587778 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.088670 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.347940 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4980780500 0.26% 0.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 920793000 0.05% 0.31% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1923175472500 99.69% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1172 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.019693 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.304899 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2122812500 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 785064000 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1905743375500 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 441 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |