diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3771 |
1 files changed, 1882 insertions, 1889 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 5cabf17a2..2b53a578a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.905651 # Number of seconds simulated -sim_ticks 1905651402000 # Number of ticks simulated -final_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906207 # Number of seconds simulated +sim_ticks 1906207240000 # Number of ticks simulated +final_tick 1906207240000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124387 # Simulator instruction rate (inst/s) -host_op_rate 124387 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4179760275 # Simulator tick rate (ticks/s) -host_mem_usage 352908 # Number of bytes of host memory used -host_seconds 455.92 # Real time elapsed on the host -sim_insts 56710998 # Number of instructions simulated -sim_ops 56710998 # Number of ops (including micro ops) simulated +host_inst_rate 147655 # Simulator instruction rate (inst/s) +host_op_rate 147655 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5021061637 # Simulator tick rate (ticks/s) +host_mem_usage 308576 # Number of bytes of host memory used +host_seconds 379.64 # Real time elapsed on the host +sim_insts 56056069 # Number of instructions simulated +sim_ops 56056069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory -system.physmem.bytes_read::total 28857792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory -system.physmem.bytes_written::total 7816896 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450903 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122139 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450903 # Number of read requests accepted -system.physmem.writeReqs 122139 # Number of write requests accepted -system.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue -system.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 903488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24906304 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 74560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 378304 # Number of bytes read from this memory +system.physmem.bytes_read::total 28912320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 903488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 74560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7848000 # Number of bytes written to this memory +system.physmem.bytes_written::total 7848000 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389161 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5911 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451755 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122625 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122625 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 473972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13065895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1390019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 39114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15167459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 473972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 39114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4117076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4117076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4117076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 473972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13065895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1390019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 39114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 198459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19284535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451755 # Number of read requests accepted +system.physmem.writeReqs 122625 # Number of write requests accepted +system.physmem.readBursts 451755 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122625 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28904128 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7846080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28912320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7848000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28020 # Per bank write bursts -system.physmem.perBankRdBursts::1 28240 # Per bank write bursts -system.physmem.perBankRdBursts::2 28746 # Per bank write bursts -system.physmem.perBankRdBursts::3 28309 # Per bank write bursts -system.physmem.perBankRdBursts::4 27973 # Per bank write bursts -system.physmem.perBankRdBursts::5 28180 # Per bank write bursts -system.physmem.perBankRdBursts::6 28116 # Per bank write bursts -system.physmem.perBankRdBursts::7 27456 # Per bank write bursts -system.physmem.perBankRdBursts::8 27700 # Per bank write bursts -system.physmem.perBankRdBursts::9 28070 # Per bank write bursts -system.physmem.perBankRdBursts::10 27744 # Per bank write bursts -system.physmem.perBankRdBursts::11 28151 # Per bank write bursts -system.physmem.perBankRdBursts::12 28476 # Per bank write bursts -system.physmem.perBankRdBursts::13 28764 # Per bank write bursts -system.physmem.perBankRdBursts::14 28477 # Per bank write bursts -system.physmem.perBankRdBursts::15 28339 # Per bank write bursts -system.physmem.perBankWrBursts::0 7807 # Per bank write bursts -system.physmem.perBankWrBursts::1 7750 # Per bank write bursts -system.physmem.perBankWrBursts::2 8222 # Per bank write bursts -system.physmem.perBankWrBursts::3 7743 # Per bank write bursts -system.physmem.perBankWrBursts::4 7390 # Per bank write bursts -system.physmem.perBankWrBursts::5 7636 # Per bank write bursts -system.physmem.perBankWrBursts::6 7609 # Per bank write bursts -system.physmem.perBankWrBursts::7 6913 # Per bank write bursts -system.physmem.perBankWrBursts::8 6944 # Per bank write bursts -system.physmem.perBankWrBursts::9 7275 # Per bank write bursts -system.physmem.perBankWrBursts::10 7157 # Per bank write bursts -system.physmem.perBankWrBursts::11 7547 # Per bank write bursts -system.physmem.perBankWrBursts::12 7916 # Per bank write bursts -system.physmem.perBankWrBursts::13 8234 # Per bank write bursts -system.physmem.perBankWrBursts::14 8082 # Per bank write bursts -system.physmem.perBankWrBursts::15 7890 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3217 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28097 # Per bank write bursts +system.physmem.perBankRdBursts::1 28602 # Per bank write bursts +system.physmem.perBankRdBursts::2 29043 # Per bank write bursts +system.physmem.perBankRdBursts::3 27571 # Per bank write bursts +system.physmem.perBankRdBursts::4 27384 # Per bank write bursts +system.physmem.perBankRdBursts::5 27564 # Per bank write bursts +system.physmem.perBankRdBursts::6 27744 # Per bank write bursts +system.physmem.perBankRdBursts::7 27694 # Per bank write bursts +system.physmem.perBankRdBursts::8 27865 # Per bank write bursts +system.physmem.perBankRdBursts::9 28720 # Per bank write bursts +system.physmem.perBankRdBursts::10 28531 # Per bank write bursts +system.physmem.perBankRdBursts::11 28618 # Per bank write bursts +system.physmem.perBankRdBursts::12 28938 # Per bank write bursts +system.physmem.perBankRdBursts::13 28977 # Per bank write bursts +system.physmem.perBankRdBursts::14 28277 # Per bank write bursts +system.physmem.perBankRdBursts::15 28002 # Per bank write bursts +system.physmem.perBankWrBursts::0 7839 # Per bank write bursts +system.physmem.perBankWrBursts::1 8045 # Per bank write bursts +system.physmem.perBankWrBursts::2 8418 # Per bank write bursts +system.physmem.perBankWrBursts::3 7040 # Per bank write bursts +system.physmem.perBankWrBursts::4 6886 # Per bank write bursts +system.physmem.perBankWrBursts::5 7040 # Per bank write bursts +system.physmem.perBankWrBursts::6 7326 # Per bank write bursts +system.physmem.perBankWrBursts::7 7097 # Per bank write bursts +system.physmem.perBankWrBursts::8 7158 # Per bank write bursts +system.physmem.perBankWrBursts::9 7908 # Per bank write bursts +system.physmem.perBankWrBursts::10 7739 # Per bank write bursts +system.physmem.perBankWrBursts::11 7821 # Per bank write bursts +system.physmem.perBankWrBursts::12 8331 # Per bank write bursts +system.physmem.perBankWrBursts::13 8401 # Per bank write bursts +system.physmem.perBankWrBursts::14 7959 # Per bank write bursts +system.physmem.perBankWrBursts::15 7587 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1905651381000 # Total gap between requests +system.physmem.totGap 1906202745000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 450903 # Read request sizes (log2) +system.physmem.readPktSize::6 451755 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122139 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122625 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 319401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 41325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -158,358 +158,359 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 549.396161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 336.305192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 420.466175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14808 22.14% 22.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11177 16.71% 38.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5157 7.71% 46.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2881 4.31% 50.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2294 3.43% 54.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1713 2.56% 56.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1492 2.23% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1822 2.72% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25548 38.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66892 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7192 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 62.794355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2475.959084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 7189 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7192 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7192 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.046023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.810949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.823344 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5742 79.84% 79.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 42 0.58% 80.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 691 9.61% 90.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 254 3.53% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 102 1.42% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 28 0.39% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.39% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 90 1.25% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.14% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 32 0.44% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 22 0.31% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 14 0.19% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 15 0.21% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 7 0.10% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 9 0.13% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 23 0.32% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.15% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.03% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 4 0.06% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 1 0.01% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 8 0.11% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 4 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 13 0.18% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 13 0.18% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads -system.physmem.totQLat 8930594750 # Total ticks spent queuing -system.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 7192 # Writes before turning the bus around for reads +system.physmem.totQLat 9007685000 # Total ticks spent queuing +system.physmem.totMemAccLat 17475691250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2258135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19944.97 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38694.97 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing -system.physmem.readRowHits 407659 # Number of row buffer hits during reads -system.physmem.writeRowHits 98604 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes -system.physmem.avgGap 3325500.37 # Average gap between requests -system.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states -system.physmem.memoryStateTime::REF 63633700000 # Time in different power states +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing +system.physmem.readRowHits 408104 # Number of row buffer hits during reads +system.physmem.writeRowHits 99226 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes +system.physmem.avgGap 3318713.65 # Average gap between requests +system.physmem.pageHitRate 88.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1805036475500 # Time in different power states +system.physmem.memoryStateTime::REF 63652420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37488657000 # Time in different power states +system.physmem.memoryStateTime::ACT 37517744500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19303809 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296468 # Transaction distribution -system.membus.trans_dist::ReadResp 296393 # Transaction distribution -system.membus.trans_dist::WriteReq 13039 # Transaction distribution -system.membus.trans_dist::WriteResp 13039 # Transaction distribution -system.membus.trans_dist::Writeback 122139 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9699 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4861 # Transaction distribution -system.membus.trans_dist::ReadExReq 162690 # Transaction distribution -system.membus.trans_dist::ReadExResp 162297 # Transaction distribution -system.membus.trans_dist::BadAddressError 75 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36748378 # Total data (bytes) -system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks) +system.membus.throughput 19340215 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296416 # Transaction distribution +system.membus.trans_dist::ReadResp 296338 # Transaction distribution +system.membus.trans_dist::WriteReq 12317 # Transaction distribution +system.membus.trans_dist::WriteResp 12317 # Transaction distribution +system.membus.trans_dist::Writeback 122625 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1033 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3220 # Transaction distribution +system.membus.trans_dist::ReadExReq 163308 # Transaction distribution +system.membus.trans_dist::ReadExResp 163210 # Transaction distribution +system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39026 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 910934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 950116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1074769 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 67930 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31453376 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31521306 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5306944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36828250 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36828250 # Total data (bytes) +system.membus.snoop_data_through_bus 38208 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 36079499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1585687750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3823460772 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376710991 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 343977 # number of replacements -system.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use -system.l2c.tags.total_refs 2582565 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27108862 # Number of tag accesses -system.l2c.tags.data_accesses 27108862 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits -system.l2c.Writeback_hits::total 822208 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits -system.l2c.demand_hits::total 2062288 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 867616 # number of overall hits -system.l2c.overall_hits::cpu0.data 891053 # number of overall hits -system.l2c.overall_hits::cpu1.inst 210128 # number of overall hits -system.l2c.overall_hits::cpu1.data 93491 # number of overall hits -system.l2c.overall_hits::total 2062288 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3729 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 406 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 434 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 840 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114695 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6342 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121037 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14035 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 388087 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1238 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6794 # number of demand (read+write) misses -system.l2c.demand_misses::total 410154 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14035 # number of overall misses -system.l2c.overall_misses::cpu0.data 388087 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1238 # number of overall misses -system.l2c.overall_misses::cpu1.data 6794 # number of overall misses -system.l2c.overall_misses::total 410154 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1067454245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17881620237 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 96862500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 35356999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19081293981 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 964468 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4567794 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 5532262 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 972461 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114995 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1087456 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9393947733 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 639497214 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10033444947 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1067454245 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 27275567970 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 96862500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 674854213 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29114738928 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1067454245 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 27275567970 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 96862500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 674854213 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 455 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 458 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 913 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 269131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 31923 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301054 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 881651 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1279140 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 211366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 100285 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2472442 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 881651 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1279140 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 211366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 100285 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2472442 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015919 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.270683 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005857 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006612 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133148 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940535 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.801822 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.896610 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.892308 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947598 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.920044 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.426168 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.198666 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.402044 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015919 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.303397 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005857 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.067747 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165890 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015919 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.303397 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005857 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.067747 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165890 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76056.590310 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65406.523369 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78241.114701 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78223.449115 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65998.519565 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 360.818556 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4325.562500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1483.577903 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2395.224138 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 264.965438 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1294.590476 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81903.724949 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100835.259224 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 82895.684353 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70984.895742 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70984.895742 # average overall miss latency +system.l2c.tags.replacements 344852 # number of replacements +system.l2c.tags.tagsinuse 65305.335131 # Cycle average of tags in use +system.l2c.tags.total_refs 2605080 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 409986 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.354071 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7095487750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53708.677879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5228.517850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6139.451939 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 202.418952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 26.268512 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.819529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079781 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.093681 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003089 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000401 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996480 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65134 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 2578 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6338 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 50733 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.993866 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27313168 # Number of tag accesses +system.l2c.tags.data_accesses 27313168 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 979450 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 788527 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 94097 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 31413 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1893487 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 833565 # number of Writeback hits +system.l2c.Writeback_hits::total 833565 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 47 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 175693 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 7721 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183414 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 979450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 964220 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 94097 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 39134 # number of demand (read+write) hits +system.l2c.demand_hits::total 2076901 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 979450 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24251967180 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 892690758 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 22724477144 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 75058500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 559740778 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24251967180 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1368893000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 20915000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389808000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1950614000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 503814500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2454428500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3319507000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524729500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3844236500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.257469 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010676 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132433 # 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average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 300064.516380 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 300064.516380 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 367481 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122577.127778 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122577.127778 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299532.295509 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299532.295509 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 298769.045960 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 298769.045960 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 366756 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28552 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28394 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.870587 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.916673 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 180 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41732 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41732 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41732 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41732 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12701883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12701883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10283217961 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10283217961 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10295919844 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10295919844 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10295919844 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10295919844 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -735,14 +736,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -756,35 +757,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12477942 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits +system.cpu0.branchPred.lookups 13535285 # Number of BP lookups +system.cpu0.branchPred.condPredicted 11399113 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 368683 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9302001 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5741441 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 61.722644 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 871515 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32576 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8879185 # DTB read hits -system.cpu0.dtb.read_misses 30734 # DTB read misses -system.cpu0.dtb.read_acv 556 # DTB read access violations -system.cpu0.dtb.read_accesses 627584 # DTB read accesses -system.cpu0.dtb.write_hits 5815647 # DTB write hits -system.cpu0.dtb.write_misses 8173 # DTB write misses -system.cpu0.dtb.write_acv 357 # DTB write access violations -system.cpu0.dtb.write_accesses 210225 # DTB write accesses -system.cpu0.dtb.data_hits 14694832 # DTB hits -system.cpu0.dtb.data_misses 38907 # DTB misses -system.cpu0.dtb.data_acv 913 # DTB access violations -system.cpu0.dtb.data_accesses 837809 # DTB accesses -system.cpu0.itb.fetch_hits 998260 # ITB hits -system.cpu0.itb.fetch_misses 27519 # ITB misses -system.cpu0.itb.fetch_acv 894 # ITB acv -system.cpu0.itb.fetch_accesses 1025779 # ITB accesses +system.cpu0.dtb.read_hits 9655924 # DTB read hits +system.cpu0.dtb.read_misses 34371 # DTB read misses +system.cpu0.dtb.read_acv 569 # DTB read access violations +system.cpu0.dtb.read_accesses 673777 # DTB read accesses +system.cpu0.dtb.write_hits 6329246 # DTB write hits +system.cpu0.dtb.write_misses 8477 # DTB write misses +system.cpu0.dtb.write_acv 351 # DTB write access violations +system.cpu0.dtb.write_accesses 236111 # DTB write accesses +system.cpu0.dtb.data_hits 15985170 # DTB hits +system.cpu0.dtb.data_misses 42848 # DTB misses +system.cpu0.dtb.data_acv 920 # DTB access violations +system.cpu0.dtb.data_accesses 909888 # DTB accesses +system.cpu0.itb.fetch_hits 1092484 # ITB hits +system.cpu0.itb.fetch_misses 31809 # ITB misses +system.cpu0.itb.fetch_acv 996 # ITB acv +system.cpu0.itb.fetch_accesses 1124293 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -797,303 +798,304 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 116074371 # number of cpu cycles simulated +system.cpu0.numCycles 120980731 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 27854466 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69491073 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13535285 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6612956 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12980522 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1985487 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37586938 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31052 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 209286 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 361146 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8301805 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 269407 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 80329317 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.865077 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.209142 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67348795 83.84% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 826622 1.03% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1640547 2.04% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 764329 0.95% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2736993 3.41% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 565546 0.70% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 615994 0.77% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1025224 1.28% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4805267 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 80329317 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.111880 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.574398 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 28693302 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 37589637 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12241193 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 539176 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1266008 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 554913 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 40031 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 68046301 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 123637 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1266008 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 29596220 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 13874520 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19704370 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11366279 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4521918 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64294985 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 8881 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 963704 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 49626 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1581472 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 42969329 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 77993479 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77835647 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 147432 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36982529 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5986792 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1597094 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 233553 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9775023 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10212119 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6719453 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1264075 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 886942 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56810323 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2002217 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 55156303 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 107150 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7195907 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4115621 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1359252 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 80329317 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.686627 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.367653 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56644741 70.52% 70.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10637349 13.24% 83.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4503428 5.61% 89.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3111745 3.87% 93.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2708967 3.37% 96.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1473067 1.83% 98.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 832512 1.04% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 359476 0.45% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 58032 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 80329317 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 91428 11.87% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 367704 47.76% 59.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 310812 40.37% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3793 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37662855 68.28% 68.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60369 0.11% 68.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.40% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16864 0.03% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 10116560 18.34% 86.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6398898 11.60% 98.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 895081 1.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued -system.cpu0.iq.rate 0.443500 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 55156303 # Type of FU issued +system.cpu0.iq.rate 0.455910 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 769944 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013959 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 190884663 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65713674 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53746277 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 634353 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 307759 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 299045 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55590646 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 331808 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 587688 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1466473 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4362 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13302 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 593267 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18777 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 290466 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1266008 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10034082 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1132931 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 62323042 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 565721 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10212119 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6719453 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1762676 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 460962 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 503945 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13302 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186944 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 388547 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 575491 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54610252 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9715916 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 546050 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3229636 # number of nop insts executed -system.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8136394 # Number of branches executed -system.cpu0.iew.exec_stores 5837466 # Number of stores executed -system.cpu0.iew.exec_rate 0.440174 # Inst execution rate -system.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25278333 # num instructions producing a value -system.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value +system.cpu0.iew.exec_nop 3510502 # number of nop insts executed +system.cpu0.iew.exec_refs 16068148 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8653897 # Number of branches executed +system.cpu0.iew.exec_stores 6352232 # Number of stores executed +system.cpu0.iew.exec_rate 0.451396 # Inst execution rate +system.cpu0.iew.wb_sent 54145867 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 54045322 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 27468175 # num instructions producing a value +system.cpu0.iew.wb_consumers 37895992 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.446727 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.724831 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7798809 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 642965 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 531823 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 79063309 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.688507 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.631609 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 59272342 74.97% 74.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8075780 10.21% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4311536 5.45% 90.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2381088 3.01% 93.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1583020 2.00% 95.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 598155 0.76% 96.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 490827 0.62% 97.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 478799 0.61% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1871762 2.37% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51248256 # Number of instructions committed -system.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 79063309 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 54435622 # Number of instructions committed +system.cpu0.commit.committedOps 54435622 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13810671 # Number of memory references committed -system.cpu0.commit.loads 8171492 # Number of loads committed -system.cpu0.commit.membars 199624 # Number of memory barriers committed -system.cpu0.commit.branches 7741114 # Number of branches committed -system.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47457125 # Number of committed integer instructions. -system.cpu0.commit.function_calls 657479 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 14871832 # Number of memory references committed +system.cpu0.commit.loads 8745646 # Number of loads committed +system.cpu0.commit.membars 219982 # Number of memory barriers committed +system.cpu0.commit.branches 8204799 # Number of branches committed +system.cpu0.commit.fp_insts 296843 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 50375539 # Number of committed integer instructions. +system.cpu0.commit.function_calls 712916 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 3148922 5.78% 5.78% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 35215746 64.69% 70.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 59292 0.11% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 16864 0.03% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8965628 16.47% 87.09% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 6132206 11.27% 98.36% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 895081 1.64% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 54435622 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1871762 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 130790454 # The number of ROB reads -system.cpu0.rob.rob_writes 116222813 # The number of ROB writes -system.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48300626 # Number of Instructions Simulated -system.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67219449 # number of integer regfile reads -system.cpu0.int_regfile_writes 36695614 # number of integer regfile writes -system.cpu0.fp_regfile_reads 128632 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130173 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads -system.cpu0.misc_regfile_writes 820377 # number of misc regfile writes +system.cpu0.rob.rob_reads 139225703 # The number of ROB reads +system.cpu0.rob.rob_writes 125735253 # The number of ROB writes +system.cpu0.timesIdled 1168278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 40651414 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3691427340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 51290467 # Number of Instructions Simulated +system.cpu0.committedOps 51290467 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.358737 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.358737 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423956 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423956 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71570668 # number of integer regfile reads +system.cpu0.int_regfile_writes 39014056 # number of integer regfile writes +system.cpu0.fp_regfile_reads 147010 # number of floating regfile reads +system.cpu0.fp_regfile_writes 148900 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1947197 # number of misc regfile reads +system.cpu0.misc_regfile_writes 897129 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1125,49 +1127,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111416521 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210926490 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks) +system.toL2Bus.throughput 111935595 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2200566 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2200471 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12317 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12317 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 833565 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4571 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1080 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5651 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 347592 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 306043 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1987262 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3563495 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 190571 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 127415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5868743 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63588928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 138451052 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 6097280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4501998 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 212639258 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 212628634 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 743808 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5019455896 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4476579522 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 6206391842 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 429200431 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 227242208 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1435370 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54591 # Transaction distribution -system.iobus.trans_dist::WriteResp 54591 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1431950 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 53869 # Transaction distribution +system.iobus.trans_dist::WriteResp 53869 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10422 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1178,12 +1180,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122490 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1194,14 +1196,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735314 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 67930 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729594 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729594 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9777000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1221,268 +1223,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380161835 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26709000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43245009 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 881127 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits -system.cpu0.icache.overall_hits::total 6795719 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses -system.cpu0.icache.overall_misses::total 926821 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 993039 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.694749 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7257459 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 993551 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.304566 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26718502250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.694749 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995498 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995498 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9295490 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9295490 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7257459 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7257459 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7257459 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7257459 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7257459 # number of overall hits +system.cpu0.icache.overall_hits::total 7257459 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1044346 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1044346 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1044346 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1044346 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1044346 # number of overall misses +system.cpu0.icache.overall_misses::total 1044346 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14667970749 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14667970749 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14667970749 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14667970749 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14667970749 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14667970749 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8301805 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8301805 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8301805 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8301805 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8301805 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8301805 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125797 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125797 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125797 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125797 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125797 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125797 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14045.125609 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14045.125609 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4303 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.642857 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50661 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50661 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 50661 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50661 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 50661 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50661 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 993685 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 993685 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 993685 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 993685 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 993685 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 993685 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12074149969 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12074149969 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12074149969 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12074149969 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12074149969 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12074149969 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119695 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.119695 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.119695 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1281204 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1357625 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.932074 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11305784 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1358137 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.324480 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25366000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.932074 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990102 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.990102 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits -system.cpu0.dcache.overall_hits::total 10126574 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses -system.cpu0.dcache.overall_misses::total 3345621 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 61088591 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 61088591 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6897589 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6897589 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4012977 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4012977 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181053 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 181053 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208423 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208423 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10910566 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10910566 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10910566 # number of overall hits +system.cpu0.dcache.overall_hits::total 10910566 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1718976 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1718976 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1889613 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1889613 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22934 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22934 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 507 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3608589 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3608589 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3608589 # number of overall misses +system.cpu0.dcache.overall_misses::total 3608589 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42674970043 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42674970043 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 81294445080 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 81294445080 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 374188245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 374188245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3007034 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3007034 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 123969415123 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 123969415123 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8616565 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8616565 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5902590 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5902590 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203987 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203987 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 208930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14519155 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14519155 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14519155 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14519155 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199497 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199497 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320133 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320133 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112429 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112429 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002427 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002427 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248540 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248540 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248540 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248540 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5931.033531 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5931.033531 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3433420 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 538 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 116463 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.480779 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 76.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks -system.cpu0.dcache.writebacks::total 754427 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 808609 # number of writebacks +system.cpu0.dcache.writebacks::total 808609 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 667238 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 667238 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1594728 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1594728 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5762 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5762 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2261966 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2261966 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2261966 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2261966 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1051738 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1051738 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 294885 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 294885 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17172 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17172 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 507 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1346623 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1346623 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1346623 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1346623 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27880739944 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27880739944 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12002536573 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12002536573 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 202887753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 202887753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1992966 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1992966 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39883276517 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 39883276517 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39883276517 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 39883276517 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1460997001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1460997001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2069284998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2069284998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3530281999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3530281999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122060 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122060 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049959 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049959 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084182 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084182 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002427 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002427 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092748 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092748 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3930.899408 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3930.899408 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1490,35 +1491,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2485884 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 831190 # Number of BTB hits +system.cpu1.branchPred.lookups 1483279 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1227619 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 44770 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 650934 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 463612 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.222582 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 99211 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4550 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1846757 # DTB read hits -system.cpu1.dtb.read_misses 10485 # DTB read misses -system.cpu1.dtb.read_acv 25 # DTB read access violations -system.cpu1.dtb.read_accesses 320297 # DTB read accesses -system.cpu1.dtb.write_hits 1188866 # DTB write hits -system.cpu1.dtb.write_misses 1998 # DTB write misses -system.cpu1.dtb.write_acv 67 # DTB write access violations -system.cpu1.dtb.write_accesses 130212 # DTB write accesses -system.cpu1.dtb.data_hits 3035623 # DTB hits -system.cpu1.dtb.data_misses 12483 # DTB misses -system.cpu1.dtb.data_acv 92 # DTB access violations -system.cpu1.dtb.data_accesses 450509 # DTB accesses -system.cpu1.itb.fetch_hits 420713 # ITB hits -system.cpu1.itb.fetch_misses 6600 # ITB misses -system.cpu1.itb.fetch_acv 223 # ITB acv -system.cpu1.itb.fetch_accesses 427313 # ITB accesses +system.cpu1.dtb.read_hits 1187167 # DTB read hits +system.cpu1.dtb.read_misses 8989 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 276351 # DTB read accesses +system.cpu1.dtb.write_hits 628916 # DTB write hits +system.cpu1.dtb.write_misses 1890 # DTB write misses +system.cpu1.dtb.write_acv 35 # DTB write access violations +system.cpu1.dtb.write_accesses 104365 # DTB write accesses +system.cpu1.dtb.data_hits 1816083 # DTB hits +system.cpu1.dtb.data_misses 10879 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 380716 # DTB accesses +system.cpu1.itb.fetch_hits 316911 # ITB hits +system.cpu1.itb.fetch_misses 5517 # ITB misses +system.cpu1.itb.fetch_acv 125 # ITB acv +system.cpu1.itb.fetch_accesses 322428 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1531,552 +1532,553 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14964653 # number of cpu cycles simulated +system.cpu1.numCycles 8637240 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 2818807 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 7093634 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1483279 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 562823 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1271731 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 278690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3719491 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 23500 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 54196 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48363 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 894062 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 29430 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 8117811 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.873836 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.252237 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 6846080 84.33% 84.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 64163 0.79% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 148479 1.83% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 110798 1.36% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 183312 2.26% 90.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 76211 0.94% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 83539 1.03% 92.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 57250 0.71% 93.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 547979 6.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 8117811 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.171731 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.821285 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 2872853 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 3821739 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1206360 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 38891 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 177967 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 63499 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 3800 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 6911640 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 11536 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 177967 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 2981399 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 177384 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3223332 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1138018 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 419709 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 6319378 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 203 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 45248 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 5428 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 135690 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 4267087 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 7667393 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 7641550 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 21648 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3453234 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 813853 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 270338 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 17002 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1051064 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1262745 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 687524 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 118324 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 74010 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 5585108 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 271421 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 5341703 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20645 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1049804 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 612834 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 207573 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 8117811 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.658023 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.347544 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 5813637 71.62% 71.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1034901 12.75% 84.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 447279 5.51% 89.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 322285 3.97% 93.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 244246 3.01% 96.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 126246 1.56% 98.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 72876 0.90% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 50809 0.63% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 5532 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 8117811 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4295 3.26% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 76591 58.14% 61.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 50850 38.60% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.07% 0.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3268625 61.19% 61.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 9680 0.18% 61.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8881 0.17% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1232456 23.07% 84.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 646098 12.10% 96.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 170686 3.20% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued -system.cpu1.iq.rate 0.609525 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 5341703 # Type of FU issued +system.cpu1.iq.rate 0.618450 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 131736 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 18885884 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 6873502 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 5132762 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 67714 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 33978 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 32480 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 5434957 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 34964 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 63957 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 266370 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 353 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1238 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 98626 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 72939 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 177967 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 80772 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 78093 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 6077668 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 83087 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1262745 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 687524 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 253926 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4593 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 73335 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1238 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 19913 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 60148 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 80061 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 5287979 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1198929 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 53724 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 483081 # number of nop insts executed -system.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1345265 # Number of branches executed -system.cpu1.iew.exec_stores 1196645 # Number of stores executed -system.cpu1.iew.exec_rate 0.603549 # Inst execution rate -system.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4203498 # num instructions producing a value -system.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value +system.cpu1.iew.exec_nop 221139 # number of nop insts executed +system.cpu1.iew.exec_refs 1832774 # number of memory reference insts executed +system.cpu1.iew.exec_branches 762873 # Number of branches executed +system.cpu1.iew.exec_stores 633845 # Number of stores executed +system.cpu1.iew.exec_rate 0.612230 # Inst execution rate +system.cpu1.iew.wb_sent 5189273 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 5165242 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2532511 # num instructions producing a value +system.cpu1.iew.wb_consumers 3587094 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.598020 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.706006 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1065222 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 63848 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 75650 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 7939844 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.623951 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.560784 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6043541 76.12% 76.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 925286 11.65% 87.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 320402 4.04% 91.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 190890 2.40% 94.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 129096 1.63% 95.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 57238 0.72% 96.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 65164 0.82% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 44060 0.55% 97.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 164167 2.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8834118 # Number of instructions committed -system.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 7939844 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 4954074 # Number of instructions committed +system.cpu1.commit.committedOps 4954074 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2811640 # Number of memory references committed -system.cpu1.commit.loads 1676136 # Number of loads committed -system.cpu1.commit.membars 41495 # Number of memory barriers committed -system.cpu1.commit.branches 1262292 # Number of branches committed -system.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8189363 # Number of committed integer instructions. -system.cpu1.commit.function_calls 139415 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction +system.cpu1.commit.refs 1585273 # Number of memory references committed +system.cpu1.commit.loads 996375 # Number of loads committed +system.cpu1.commit.membars 16576 # Number of memory barriers committed +system.cpu1.commit.branches 700739 # Number of branches committed +system.cpu1.commit.fp_insts 31280 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 4632533 # Number of committed integer instructions. +system.cpu1.commit.function_calls 77324 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 191990 3.88% 3.88% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 2969211 59.93% 63.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 9565 0.19% 64.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8881 0.18% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.04% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1012951 20.45% 84.66% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 589031 11.89% 96.55% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 170686 3.45% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction -system.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 4954074 # Class of committed instruction +system.cpu1.commit.bw_lim_events 164167 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 23736453 # The number of ROB reads -system.cpu1.rob.rob_writes 20710450 # The number of ROB writes -system.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8410372 # Number of Instructions Simulated -system.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11653751 # number of integer regfile reads -system.cpu1.int_regfile_writes 6367365 # number of integer regfile writes -system.cpu1.fp_regfile_reads 51509 # number of floating regfile reads -system.cpu1.fp_regfile_writes 51143 # number of floating regfile writes -system.cpu1.misc_regfile_reads 926936 # number of misc regfile reads -system.cpu1.misc_regfile_writes 206554 # number of misc regfile writes -system.cpu1.icache.tags.replacements 210820 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 13715407 # The number of ROB reads +system.cpu1.rob.rob_writes 12215098 # The number of ROB writes +system.cpu1.timesIdled 57372 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 519429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3803095502 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 4765602 # Number of Instructions Simulated +system.cpu1.committedOps 4765602 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.812413 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.812413 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551751 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551751 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 6848640 # number of integer regfile reads +system.cpu1.int_regfile_writes 3746417 # number of integer regfile writes +system.cpu1.fp_regfile_reads 21244 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19994 # number of floating regfile writes +system.cpu1.misc_regfile_reads 693471 # number of misc regfile reads +system.cpu1.misc_regfile_writes 115172 # number of misc regfile writes +system.cpu1.icache.tags.replacements 94727 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.369242 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 794363 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 95239 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.340732 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880860642000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.369242 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885487 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.885487 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits -system.cpu1.icache.overall_hits::total 1201520 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses -system.cpu1.icache.overall_misses::total 219211 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # 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Number of tag accesses +system.cpu1.icache.tags.data_accesses 989361 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 794363 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 794363 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 794363 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 794363 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 794363 # number of overall hits +system.cpu1.icache.overall_hits::total 794363 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 99697 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 99697 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 99697 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 99697 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 99697 # number of overall misses +system.cpu1.icache.overall_misses::total 99697 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1381976879 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1381976879 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1381976879 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1381976879 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1381976879 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1381976879 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 894060 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 894060 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 894060 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 894060 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 894060 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13861.769953 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.217391 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 4396 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 4396 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1139734069 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1139734069 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1139734069 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1139734069 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106594 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.106594 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.106594 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 102235 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1521331 # 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Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 6609919 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 6609919 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 960992 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 960992 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 477143 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 477143 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 12504 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 12504 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 10799 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 10799 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1438135 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1438135 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1438135 # number of overall hits +system.cpu1.dcache.overall_hits::total 1438135 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 81302 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 81302 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 95545 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 95545 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1156 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1156 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 573 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 573 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 176847 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 176847 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 176847 # number of overall misses +system.cpu1.dcache.overall_misses::total 176847 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1110177095 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1110177095 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5046033431 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5046033431 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13905498 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 13905498 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4132075 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4132075 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6156210526 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6156210526 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6156210526 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6156210526 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1042294 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1042294 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 572688 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 572688 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 13660 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 13660 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11372 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 11372 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1614982 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1614982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1614982 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1614982 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078003 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.078003 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166836 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.166836 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084627 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084627 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050387 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050387 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.109504 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.109504 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.109504 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.109504 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7211.300175 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7211.300175 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 236601 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6165 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 38.378102 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks -system.cpu1.dcache.writebacks::total 67781 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 24956 # number of writebacks +system.cpu1.dcache.writebacks::total 24956 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 46173 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 46173 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 80581 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 80581 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 235 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 235 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 126754 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 126754 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 126754 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 126754 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35129 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 35129 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 14964 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 14964 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 921 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 921 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 573 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 573 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 50093 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 50093 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 50093 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 50093 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 398615352 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 398615352 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 730663501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 730663501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8358752 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8358752 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2984925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2984925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1129278853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1129278853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1129278853 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1129278853 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22397000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22397000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 533147000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 533147000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555544000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555544000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033704 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033704 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026129 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067423 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067423 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050387 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050387 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031018 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031018 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9075.735071 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9075.735071 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5209.293194 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5209.293194 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2085,170 +2087,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6410 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202830 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72673 40.72% 40.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.08% 41.87% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 103726 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178462 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71304 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.38% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.33% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.72% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71298 49.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144665 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863558813000 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63845500 0.00% 97.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 565237000 0.03% 97.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 3385500 0.00% 97.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42015112000 2.20% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1906206393000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981162 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.687369 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810621 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169959 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches +system.cpu0.kern.callpal::wripir 95 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3930 2.10% 2.15% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpipl 171605 91.48% 93.66% # number of callpals executed +system.cpu0.kern.callpal::rdps 6547 3.49% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::rti 4793 2.56% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 187581 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7378 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1286 -system.cpu0.kern.mode_good::user 1287 +system.cpu0.kern.mode_good::kernel 1369 +system.cpu0.kern.mode_good::user 1370 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.185552 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313100 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1904135221500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2071163500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3530 # number of times the context was actually changed +system.cpu0.kern.swap_context 3931 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2254 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 34590 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8916 31.91% 31.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 6.89% 38.80% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 95 0.34% 39.14% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17006 60.86% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 27942 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8908 45.12% 45.12% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 9.75% 54.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 95 0.48% 55.36% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8813 44.64% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 19741 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1876395415500 98.45% 98.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531818000 0.03% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 44293500 0.00% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28895956000 1.52% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1905867483000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999103 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.518229 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.706499 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed -system.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 298 1.04% 1.07% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.08% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.11% # number of callpals executed +system.cpu1.kern.callpal::swpipl 23527 82.20% 83.30% # number of callpals executed +system.cpu1.kern.callpal::rdps 2214 7.74% 91.04% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.04% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 91.05% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.06% # number of callpals executed +system.cpu1.kern.callpal::rti 2394 8.36% 99.43% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.42% 99.85% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48076 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches -system.cpu1.kern.mode_switch::user 460 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 662 -system.cpu1.kern.mode_good::user 460 -system.cpu1.kern.mode_good::idle 202 -system.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 28623 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 659 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2036 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 386 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 19 +system.cpu1.kern.mode_switch_good::kernel 0.585736 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1068 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.009332 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.252123 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1444110500 0.08% 0.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 692193000 0.04% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1903401131500 99.89% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 299 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |