diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3162 |
1 files changed, 1581 insertions, 1581 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 30313ea26..40315f031 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901720 # Number of seconds simulated -sim_ticks 1901719660500 # Number of ticks simulated -final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.898811 # Number of seconds simulated +sim_ticks 1898811181000 # Number of ticks simulated +final_tick 1898811181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97307 # Simulator instruction rate (inst/s) -host_op_rate 97307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3261646555 # Simulator tick rate (ticks/s) -host_mem_usage 383552 # Number of bytes of host memory used -host_seconds 583.06 # Real time elapsed on the host -sim_insts 56735321 # Number of instructions simulated -sim_ops 56735321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24596992 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 118720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 533440 # Number of bytes read from this memory -system.physmem.bytes_read::total 28758656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 118720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7726912 # Number of bytes written to this memory -system.physmem.bytes_written::total 7726912 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384328 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8335 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449354 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120733 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120733 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 450960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12934079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1394477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15122448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 450960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513388 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4063118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4063118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4063118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 450960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12934079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1394477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 280504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19185566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449354 # Total number of read requests seen -system.physmem.writeReqs 120733 # Total number of write requests seen -system.physmem.cpureqs 587676 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28758656 # Total number of bytes read from memory -system.physmem.bytesWritten 7726912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28758656 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7726912 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4987 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28541 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28148 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27749 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7547 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7751 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7593 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7293 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7616 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7539 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7418 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7246 # Track writes on a per bank basis +host_inst_rate 163774 # Simulator instruction rate (inst/s) +host_op_rate 163774 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5540525376 # Simulator tick rate (ticks/s) +host_mem_usage 339592 # Number of bytes of host memory used +host_seconds 342.71 # Real time elapsed on the host +sim_insts 56127436 # Number of instructions simulated +sim_ops 56127436 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 739584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24165760 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 241984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1058688 # Number of bytes read from this memory +system.physmem.bytes_read::total 28856384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 739584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 241984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7824192 # Number of bytes written to this memory +system.physmem.bytes_written::total 7824192 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377590 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16542 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450881 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 389498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12726784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 127440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 557553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15197079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 127440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4120574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4120574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4120574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12726784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 127440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 557553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19317653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450881 # Total number of read requests seen +system.physmem.writeReqs 122253 # Total number of write requests seen +system.physmem.cpureqs 582476 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28856384 # Total number of bytes read from memory +system.physmem.bytesWritten 7824192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28856384 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7824192 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 66 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3389 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28253 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28343 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28155 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28056 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28022 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27898 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8087 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7991 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7846 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7721 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7765 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7705 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7559 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7394 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7457 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7400 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7239 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7345 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 393 # Number of times wr buffer was full causing retry -system.physmem.totGap 1901668058000 # Total gap between requests +system.physmem.numWrRetry 1873 # Number of times wr buffer was full causing retry +system.physmem.totGap 1898811160000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449354 # Categorize read packet sizes +system.physmem.readPktSize::6 450881 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121126 # categorize write packet sizes +system.physmem.writePktSize::6 124126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,33 +116,33 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4987 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3389 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 322670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 320280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # 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Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.totQLat 8261632913 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 16092226663 # Sum of mem lat for all requests +system.physmem.totBusLat 2254075000 # Total cycles spent in databus access +system.physmem.totBankLat 5576518750 # Total cycles spent in bank access +system.physmem.avgQLat 18325.99 # Average queueing delay per request +system.physmem.avgBankLat 12369.86 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 35695.85 # Average memory access latency +system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # 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number of cycles access was blocked +system.iocache.blocked::no_mshrs 27128 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.332211 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.505013 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41522 # number of writebacks +system.iocache.writebacks::total 41522 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12298000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12298000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7352694535 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7352694535 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7364992535 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7364992535 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7364992535 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7364992535 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12115250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12115250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8496857845 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8496857845 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8508973095 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8508973095 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8508973095 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8508973095 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -591,14 +591,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68703.910615 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68703.910615 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176951.639753 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176951.639753 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68836.647727 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68836.647727 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204487.337433 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204487.337433 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,35 +612,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12372868 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10433314 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 330387 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8151024 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5278103 # Number of BTB hits +system.cpu0.branchPred.lookups 10581841 # Number of BP lookups +system.cpu0.branchPred.condPredicted 8959361 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 281985 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7046138 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4567974 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.753864 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 784011 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32544 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 64.829471 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 656046 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29257 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8796431 # DTB read hits -system.cpu0.dtb.read_misses 31428 # DTB read misses -system.cpu0.dtb.read_acv 541 # DTB read access violations -system.cpu0.dtb.read_accesses 625134 # DTB read accesses -system.cpu0.dtb.write_hits 5759616 # DTB write hits -system.cpu0.dtb.write_misses 8293 # DTB write misses -system.cpu0.dtb.write_acv 340 # DTB write access violations -system.cpu0.dtb.write_accesses 208056 # DTB write accesses -system.cpu0.dtb.data_hits 14556047 # DTB hits -system.cpu0.dtb.data_misses 39721 # DTB misses -system.cpu0.dtb.data_acv 881 # DTB access violations -system.cpu0.dtb.data_accesses 833190 # DTB accesses -system.cpu0.itb.fetch_hits 984271 # ITB hits -system.cpu0.itb.fetch_misses 30098 # ITB misses -system.cpu0.itb.fetch_acv 957 # ITB acv -system.cpu0.itb.fetch_accesses 1014369 # ITB accesses +system.cpu0.dtb.read_hits 7560815 # DTB read hits +system.cpu0.dtb.read_misses 30461 # DTB read misses +system.cpu0.dtb.read_acv 538 # DTB read access violations +system.cpu0.dtb.read_accesses 623625 # DTB read accesses +system.cpu0.dtb.write_hits 5040625 # DTB write hits +system.cpu0.dtb.write_misses 7520 # DTB write misses +system.cpu0.dtb.write_acv 334 # DTB write access violations +system.cpu0.dtb.write_accesses 206551 # DTB write accesses +system.cpu0.dtb.data_hits 12601440 # DTB hits +system.cpu0.dtb.data_misses 37981 # DTB misses +system.cpu0.dtb.data_acv 872 # DTB access violations +system.cpu0.dtb.data_accesses 830176 # DTB accesses +system.cpu0.itb.fetch_hits 911527 # ITB hits +system.cpu0.itb.fetch_misses 30644 # ITB misses +system.cpu0.itb.fetch_acv 921 # ITB acv +system.cpu0.itb.fetch_accesses 942171 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -653,269 +653,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 101814962 # number of cpu cycles simulated +system.cpu0.numCycles 89753559 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6062114 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11958171 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1721751 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36639586 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31996 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 197160 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 291451 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 250 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7650026 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223701 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 75155119 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.846620 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.185016 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21107693 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 54367118 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 10581841 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5224020 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10262063 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1458036 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 30903552 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 30207 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 199263 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 186050 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6657299 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 195043 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 63623646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.854511 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.189260 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63196948 84.09% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 760434 1.01% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1555219 2.07% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 695943 0.93% 88.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2597980 3.46% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 515321 0.69% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 570202 0.76% 93.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 825200 1.10% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4437872 5.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 53361583 83.87% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 672459 1.06% 84.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1316592 2.07% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 583007 0.92% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2295308 3.61% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 445844 0.70% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 472664 0.74% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 743494 1.17% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3732695 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 75155119 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121523 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.624936 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26159678 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36134055 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10861438 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 929510 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1070437 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 506952 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35177 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62384726 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105081 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1070437 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27188236 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14621537 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18000496 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10158555 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4115856 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58951339 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6767 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 643786 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1455498 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39478397 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71801839 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71417626 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 384213 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34623741 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4854648 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1439423 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 209577 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11309679 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9204846 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6035425 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1140474 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 743155 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52262338 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1790513 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51072320 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91453 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5903524 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3097982 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1211963 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 75155119 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.679559 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328921 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 63623646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.117899 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.605738 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 22232367 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 30357900 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9303163 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 825009 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 905206 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 419214 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29823 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53368764 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 92723 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 905206 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 23093913 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11627753 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15736016 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8768275 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3492481 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50503220 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 393829 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1341574 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 33876980 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 61564678 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 61250531 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 314147 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 29813717 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4063255 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1268860 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 187899 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9409132 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7922191 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5257693 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 964170 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 651506 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 44858999 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1558626 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 43884207 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 67322 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 4967350 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2566909 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1055206 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 63623646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.689747 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329677 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52460165 69.80% 69.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10326519 13.74% 83.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4642920 6.18% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3073584 4.09% 93.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2437230 3.24% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1208862 1.61% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 646282 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 308169 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51388 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 43919799 69.03% 69.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9075335 14.26% 83.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4098408 6.44% 89.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2614119 4.11% 93.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2006211 3.15% 97.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1055812 1.66% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 551217 0.87% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 263467 0.41% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 39278 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 75155119 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 63623646 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82854 12.32% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 311669 46.35% 58.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 277938 41.33% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62740 10.88% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 271097 47.03% 57.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 242616 42.09% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35204584 68.93% 68.94% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56105 0.11% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9153958 17.92% 87.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5827340 11.41% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 808994 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30137882 68.68% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 45897 0.10% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14285 0.03% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7870096 17.93% 86.76% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5096964 11.61% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 713427 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51072320 # Type of FU issued -system.cpu0.iq.rate 0.501619 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 672462 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 177512873 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59702358 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50032811 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 550800 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 266343 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260046 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51452584 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288424 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 541788 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 43884207 # Type of FU issued +system.cpu0.iq.rate 0.488941 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 576453 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013136 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 151584762 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 51176195 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43017955 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 451072 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 219118 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 212749 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 44220901 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 235982 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 487348 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1120800 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2789 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12579 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 457772 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 958085 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2941 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10552 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 366818 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 147130 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13186 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 117811 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1070437 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10393328 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 793846 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57261563 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 642303 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9204846 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6035425 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1577054 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 582295 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5281 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12579 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164111 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 347239 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 511350 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50686887 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8851053 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 385432 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 905206 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8069118 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 677733 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49115212 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 536411 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7922191 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5257693 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1375945 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 564143 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4652 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10552 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 138850 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 301409 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 440259 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 43556869 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7611218 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 327337 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3208712 # number of nop insts executed -system.cpu0.iew.exec_refs 14632506 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8068479 # Number of branches executed -system.cpu0.iew.exec_stores 5781453 # Number of stores executed -system.cpu0.iew.exec_rate 0.497833 # Inst execution rate -system.cpu0.iew.wb_sent 50383937 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50292857 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25094352 # num instructions producing a value -system.cpu0.iew.wb_consumers 33818001 # num instructions consuming a value +system.cpu0.iew.exec_nop 2697587 # number of nop insts executed +system.cpu0.iew.exec_refs 12670581 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6879787 # Number of branches executed +system.cpu0.iew.exec_stores 5059363 # Number of stores executed +system.cpu0.iew.exec_rate 0.485294 # Inst execution rate +system.cpu0.iew.wb_sent 43311636 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43230704 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 21537449 # num instructions producing a value +system.cpu0.iew.wb_consumers 28771492 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.493963 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742041 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.481660 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.748569 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6371688 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 578550 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 477828 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74084682 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685601 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.604018 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5358562 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 503420 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 412035 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 62718440 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.696169 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.614251 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55026515 74.28% 74.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7939418 10.72% 84.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4342581 5.86% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2354466 3.18% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1312338 1.77% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 550007 0.74% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466229 0.63% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 437204 0.59% 97.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1655924 2.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 46279929 73.79% 73.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6945490 11.07% 84.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3654930 5.83% 90.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2050520 3.27% 93.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1130391 1.80% 95.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 454158 0.72% 96.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 393863 0.63% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 373108 0.59% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1436051 2.29% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74084682 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50792559 # Number of instructions committed -system.cpu0.commit.committedOps 50792559 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 62718440 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 43662606 # Number of instructions committed +system.cpu0.commit.committedOps 43662606 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13661699 # Number of memory references committed -system.cpu0.commit.loads 8084046 # Number of loads committed -system.cpu0.commit.membars 197074 # Number of memory barriers committed -system.cpu0.commit.branches 7671683 # Number of branches committed -system.cpu0.commit.fp_insts 257823 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47034170 # Number of committed integer instructions. -system.cpu0.commit.function_calls 648346 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1655924 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11854981 # Number of memory references committed +system.cpu0.commit.loads 6964106 # Number of loads committed +system.cpu0.commit.membars 168172 # Number of memory barriers committed +system.cpu0.commit.branches 6551324 # Number of branches committed +system.cpu0.commit.fp_insts 210613 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 40489033 # Number of committed integer instructions. +system.cpu0.commit.function_calls 540020 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1436051 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129398549 # The number of ROB reads -system.cpu0.rob.rob_writes 115399767 # The number of ROB writes -system.cpu0.timesIdled 1054205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26659843 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3701617819 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47867129 # Number of Instructions Simulated -system.cpu0.committedOps 47867129 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47867129 # Number of Instructions Simulated -system.cpu0.cpi 2.127033 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.127033 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.470138 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.470138 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66695316 # number of integer regfile reads -system.cpu0.int_regfile_writes 36408183 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127649 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129302 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1695809 # number of misc regfile reads -system.cpu0.misc_regfile_writes 808592 # number of misc regfile writes +system.cpu0.rob.rob_reads 110111593 # The number of ROB reads +system.cpu0.rob.rob_writes 98948174 # The number of ROB writes +system.cpu0.timesIdled 879648 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26129913 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3707863967 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41199881 # Number of Instructions Simulated +system.cpu0.committedOps 41199881 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 41199881 # Number of Instructions Simulated +system.cpu0.cpi 2.178491 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.178491 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.459033 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.459033 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 57370310 # number of integer regfile reads +system.cpu0.int_regfile_writes 31317782 # number of integer regfile writes +system.cpu0.fp_regfile_reads 104569 # number of floating regfile reads +system.cpu0.fp_regfile_writes 105332 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1463769 # number of misc regfile reads +system.cpu0.misc_regfile_writes 718581 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -947,245 +947,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 867960 # number of replacements -system.cpu0.icache.tagsinuse 510.328414 # Cycle average of tags in use -system.cpu0.icache.total_refs 6737923 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 868472 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.758365 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20312098000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.328414 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6737923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6737923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6737923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6737923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6737923 # number of overall hits -system.cpu0.icache.overall_hits::total 6737923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 912101 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 912101 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 912101 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 912101 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 912101 # number of overall misses -system.cpu0.icache.overall_misses::total 912101 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12723011493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12723011493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12723011493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12723011493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12723011493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12723011493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7650024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7650024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7650024 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7650024 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7650024 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7650024 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119229 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119229 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119229 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119229 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119229 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119229 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13949.125692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13949.125692 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13949.125692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13949.125692 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3314 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.replacements 728874 # number of replacements +system.cpu0.icache.tagsinuse 510.265304 # Cycle average of tags in use +system.cpu0.icache.total_refs 5890439 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 729383 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.075920 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20962478000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.265304 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996612 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996612 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5890439 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5890439 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5890439 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5890439 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5890439 # number of overall hits +system.cpu0.icache.overall_hits::total 5890439 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 766860 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 766860 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 766860 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 766860 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 766860 # number of overall misses +system.cpu0.icache.overall_misses::total 766860 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10795349496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10795349496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10795349496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10795349496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10795349496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10795349496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6657299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6657299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6657299 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6657299 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6657299 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6657299 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.115191 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.115191 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.115191 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.115191 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.115191 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.115191 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14077.340709 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14077.340709 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14077.340709 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14077.340709 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2177 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 468 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 128 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.013889 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 438 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.007812 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 468 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43445 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43445 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43445 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43445 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43445 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43445 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868656 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 868656 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 868656 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 868656 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 868656 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 868656 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10487782996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10487782996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10487782996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10487782996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10487782996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10487782996 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113549 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113549 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12073.574575 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37318 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 37318 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37318 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 37318 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37318 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 37318 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 729542 # 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number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109585 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.109585 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.109585 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12201.878709 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1274576 # number of replacements -system.cpu0.dcache.tagsinuse 505.658053 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10359284 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1275088 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.124368 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.658053 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987613 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987613 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6368256 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6368256 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3633863 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3633863 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160621 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160621 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185111 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 185111 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10002119 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10002119 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10002119 # number of overall hits -system.cpu0.dcache.overall_hits::total 10002119 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1588144 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1588144 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1741180 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1741180 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20406 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20406 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2921 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2921 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3329324 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3329324 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3329324 # number of overall misses -system.cpu0.dcache.overall_misses::total 3329324 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34092049500 # 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number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13331443 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13331443 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199606 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199606 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323938 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323938 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112724 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112724 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015535 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015535 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249735 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249735 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249735 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249735 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21466.598432 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21466.598432 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39946.744775 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39946.744775 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14136.577477 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14136.577477 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7323.005820 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7323.005820 # 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Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 479.291529 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.936116 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.936116 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5529733 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5529733 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3096724 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3096724 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 145068 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 145068 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 167974 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 167974 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8626457 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8626457 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8626457 # number of overall hits +system.cpu0.dcache.overall_hits::total 8626457 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1297164 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1297164 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1613226 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1613226 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 15668 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 15668 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2910390 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2910390 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2910390 # number of overall misses +system.cpu0.dcache.overall_misses::total 2910390 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 30009249500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 30009249500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61556935480 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 61556935480 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 231982500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 231982500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4680500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4680500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 91566184980 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 91566184980 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 91566184980 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 91566184980 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826897 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6826897 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4709950 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4709950 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160736 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160736 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168740 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 168740 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11536847 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11536847 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11536847 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11536847 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.190008 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.190008 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342514 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.342514 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.097477 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097477 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004540 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004540 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252269 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.252269 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252269 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.252269 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23134.506893 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23134.506893 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38157.663886 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38157.663886 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14806.133521 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14806.133521 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6110.313316 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6110.313316 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31461.826415 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31461.826415 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2024468 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 671 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 45038 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 49.313033 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 251.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.950220 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 95.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 749955 # number of writebacks -system.cpu0.dcache.writebacks::total 749955 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 587926 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 587926 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1468148 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1468148 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4517 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4517 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2056074 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2056074 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2056074 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2056074 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1000218 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1000218 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273032 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 273032 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15889 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15889 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2921 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2921 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1273250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1273250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1273250 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1273250 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21325955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21325955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10169026713 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10169026713 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181062500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181062500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15548500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15548500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31494981713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31494981713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31494981713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31494981713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1455479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1455479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128324998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128324998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3583803998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3583803998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125712 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125712 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050796 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050796 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087771 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087771 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095507 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095507 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21321.306955 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21321.306955 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37244.816406 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37244.816406 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11395.462269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.462269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5323.005820 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5323.005820 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 554167 # number of writebacks +system.cpu0.dcache.writebacks::total 554167 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 497870 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 497870 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1365575 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1365575 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3772 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3772 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1863445 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1863445 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1863445 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1863445 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 799294 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 799294 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 247651 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 247651 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 11896 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11896 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1046945 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1046945 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1046945 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1046945 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19199342000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19199342000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8924614838 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8924614838 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148344000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148344000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3148500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3148500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 28123956838 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 28123956838 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 28123956838 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 28123956838 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 991461500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 991461500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668991999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668991999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2660453499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2660453499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117080 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117080 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074010 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074010 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004540 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004540 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.090748 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.090748 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24020.375481 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24020.375481 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36037.063602 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36037.063602 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12470.073974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.073974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4110.313316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4110.313316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,35 +1193,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2617746 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2161338 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 77903 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1516620 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 873996 # Number of BTB hits +system.cpu1.branchPred.lookups 4327546 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3555815 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 137782 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2736457 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1529937 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.627883 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 182212 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8242 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 55.909411 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 311519 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 14646 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1943067 # DTB read hits -system.cpu1.dtb.read_misses 10795 # DTB read misses -system.cpu1.dtb.read_acv 23 # DTB read access violations -system.cpu1.dtb.read_accesses 324453 # DTB read accesses -system.cpu1.dtb.write_hits 1254400 # DTB write hits -system.cpu1.dtb.write_misses 2201 # DTB write misses -system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_accesses 132933 # DTB write accesses -system.cpu1.dtb.data_hits 3197467 # DTB hits -system.cpu1.dtb.data_misses 12996 # DTB misses -system.cpu1.dtb.data_acv 86 # DTB access violations -system.cpu1.dtb.data_accesses 457386 # DTB accesses -system.cpu1.itb.fetch_hits 434450 # ITB hits -system.cpu1.itb.fetch_misses 7705 # ITB misses -system.cpu1.itb.fetch_acv 232 # ITB acv -system.cpu1.itb.fetch_accesses 442155 # ITB accesses +system.cpu1.dtb.read_hits 3068448 # DTB read hits +system.cpu1.dtb.read_misses 13337 # DTB read misses +system.cpu1.dtb.read_acv 21 # DTB read access violations +system.cpu1.dtb.read_accesses 325420 # DTB read accesses +system.cpu1.dtb.write_hits 1915630 # DTB write hits +system.cpu1.dtb.write_misses 2521 # DTB write misses +system.cpu1.dtb.write_acv 68 # DTB write access violations +system.cpu1.dtb.write_accesses 132592 # DTB write accesses +system.cpu1.dtb.data_hits 4984078 # DTB hits +system.cpu1.dtb.data_misses 15858 # DTB misses +system.cpu1.dtb.data_acv 89 # DTB access violations +system.cpu1.dtb.data_accesses 458012 # DTB accesses +system.cpu1.itb.fetch_hits 498592 # ITB hits +system.cpu1.itb.fetch_misses 6957 # ITB misses +system.cpu1.itb.fetch_acv 210 # ITB acv +system.cpu1.itb.fetch_accesses 505549 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1234,508 +1234,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16039611 # number of cpu cycles simulated +system.cpu1.numCycles 28341850 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1056208 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2219979 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 406574 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6282819 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 27064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 67109 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 53469 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1501296 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 52568 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14943285 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.828159 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.202626 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9666058 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 20746660 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4327546 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1841456 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3769607 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 667538 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 11516910 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24752 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65971 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 157862 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2430728 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 90320 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 25638274 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.809207 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.171586 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12723306 85.14% 85.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 143447 0.96% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 238457 1.60% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 178791 1.20% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 308600 2.07% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 118341 0.79% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 133550 0.89% 92.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 199066 1.33% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 899727 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 21868667 85.30% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 217825 0.85% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 471767 1.84% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 290566 1.13% 89.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 572691 2.23% 91.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 192619 0.75% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 225020 0.88% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 283328 1.11% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1515791 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14943285 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.163205 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.771553 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5967965 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6534138 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2076282 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 111928 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 252971 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 114663 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7593 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12129871 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22496 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 252971 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6175430 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 499012 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5393527 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1978606 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 643737 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11250530 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 66 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 56207 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 157985 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7407591 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13449617 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13309138 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 140479 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6324692 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1082899 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 450684 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 43314 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1976964 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2055976 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1329039 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 193469 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 109268 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9879442 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 495628 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9611427 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29957 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1443490 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 718060 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356268 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14943285 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.643194 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.319140 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 25638274 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.152691 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.732015 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 9733408 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 11767392 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3496252 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 218180 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 423041 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 197160 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 14107 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 20339380 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 42509 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 423041 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 10090973 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3436285 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 7189136 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3265501 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1233336 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 19035683 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 302354 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 266371 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 12573410 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 22727510 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 22552449 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 175061 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 10671795 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1901615 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 598380 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 62207 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3655619 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3246585 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2021315 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 341799 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 191681 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 16730301 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 718132 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 16236732 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 38678 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2401085 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1178363 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 514161 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 25638274 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.633301 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.313801 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10722627 71.76% 71.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1934278 12.94% 84.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 829364 5.55% 90.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 551304 3.69% 93.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 470726 3.15% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 216087 1.45% 98.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 139402 0.93% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 71218 0.48% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8279 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 18618463 72.62% 72.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 3106773 12.12% 84.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1368758 5.34% 90.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 986929 3.85% 93.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 856057 3.34% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 349630 1.36% 98.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 219211 0.86% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 115612 0.45% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 16841 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14943285 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 25638274 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3634 1.84% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 107033 54.32% 56.16% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 86373 43.84% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22162 7.89% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 144030 51.29% 59.18% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 114619 40.82% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5997328 62.40% 62.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16465 0.17% 62.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10793 0.11% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2032935 21.15% 83.89% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1277891 13.30% 97.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 270726 2.82% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3527 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 10692350 65.85% 65.87% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 24766 0.15% 66.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11484 0.07% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3204356 19.74% 85.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1945149 11.98% 97.82% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 353337 2.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9611427 # Type of FU issued -system.cpu1.iq.rate 0.599231 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 197040 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020501 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 34189984 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11721176 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9344184 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 203152 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 99152 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 96176 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9699010 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 105931 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 93506 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 16236732 # Type of FU issued +system.cpu1.iq.rate 0.572889 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 280811 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017295 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 58178646 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 19730507 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 15830008 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 252581 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 122599 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 119620 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 16382145 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 131871 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 151965 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 286352 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1028 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1836 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 129863 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 456957 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 998 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3692 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 187617 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 382 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 9210 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5626 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 16438 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 252971 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 330484 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 40597 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10884350 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 145943 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2055976 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1329039 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 449000 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33362 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2246 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1836 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 35752 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 100142 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 135894 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9521603 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1961135 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 89824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 423041 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2638422 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 162147 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 18437863 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 211636 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3246585 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2021315 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 643129 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 60084 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2152 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3692 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 66784 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 149088 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 215872 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 16080551 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3090638 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 156181 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 509280 # number of nop insts executed -system.cpu1.iew.exec_refs 3223669 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1421889 # Number of branches executed -system.cpu1.iew.exec_stores 1262534 # Number of stores executed -system.cpu1.iew.exec_rate 0.593631 # Inst execution rate -system.cpu1.iew.wb_sent 9469121 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9440360 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4419848 # num instructions producing a value -system.cpu1.iew.wb_consumers 6207573 # num instructions consuming a value +system.cpu1.iew.exec_nop 989430 # number of nop insts executed +system.cpu1.iew.exec_refs 5015230 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2535241 # Number of branches executed +system.cpu1.iew.exec_stores 1924592 # Number of stores executed +system.cpu1.iew.exec_rate 0.567378 # Inst execution rate +system.cpu1.iew.wb_sent 15988482 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 15949628 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7724743 # num instructions producing a value +system.cpu1.iew.wb_consumers 10881499 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.588565 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712009 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.562759 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709897 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1489613 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 139360 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 127942 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14690314 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.634143 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577922 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2575173 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 203971 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 201824 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 25215233 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.626683 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.561616 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11205689 76.28% 76.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1626477 11.07% 87.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 606444 4.13% 91.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 368240 2.51% 93.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 264133 1.80% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 104886 0.71% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 108759 0.74% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 107326 0.73% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 298360 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 19361338 76.78% 76.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2499341 9.91% 86.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1261575 5.00% 91.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 645749 2.56% 94.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 410067 1.63% 95.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 193046 0.77% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 184525 0.73% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 147171 0.58% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 512421 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14690314 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9315763 # Number of instructions committed -system.cpu1.commit.committedOps 9315763 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 25215233 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 15801951 # Number of instructions committed +system.cpu1.commit.committedOps 15801951 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2968800 # Number of memory references committed -system.cpu1.commit.loads 1769624 # Number of loads committed -system.cpu1.commit.membars 44277 # Number of memory barriers committed -system.cpu1.commit.branches 1334383 # Number of branches committed -system.cpu1.commit.fp_insts 94889 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8635888 # Number of committed integer instructions. -system.cpu1.commit.function_calls 148923 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 298360 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4623326 # Number of memory references committed +system.cpu1.commit.loads 2789628 # Number of loads committed +system.cpu1.commit.membars 68640 # Number of memory barriers committed +system.cpu1.commit.branches 2366242 # Number of branches committed +system.cpu1.commit.fp_insts 118314 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 14589318 # Number of committed integer instructions. +system.cpu1.commit.function_calls 250839 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 512421 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25106022 # The number of ROB reads -system.cpu1.rob.rob_writes 21862282 # The number of ROB writes -system.cpu1.timesIdled 131003 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1096326 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3786825078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8868192 # Number of Instructions Simulated -system.cpu1.committedOps 8868192 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8868192 # Number of Instructions Simulated -system.cpu1.cpi 1.808668 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.808668 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.552893 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.552893 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12288735 # number of integer regfile reads -system.cpu1.int_regfile_writes 6719305 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52595 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52295 # number of floating regfile writes -system.cpu1.misc_regfile_reads 519807 # number of misc regfile reads -system.cpu1.misc_regfile_writes 218837 # number of misc regfile writes -system.cpu1.icache.replacements 223384 # number of replacements -system.cpu1.icache.tagsinuse 470.911172 # Cycle average of tags in use -system.cpu1.icache.total_refs 1268764 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 223896 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.666756 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1876151234000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.911172 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919748 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919748 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1268764 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1268764 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1268764 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1268764 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1268764 # number of overall hits -system.cpu1.icache.overall_hits::total 1268764 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 232532 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 232532 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 232532 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 232532 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 232532 # number of overall misses -system.cpu1.icache.overall_misses::total 232532 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3191119498 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3191119498 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3191119498 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3191119498 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3191119498 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3191119498 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1501296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1501296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1501296 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1501296 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1501296 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1501296 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154888 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154888 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154888 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.154888 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154888 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.154888 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13723.356347 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13723.356347 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13723.356347 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13723.356347 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 852 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 37.043478 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 42991260 # The number of ROB reads +system.cpu1.rob.rob_writes 37176651 # The number of ROB writes +system.cpu1.timesIdled 292999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2703576 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3768655732 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 14927555 # Number of Instructions Simulated +system.cpu1.committedOps 14927555 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 14927555 # Number of Instructions Simulated +system.cpu1.cpi 1.898626 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.898626 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.526697 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.526697 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20802804 # number of integer regfile reads +system.cpu1.int_regfile_writes 11409368 # number of integer regfile writes +system.cpu1.fp_regfile_reads 63889 # number of floating regfile reads +system.cpu1.fp_regfile_writes 64169 # number of floating regfile writes +system.cpu1.misc_regfile_reads 688257 # number of misc regfile reads +system.cpu1.misc_regfile_writes 294653 # number of misc regfile writes +system.cpu1.icache.replacements 359909 # number of replacements +system.cpu1.icache.tagsinuse 505.656535 # Cycle average of tags in use +system.cpu1.icache.total_refs 2054105 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 360421 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.699182 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 43308699500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.656535 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.987610 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.987610 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 2054105 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2054105 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2054105 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2054105 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2054105 # number of overall hits +system.cpu1.icache.overall_hits::total 2054105 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 376623 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 376623 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 376623 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 376623 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 376623 # number of overall misses +system.cpu1.icache.overall_misses::total 376623 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5258660997 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5258660997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5258660997 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5258660997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5258660997 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5258660997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2430728 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2430728 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2430728 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2430728 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2430728 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2430728 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154942 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.154942 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154942 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.154942 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154942 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.154942 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.665575 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13962.665575 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13962.665575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13962.665575 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2479 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1476 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 54 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 45.907407 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 1476 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223964 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 223964 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 223964 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 223964 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 223964 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 223964 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2651052998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2651052998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2651052998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2651052998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2651052998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2651052998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.149180 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.149180 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.149180 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11836.960395 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16134 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 16134 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 16134 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 16134 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 16134 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 16134 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 360489 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 360489 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 360489 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 360489 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 360489 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 360489 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4342433998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4342433998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4342433998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4342433998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4342433998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4342433998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148305 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.148305 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.148305 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12045.954240 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 107089 # number of replacements -system.cpu1.dcache.tagsinuse 492.773988 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2615920 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 107493 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.335724 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 38980492000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 492.773988 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.962449 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.962449 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1604976 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1604976 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 940707 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 940707 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33481 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 33481 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32051 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 32051 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2545683 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2545683 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2545683 # number of overall hits -system.cpu1.dcache.overall_hits::total 2545683 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 206048 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 206048 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 217271 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 217271 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5237 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5237 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3060 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3060 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 423319 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 423319 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 423319 # number of overall misses -system.cpu1.dcache.overall_misses::total 423319 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3148302000 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1811024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1811024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1157978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1157978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38718 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 38718 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35111 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35111 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2969002 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2969002 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2969002 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2969002 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.113774 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.113774 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187630 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187630 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135260 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135260 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087152 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087152 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.142580 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.142580 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.142580 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.142580 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15279.459155 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15279.459155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40782.120412 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40782.120412 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10443.001719 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10443.001719 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7233.333333 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7233.333333 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.972223 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.972223 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2307913 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2307913 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1365825 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1365825 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47088 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47088 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50932 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50932 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3673738 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3673738 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3673738 # number of overall hits +system.cpu1.dcache.overall_hits::total 3673738 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 542018 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 542018 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 408775 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 408775 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9102 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9102 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 780 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 780 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 950793 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 950793 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 950793 # number of overall misses +system.cpu1.dcache.overall_misses::total 950793 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8456828000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8456828000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13523509258 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13523509258 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132387000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 132387000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5554000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5554000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 21980337258 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 21980337258 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 21980337258 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 21980337258 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2849931 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2849931 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1774600 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1774600 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56190 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 56190 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 51712 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 51712 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4624531 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4624531 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4624531 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4624531 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.190186 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.190186 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.230348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.230348 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.161986 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.161986 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015084 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015084 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.205598 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.205598 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.205598 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.205598 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15602.485526 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15602.485526 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33083.014514 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33083.014514 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14544.825313 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14544.825313 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7120.512821 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7120.512821 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23117.899751 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23117.899751 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 393760 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3910 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7994 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 86.716113 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 49.256943 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 70825 # number of writebacks -system.cpu1.dcache.writebacks::total 70825 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 127864 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 127864 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 178553 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 178553 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 567 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 567 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 306417 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 306417 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 306417 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 306417 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 78184 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 78184 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 38718 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 38718 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4670 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4670 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 116902 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 116902 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 116902 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 116902 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 956868500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 956868500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1322831987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1322831987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38016500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38016500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16018000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16018000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2279700487 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2279700487 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2279700487 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2279700487 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30982500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30982500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 645432500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 645432500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676415000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676415000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043171 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043171 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033436 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033436 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120616 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120616 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087095 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087095 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039374 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039374 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12238.674153 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12238.674153 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34165.814014 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34165.814014 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8140.578158 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.578158 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5238.064094 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5238.064094 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 289966 # number of writebacks +system.cpu1.dcache.writebacks::total 289966 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 235266 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 235266 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 338145 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 338145 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1764 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1764 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 573411 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 573411 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 573411 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 573411 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 306752 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 306752 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 70630 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 70630 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7338 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7338 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 780 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 780 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 377382 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 377382 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 377382 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 377382 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4029157000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4029157000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2036960738 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2036960738 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87414000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87414000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3994000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3994000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6066117738 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6066117738 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6066117738 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6066117738 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491781000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491781000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 942840000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 942840000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1434621000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1434621000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.039801 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.039801 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130593 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130593 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015084 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015084 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.081604 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.081604 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13134.900506 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13134.900506 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28839.880193 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28839.880193 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11912.510221 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11912.510221 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5120.512821 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5120.512821 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1744,32 +1744,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6541 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 182292 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64399 40.43% 40.43% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 137 0.09% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1928 1.21% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 188 0.12% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92618 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 159270 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63397 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 137 0.11% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1928 1.50% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63212 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128862 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866521704000 98.15% 98.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63425000 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 571234500 0.03% 98.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 91794500 0.00% 98.19% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34470644500 1.81% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901718802500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984441 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4837 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 159566 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 54412 39.60% 39.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.10% 39.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.40% 41.09% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.10% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80931 58.90% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 137415 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 53531 49.06% 49.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.76% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 53515 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 109118 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866933879000 98.32% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62852000 0.00% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 558860500 0.03% 98.35% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8730000 0.00% 98.35% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 31246000500 1.65% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1898810322000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983809 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682502 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809079 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.661242 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.794076 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1801,60 +1801,60 @@ system.cpu0.kern.syscall::144 1 0.50% 99.01% # nu system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 291 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3482 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.28% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 152520 91.05% 93.34% # number of callpals executed -system.cpu0.kern.callpal::rdps 6170 3.68% 97.03% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4499 2.69% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167505 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7002 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1256 # number of protection mode switches +system.cpu0.kern.callpal::wripir 107 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2838 1.96% 2.03% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.07% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.07% # number of callpals executed +system.cpu0.kern.callpal::swpipl 131134 90.46% 92.54% # number of callpals executed +system.cpu0.kern.callpal::rdps 6127 4.23% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.77% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rti 4208 2.90% 99.68% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.23% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 144957 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6180 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1255 -system.cpu0.kern.mode_good::user 1256 +system.cpu0.kern.mode_good::kernel 1257 +system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.179235 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.203398 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.304069 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899848666000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1870128500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.338129 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1896878389500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1931924500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3483 # number of times the context was actually changed +system.cpu0.kern.swap_context 2839 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 57520 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17961 36.86% 36.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 3.96% 40.82% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 291 0.60% 41.41% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28549 58.59% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 48729 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17586 47.40% 47.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 5.20% 52.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 291 0.78% 53.38% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17296 46.62% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37101 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876762048000 98.70% 98.70% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532687000 0.03% 98.73% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 132052500 0.01% 98.74% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24006771500 1.26% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1901433559000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979121 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3835 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77998 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27220 39.42% 39.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 2.78% 42.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 107 0.15% 42.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 39804 57.64% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69054 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26724 48.26% 48.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 3.47% 51.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 107 0.19% 51.93% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26617 48.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55371 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1869610475000 98.48% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533425500 0.03% 98.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 50588500 0.00% 98.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28306196500 1.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1898500685500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981778 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.605836 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.761374 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.668702 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.801851 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1878,36 +1878,36 @@ system.cpu1.kern.syscall::132 3 2.42% 99.19% # nu system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1118 2.21% 2.58% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.60% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43429 85.72% 88.33% # number of callpals executed -system.cpu1.kern.callpal::rdps 2596 5.12% 93.45% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.45% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.46% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3081 6.08% 99.55% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1407 1.97% 2.00% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.01% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.02% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64017 89.75% 91.76% # number of callpals executed +system.cpu1.kern.callpal::rdps 2632 3.69% 95.45% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.45% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.46% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 95.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3006 4.21% 99.68% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.26% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 50665 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1406 # number of protection mode switches +system.cpu1.kern.callpal::total 71331 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1876 # number of protection mode switches system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2430 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 704 +system.cpu1.kern.mode_switch::idle 2061 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 557 system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 216 -system.cpu1.kern.mode_switch_good::kernel 0.500711 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 69 +system.cpu1.kern.mode_switch_good::kernel 0.296908 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.088889 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.325624 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4780653500 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 828450500 0.04% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1895813783000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1119 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.033479 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.251751 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 39690497500 2.09% 2.09% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 850597000 0.04% 2.14% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1857949530000 97.86% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1408 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |