diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3653 |
1 files changed, 1829 insertions, 1824 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 092a1319f..38c6e11f9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901187 # Number of seconds simulated -sim_ticks 1901187238000 # Number of ticks simulated -final_tick 1901187238000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.901175 # Number of seconds simulated +sim_ticks 1901175003500 # Number of ticks simulated +final_tick 1901175003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164685 # Simulator instruction rate (inst/s) -host_op_rate 164685 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5473626023 # Simulator tick rate (ticks/s) -host_mem_usage 324480 # Number of bytes of host memory used -host_seconds 347.34 # Real time elapsed on the host -sim_insts 57201060 # Number of instructions simulated -sim_ops 57201060 # Number of ops (including micro ops) simulated +host_inst_rate 154934 # Simulator instruction rate (inst/s) +host_op_rate 154934 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5197600055 # Simulator tick rate (ticks/s) +host_mem_usage 378544 # Number of bytes of host memory used +host_seconds 365.78 # Real time elapsed on the host +sim_insts 56671579 # Number of instructions simulated +sim_ops 56671579 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 886592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24764800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 96384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 525056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 885824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24795264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 95808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 496320 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26273792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 886592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 96384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7873024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7873024 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13853 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386950 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8204 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26274176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 885824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 95808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7885056 # Number of bytes written to this memory +system.physmem.bytes_written::total 7885056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7755 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410528 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 466336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13025966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 276173 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 410534 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123204 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123204 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 465935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13042073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 261060 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13819676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 466336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50697 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4141109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4141109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4141109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 466336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13025966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 276173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13819967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 465935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50394 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4147465 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4147465 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4147465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 465935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13042073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 261060 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17960785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410528 # Number of read requests accepted -system.physmem.writeReqs 164568 # Number of write requests accepted -system.physmem.readBursts 410528 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 164568 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26267072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 10385920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26273792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10532352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6311 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25881 # Per bank write bursts -system.physmem.perBankRdBursts::1 25672 # Per bank write bursts -system.physmem.perBankRdBursts::2 26260 # Per bank write bursts -system.physmem.perBankRdBursts::3 25757 # Per bank write bursts -system.physmem.perBankRdBursts::4 25283 # Per bank write bursts -system.physmem.perBankRdBursts::5 25202 # Per bank write bursts -system.physmem.perBankRdBursts::6 25755 # Per bank write bursts -system.physmem.perBankRdBursts::7 25257 # Per bank write bursts -system.physmem.perBankRdBursts::8 25550 # Per bank write bursts -system.physmem.perBankRdBursts::9 25721 # Per bank write bursts -system.physmem.perBankRdBursts::10 25770 # Per bank write bursts -system.physmem.perBankRdBursts::11 25804 # Per bank write bursts -system.physmem.perBankRdBursts::12 25810 # Per bank write bursts -system.physmem.perBankRdBursts::13 25881 # Per bank write bursts -system.physmem.perBankRdBursts::14 25644 # Per bank write bursts -system.physmem.perBankRdBursts::15 25176 # Per bank write bursts -system.physmem.perBankWrBursts::0 10943 # Per bank write bursts -system.physmem.perBankWrBursts::1 9789 # Per bank write bursts -system.physmem.perBankWrBursts::2 10222 # Per bank write bursts -system.physmem.perBankWrBursts::3 9625 # Per bank write bursts -system.physmem.perBankWrBursts::4 9290 # Per bank write bursts -system.physmem.perBankWrBursts::5 9560 # Per bank write bursts -system.physmem.perBankWrBursts::6 10277 # Per bank write bursts -system.physmem.perBankWrBursts::7 9346 # Per bank write bursts -system.physmem.perBankWrBursts::8 9649 # Per bank write bursts -system.physmem.perBankWrBursts::9 9784 # Per bank write bursts -system.physmem.perBankWrBursts::10 9978 # Per bank write bursts -system.physmem.perBankWrBursts::11 10113 # Per bank write bursts -system.physmem.perBankWrBursts::12 11182 # Per bank write bursts -system.physmem.perBankWrBursts::13 11629 # Per bank write bursts -system.physmem.perBankWrBursts::14 10712 # Per bank write bursts -system.physmem.perBankWrBursts::15 10181 # Per bank write bursts +system.physmem.bw_total::total 17967432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410534 # Number of read requests accepted +system.physmem.writeReqs 164756 # Number of write requests accepted +system.physmem.readBursts 410534 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 164756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26267904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue +system.physmem.bytesWritten 10393408 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26274176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10544384 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2335 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4921 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25742 # Per bank write bursts +system.physmem.perBankRdBursts::1 25822 # Per bank write bursts +system.physmem.perBankRdBursts::2 25939 # Per bank write bursts +system.physmem.perBankRdBursts::3 25643 # Per bank write bursts +system.physmem.perBankRdBursts::4 25873 # Per bank write bursts +system.physmem.perBankRdBursts::5 25657 # Per bank write bursts +system.physmem.perBankRdBursts::6 25709 # Per bank write bursts +system.physmem.perBankRdBursts::7 25201 # Per bank write bursts +system.physmem.perBankRdBursts::8 25222 # Per bank write bursts +system.physmem.perBankRdBursts::9 26115 # Per bank write bursts +system.physmem.perBankRdBursts::10 25677 # Per bank write bursts +system.physmem.perBankRdBursts::11 25575 # Per bank write bursts +system.physmem.perBankRdBursts::12 25800 # Per bank write bursts +system.physmem.perBankRdBursts::13 26085 # Per bank write bursts +system.physmem.perBankRdBursts::14 25301 # Per bank write bursts +system.physmem.perBankRdBursts::15 25075 # Per bank write bursts +system.physmem.perBankWrBursts::0 10194 # Per bank write bursts +system.physmem.perBankWrBursts::1 10103 # Per bank write bursts +system.physmem.perBankWrBursts::2 10030 # Per bank write bursts +system.physmem.perBankWrBursts::3 9736 # Per bank write bursts +system.physmem.perBankWrBursts::4 9490 # Per bank write bursts +system.physmem.perBankWrBursts::5 10167 # Per bank write bursts +system.physmem.perBankWrBursts::6 10200 # Per bank write bursts +system.physmem.perBankWrBursts::7 9338 # Per bank write bursts +system.physmem.perBankWrBursts::8 9741 # Per bank write bursts +system.physmem.perBankWrBursts::9 10459 # Per bank write bursts +system.physmem.perBankWrBursts::10 10157 # Per bank write bursts +system.physmem.perBankWrBursts::11 10688 # Per bank write bursts +system.physmem.perBankWrBursts::12 11170 # Per bank write bursts +system.physmem.perBankWrBursts::13 11200 # Per bank write bursts +system.physmem.perBankWrBursts::14 10147 # Per bank write bursts +system.physmem.perBankWrBursts::15 9577 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1901182789000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 1901170614000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410528 # Read request sizes (log2) +system.physmem.readPktSize::6 410534 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 164568 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 164756 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,187 +158,193 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 546.521218 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 334.319778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.846112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14858 22.15% 22.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11363 16.94% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5157 7.69% 46.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2935 4.38% 51.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2350 3.50% 54.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 2.54% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1587 2.37% 59.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1704 2.54% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25411 37.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67066 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.402667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2725.840527 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5997 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 545.527075 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 333.566914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.530844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14928 22.21% 22.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11337 16.87% 39.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5205 7.75% 46.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2937 4.37% 51.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2377 3.54% 54.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1798 2.68% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1602 2.38% 59.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1684 2.51% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25335 37.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67203 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6020 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.178073 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2721.311016 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6017 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6000 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.046667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.651184 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.190276 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4953 82.55% 82.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 193 3.22% 85.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 289 4.82% 90.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.83% 91.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 96 1.60% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 44 0.73% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 19 0.32% 94.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 8 0.13% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 23 0.38% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 10 0.17% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 13 0.22% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.10% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 95.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.08% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 20 0.33% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 38 0.63% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.28% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 12 0.20% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 91 1.52% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 43 0.72% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 17 0.28% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 19 0.32% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 8 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6000 # Writes before turning the bus around for reads -system.physmem.totQLat 3893190750 # Total ticks spent queuing -system.physmem.totMemAccLat 11588622000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9485.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6020 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6020 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.976246 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.646869 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.117275 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4955 82.31% 82.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 186 3.09% 85.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 316 5.25% 90.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 58 0.96% 91.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 93 1.54% 93.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 41 0.68% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 21 0.35% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.18% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 26 0.43% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.28% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 7 0.12% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.03% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 20 0.33% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 42 0.70% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 17 0.28% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 7 0.12% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 80 1.33% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 45 0.75% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 12 0.20% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 27 0.45% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 6 0.10% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.08% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.07% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 4 0.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6020 # Writes before turning the bus around for reads +system.physmem.totQLat 3885054500 # Total ticks spent queuing +system.physmem.totMemAccLat 11580729500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9465.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28235.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28215.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 5.47 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.54 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing -system.physmem.readRowHits 370176 # Number of row buffer hits during reads -system.physmem.writeRowHits 135461 # Number of row buffer hits during writes +system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing +system.physmem.readRowHits 370181 # Number of row buffer hits during reads +system.physmem.writeRowHits 135448 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.46 # Row buffer hit rate for writes -system.physmem.avgGap 3305852.92 # Average gap between requests -system.physmem.pageHitRate 88.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800384684500 # Time in different power states -system.physmem.memoryStateTime::REF 63484720000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37315104250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 252216720 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 254802240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 137618250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 139029000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1599522600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1601776800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 512256960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 539317440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 124176112320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 124176112320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 57055460715 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 57001965930 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1090662047250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1090708972500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1274395234815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1274421976230 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.316446 # Core power per rank (mW) -system.physmem.averagePower::1 670.330512 # Core power per rank (mW) -system.cpu0.branchPred.lookups 15024669 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13090822 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 302150 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9266199 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5129053 # Number of BTB hits +system.physmem.writeRowHitRate 83.39 # Row buffer hit rate for writes +system.physmem.avgGap 3304716.95 # Average gap between requests +system.physmem.pageHitRate 88.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 253260000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138187500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1603570800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 513591840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57090888495 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1090621618500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1274396212335 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.322456 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1814181645000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23503077500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 254688840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138967125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597455600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 538429680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57028143465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1090676670000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1274409449910 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.329412 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1814277217000 # Time in different power states +system.physmem_1.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23408681000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu0.branchPred.lookups 16131633 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14074847 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 326763 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9526803 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5411642 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 55.352286 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 762066 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 14857 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 56.804387 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 814199 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17678 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8699665 # DTB read hits -system.cpu0.dtb.read_misses 31652 # DTB read misses -system.cpu0.dtb.read_acv 518 # DTB read access violations -system.cpu0.dtb.read_accesses 684964 # DTB read accesses -system.cpu0.dtb.write_hits 5527628 # DTB write hits -system.cpu0.dtb.write_misses 7312 # DTB write misses -system.cpu0.dtb.write_acv 384 # DTB write access violations -system.cpu0.dtb.write_accesses 236678 # DTB write accesses -system.cpu0.dtb.data_hits 14227293 # DTB hits -system.cpu0.dtb.data_misses 38964 # DTB misses -system.cpu0.dtb.data_acv 902 # DTB access violations -system.cpu0.dtb.data_accesses 921642 # DTB accesses -system.cpu0.itb.fetch_hits 1360805 # ITB hits -system.cpu0.itb.fetch_misses 29325 # ITB misses -system.cpu0.itb.fetch_acv 623 # ITB acv -system.cpu0.itb.fetch_accesses 1390130 # ITB accesses +system.cpu0.dtb.read_hits 9231009 # DTB read hits +system.cpu0.dtb.read_misses 34580 # DTB read misses +system.cpu0.dtb.read_acv 535 # DTB read access violations +system.cpu0.dtb.read_accesses 687791 # DTB read accesses +system.cpu0.dtb.write_hits 5940395 # DTB write hits +system.cpu0.dtb.write_misses 7538 # DTB write misses +system.cpu0.dtb.write_acv 382 # DTB write access violations +system.cpu0.dtb.write_accesses 237219 # DTB write accesses +system.cpu0.dtb.data_hits 15171404 # DTB hits +system.cpu0.dtb.data_misses 42118 # DTB misses +system.cpu0.dtb.data_acv 917 # DTB access violations +system.cpu0.dtb.data_accesses 925010 # DTB accesses +system.cpu0.itb.fetch_hits 1435355 # ITB hits +system.cpu0.itb.fetch_misses 29386 # ITB misses +system.cpu0.itb.fetch_acv 625 # ITB acv +system.cpu0.itb.fetch_accesses 1464741 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,467 +357,466 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 108792579 # number of cpu cycles simulated +system.cpu0.numCycles 112944275 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24480610 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 66921510 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 15024669 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5891119 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 76960209 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1006918 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 587 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 30320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1459024 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 459440 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7808182 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 214478 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103893877 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.944480 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26734623 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70871158 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16131633 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6225841 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 78572167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1087344 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 938 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1452901 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 461019 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8195583 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 233790 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 107793734 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.657470 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.965319 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 91308838 87.89% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 814381 0.78% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1763801 1.70% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 741690 0.71% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2523255 2.43% 93.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 561128 0.54% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 635570 0.61% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 719335 0.69% 95.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4825879 4.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 94531257 87.70% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 858509 0.80% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1823492 1.69% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 785861 0.73% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2602190 2.41% 93.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 590625 0.55% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 664328 0.62% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 839547 0.78% 95.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5097925 4.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103893877 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.138104 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.615129 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19900832 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 73745257 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8046257 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1730950 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 470580 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 495026 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 33344 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 58913691 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 103815 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 470580 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20722206 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 48316669 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17970373 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8856068 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7557979 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 56901533 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 202703 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2015999 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 141191 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3736855 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 38160864 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 69501237 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69376844 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 115358 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33567232 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4593624 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1365129 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 198221 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12480015 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8824182 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5791367 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1299957 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 953544 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50831435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1735186 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49951846 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52661 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5989483 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2856975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1193961 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103893877 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.480797 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.214404 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 107793734 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.142828 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.627488 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21731474 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 75223274 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8544304 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1787077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 507604 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 524648 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36495 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62167212 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 115754 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 507604 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22589385 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48401768 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19164228 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9376952 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7753795 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 60013920 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 204923 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2024034 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 144343 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3822558 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 40119139 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72975711 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72834321 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 131688 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35221894 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4897237 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1480119 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 216056 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12920416 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9368350 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6206352 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1340557 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 962340 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53512619 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1895957 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52599778 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52230 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6392747 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3006442 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1305426 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 107793734 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.487967 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.221871 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 83240383 80.12% 80.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8994841 8.66% 88.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3729897 3.59% 92.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2662216 2.56% 94.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2692674 2.59% 97.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1272103 1.22% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 842802 0.81% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 349148 0.34% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109813 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 86044446 79.82% 79.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9475309 8.79% 88.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3928815 3.64% 92.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2790586 2.59% 94.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2836372 2.63% 97.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1349941 1.25% 98.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 893970 0.83% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 358292 0.33% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 116003 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103893877 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 107793734 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 174329 19.02% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 437335 47.71% 66.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 305033 33.28% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 177733 18.25% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 467063 47.95% 66.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 329340 33.81% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34481483 69.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54630 0.11% 69.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 27712 0.06% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9019851 18.06% 87.26% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5598402 11.21% 98.47% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 764115 1.53% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36087462 68.61% 68.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57222 0.11% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28709 0.05% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9582527 18.22% 87.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6011046 11.43% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 827159 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49951846 # Type of FU issued -system.cpu0.iq.rate 0.459148 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 916697 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018352 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 204260867 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 58336070 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48679612 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 506059 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 237571 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 232415 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 50592327 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 272446 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 560089 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52599778 # Type of FU issued +system.cpu0.iq.rate 0.465714 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 974136 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018520 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 213441030 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61548330 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51220095 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 578625 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 270952 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 265721 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53258517 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 311627 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 583786 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1038811 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4304 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17864 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 487331 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1112279 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5019 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18330 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 503254 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18869 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 349661 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 369989 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 470580 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 44276704 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1577501 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 55768983 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 120052 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8824182 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5791367 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1533608 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 47079 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1307470 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17864 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 152204 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 328517 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 480721 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49479281 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8753036 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 472564 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 507604 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 44339596 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1604348 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58817574 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 124782 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9368350 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6206352 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1675353 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 48473 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1332642 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18330 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164161 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 356822 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 520983 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52091421 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9288991 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 508356 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3202362 # number of nop insts executed -system.cpu0.iew.exec_refs 14301032 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7879408 # Number of branches executed -system.cpu0.iew.exec_stores 5547996 # Number of stores executed -system.cpu0.iew.exec_rate 0.454804 # Inst execution rate -system.cpu0.iew.wb_sent 49022541 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48912027 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25297454 # num instructions producing a value -system.cpu0.iew.wb_consumers 34938196 # num instructions consuming a value +system.cpu0.iew.exec_nop 3408998 # number of nop insts executed +system.cpu0.iew.exec_refs 15250639 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8273174 # Number of branches executed +system.cpu0.iew.exec_stores 5961648 # Number of stores executed +system.cpu0.iew.exec_rate 0.461213 # Inst execution rate +system.cpu0.iew.wb_sent 51600991 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51485816 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26436063 # num instructions producing a value +system.cpu0.iew.wb_consumers 36546981 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.724063 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.455851 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723345 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6548409 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 541225 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 440159 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102738863 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.478033 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.411836 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7016261 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 590531 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 476969 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 106554717 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.485172 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.424408 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 85310078 83.04% 83.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6928869 6.74% 89.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3804927 3.70% 93.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2004533 1.95% 95.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1514323 1.47% 96.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 555844 0.54% 97.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 414883 0.40% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 408778 0.40% 98.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1796628 1.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 88252662 82.82% 82.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7298996 6.85% 89.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3974083 3.73% 93.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2090799 1.96% 95.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1561874 1.47% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 585444 0.55% 97.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 439090 0.41% 97.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 445608 0.42% 98.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1906161 1.79% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102738863 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49112602 # Number of instructions committed -system.cpu0.commit.committedOps 49112602 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 106554717 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51697359 # Number of instructions committed +system.cpu0.commit.committedOps 51697359 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13089407 # Number of memory references committed -system.cpu0.commit.loads 7785371 # Number of loads committed -system.cpu0.commit.membars 183023 # Number of memory barriers committed -system.cpu0.commit.branches 7443994 # Number of branches committed -system.cpu0.commit.fp_insts 229281 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45524861 # Number of committed integer instructions. -system.cpu0.commit.function_calls 617737 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2801788 5.70% 5.70% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32185758 65.53% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 53394 0.11% 71.35% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.35% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 27239 0.06% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7968394 16.22% 87.63% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5310031 10.81% 98.44% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 764115 1.56% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13959169 # Number of memory references committed +system.cpu0.commit.loads 8256071 # Number of loads committed +system.cpu0.commit.membars 200989 # Number of memory barriers committed +system.cpu0.commit.branches 7816314 # Number of branches committed +system.cpu0.commit.fp_insts 262681 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47879291 # Number of committed integer instructions. +system.cpu0.commit.function_calls 663768 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2971590 5.75% 5.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33646334 65.08% 70.83% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55999 0.11% 70.94% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28236 0.05% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8457060 16.36% 87.36% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5709098 11.04% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 827159 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49112602 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1796628 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 51697359 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1906161 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 156399894 # The number of ROB reads -system.cpu0.rob.rob_writes 112470885 # The number of ROB writes -system.cpu0.timesIdled 448982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4898702 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693581898 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46314581 # Number of Instructions Simulated -system.cpu0.committedOps 46314581 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.348992 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.348992 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.425715 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.425715 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65241971 # number of integer regfile reads -system.cpu0.int_regfile_writes 35484902 # number of integer regfile writes -system.cpu0.fp_regfile_reads 114300 # number of floating regfile reads -system.cpu0.fp_regfile_writes 114851 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1680980 # number of misc regfile reads -system.cpu0.misc_regfile_writes 762179 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1226061 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.967877 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9972327 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1226573 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.130235 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 163161097 # The number of ROB reads +system.cpu0.rob.rob_writes 118660594 # The number of ROB writes +system.cpu0.timesIdled 501791 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5150541 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3689405733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48729536 # Number of Instructions Simulated +system.cpu0.committedOps 48729536 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.317779 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.317779 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.431448 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.431448 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68466406 # number of integer regfile reads +system.cpu0.int_regfile_writes 37249066 # number of integer regfile writes +system.cpu0.fp_regfile_reads 130692 # number of floating regfile reads +system.cpu0.fp_regfile_writes 131766 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1811017 # number of misc regfile reads +system.cpu0.misc_regfile_writes 827352 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1291740 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.889209 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10636670 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1292252 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.231111 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.967877 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988219 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988219 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.889209 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988065 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988065 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 53849509 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 53849509 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6192446 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6192446 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3442531 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3442531 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150135 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 150135 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172107 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 172107 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9634977 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9634977 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9634977 # number of overall hits -system.cpu0.dcache.overall_hits::total 9634977 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1501821 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1501821 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1669841 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1669841 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19141 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19141 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4636 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4636 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3171662 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3171662 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3171662 # number of overall misses -system.cpu0.dcache.overall_misses::total 3171662 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39101656628 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39101656628 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78115764371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 78115764371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 290102987 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 290102987 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35172730 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 35172730 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117217420999 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117217420999 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117217420999 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117217420999 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7694267 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7694267 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5112372 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5112372 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169276 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 169276 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176743 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 176743 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12806639 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12806639 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12806639 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12806639 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195187 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.195187 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.326627 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.326627 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113076 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113076 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026230 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026230 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247658 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247658 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247658 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247658 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26036.163183 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26036.163183 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46780.360748 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46780.360748 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15156.104018 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15156.104018 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7586.870147 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7586.870147 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36957.727841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36957.727841 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3837622 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 160954 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.842974 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 37.561798 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 57483025 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 57483025 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6556019 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6556019 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3715997 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3715997 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164872 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 164872 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189733 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189733 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10272016 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10272016 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10272016 # number of overall hits +system.cpu0.dcache.overall_hits::total 10272016 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1615331 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1615331 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1779982 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1779982 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21282 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21282 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2627 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2627 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3395313 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3395313 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3395313 # number of overall misses +system.cpu0.dcache.overall_misses::total 3395313 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40801843239 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40801843239 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80191363617 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 80191363617 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336613990 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336613990 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 19436381 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 19436381 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 120993206856 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 120993206856 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8171350 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8171350 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495979 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5495979 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 186154 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 186154 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192360 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192360 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13667329 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13667329 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13667329 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13667329 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197682 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197682 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323870 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323870 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114325 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114325 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013657 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013657 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248425 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248425 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248425 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248425 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7398.698515 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7398.698515 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3895440 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3799 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 167914 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.199019 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 40.414894 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 711843 # number of writebacks -system.cpu0.dcache.writebacks::total 711843 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 520027 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 520027 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1419840 # 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number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14597 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4636 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4636 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1231795 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1231795 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1231795 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1231795 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27071690424 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27071690424 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11368022018 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11368022018 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148174261 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148174261 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25899270 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25899270 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38439712442 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38439712442 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38439712442 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38439712442 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458085000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458085000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2211101998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2211101998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3669186998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3669186998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127601 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127601 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048901 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048901 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086232 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086232 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026230 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026230 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096184 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096184 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27573.697154 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27573.697154 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45471.906184 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45471.906184 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10151.007810 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10151.007810 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5586.555220 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5586.555220 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 762456 # number of writebacks +system.cpu0.dcache.writebacks::total 762456 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 593909 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 593909 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512221 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1512221 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5168 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5168 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2106130 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2106130 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2106130 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2106130 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 39284989860 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39284989860 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 39284989860 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458359000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458359000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2137811998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2137811998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3596170998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3596170998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048719 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048719 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086563 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086563 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094326 # 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average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -819,126 +824,126 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # 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Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7236389 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 915045 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.908233 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485919250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.589702 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995292 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995292 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 431 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8630516 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8630516 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6946118 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6946118 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6946118 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6946118 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6946118 # number of overall hits -system.cpu0.icache.overall_hits::total 6946118 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 862061 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 862061 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7808179 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7808179 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7808179 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7808179 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7808179 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110405 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110405 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110405 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110405 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110405 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14312.674478 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14312.674478 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14312.674478 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14312.674478 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14312.674478 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14312.674478 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4878 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9110810 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9110810 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7236389 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7236389 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7236389 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7236389 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7236389 # number of overall hits +system.cpu0.icache.overall_hits::total 7236389 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 959193 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 959193 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 959193 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 959193 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 959193 # number of overall misses +system.cpu0.icache.overall_misses::total 959193 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13598697683 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13598697683 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13598697683 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13598697683 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13598697683 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13598697683 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8195582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8195582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8195582 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8195582 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8195582 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8195582 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117038 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117038 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117038 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117038 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117038 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117038 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14177.227819 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14177.227819 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14177.227819 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14177.227819 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4960 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 185 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.367568 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.177665 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39724 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 39724 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 39724 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 39724 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 39724 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 39724 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 822337 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 822337 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 822337 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 822337 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 822337 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 822337 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10177943027 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10177943027 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10177943027 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10177943027 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10177943027 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10177943027 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105317 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105317 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105317 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12376.851616 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43965 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43965 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43965 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43965 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43965 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43965 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915228 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915228 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915228 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915228 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915228 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915228 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11221708315 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11221708315 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11221708315 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11221708315 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11221708315 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11221708315 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111673 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111673 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111673 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12261.106866 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4575539 # Number of BP lookups -system.cpu1.branchPred.condPredicted 4011453 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 80159 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2846769 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1118608 # Number of BTB hits +system.cpu1.branchPred.lookups 3410499 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2981782 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 63006 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1861186 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 813170 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 39.293950 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 219011 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6943 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 43.690958 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 161954 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4822 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2376918 # DTB read hits -system.cpu1.dtb.read_misses 9978 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 290947 # DTB read accesses -system.cpu1.dtb.write_hits 1576285 # DTB write hits -system.cpu1.dtb.write_misses 2026 # DTB write misses -system.cpu1.dtb.write_acv 38 # DTB write access violations -system.cpu1.dtb.write_accesses 109535 # DTB write accesses -system.cpu1.dtb.data_hits 3953203 # DTB hits -system.cpu1.dtb.data_misses 12004 # DTB misses -system.cpu1.dtb.data_acv 43 # DTB access violations -system.cpu1.dtb.data_accesses 400482 # DTB accesses -system.cpu1.itb.fetch_hits 602928 # ITB hits -system.cpu1.itb.fetch_misses 5576 # ITB misses -system.cpu1.itb.fetch_acv 51 # ITB acv -system.cpu1.itb.fetch_accesses 608504 # ITB accesses +system.cpu1.dtb.read_hits 1800297 # DTB read hits +system.cpu1.dtb.read_misses 9623 # DTB read misses +system.cpu1.dtb.read_acv 4 # DTB read access violations +system.cpu1.dtb.read_accesses 290908 # DTB read accesses +system.cpu1.dtb.write_hits 1120103 # DTB write hits +system.cpu1.dtb.write_misses 2035 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 109629 # DTB write accesses +system.cpu1.dtb.data_hits 2920400 # DTB hits +system.cpu1.dtb.data_misses 11658 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 400537 # DTB accesses +system.cpu1.itb.fetch_hits 513208 # ITB hits +system.cpu1.itb.fetch_misses 5417 # ITB misses +system.cpu1.itb.fetch_acv 59 # ITB acv +system.cpu1.itb.fetch_accesses 518625 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -951,463 +956,463 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 18735029 # number of cpu cycles simulated +system.cpu1.numCycles 13834996 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8327481 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17619609 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4575539 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1337619 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9079051 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 321428 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 222369 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 65129 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1934705 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 65647 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 17881393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.985360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.396691 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5742756 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13201278 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3410499 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 975124 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7052078 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 251690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 24829 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 212437 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 51117 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1482208 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50416 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 13209086 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.999409 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.408470 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 14806869 82.81% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 203122 1.14% 83.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 303524 1.70% 85.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 223355 1.25% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 384843 2.15% 89.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149669 0.84% 89.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 166893 0.93% 90.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 294645 1.65% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1348473 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 10898169 82.51% 82.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 144102 1.09% 83.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 239022 1.81% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 173764 1.32% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 293834 2.22% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 119928 0.91% 89.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 132080 1.00% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 175112 1.33% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1033075 7.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 17881393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.244224 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.940463 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6834927 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8400269 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2240291 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 252863 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 153042 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 134285 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7749 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14408505 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 25621 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 153042 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7012697 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 586426 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6840794 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2316099 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 972333 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13683407 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 9781 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 69005 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 16467 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 367791 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 8910587 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16181694 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16097130 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 77675 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7724005 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1186582 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 556647 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 57942 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2323703 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2456737 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1657029 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 275399 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 155321 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12021391 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 653222 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11806375 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22216 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1705669 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 770229 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 468205 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 17881393 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.660260 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.377042 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13209086 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.246512 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.954195 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 4781490 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6446001 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1665086 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 196515 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 119993 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 102189 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5928 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10739248 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 19374 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 119993 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 4918512 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 544557 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5139003 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1724887 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 762132 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10178184 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4877 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 68265 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 13199 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 289695 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6692544 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12133960 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12078154 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 50250 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5671659 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1020885 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 419664 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 38232 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1772644 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1865226 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1191683 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 210655 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 119712 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8963290 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 478811 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8726606 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20522 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1437541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 698510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 352654 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13209086 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.660652 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.378469 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 12935770 72.34% 72.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2198264 12.29% 84.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 914656 5.12% 89.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 630896 3.53% 93.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 572849 3.20% 96.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 314457 1.76% 98.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 208202 1.16% 99.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 77174 0.43% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 29125 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9547804 72.28% 72.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1625741 12.31% 84.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 686242 5.20% 89.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 474957 3.60% 93.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 417301 3.16% 96.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 221804 1.68% 98.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 145793 1.10% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 65024 0.49% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 24420 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 17881393 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13209086 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 23808 8.12% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 159009 54.21% 62.33% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 110483 37.67% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22353 9.61% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 126163 54.23% 63.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 84116 36.16% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7355530 62.30% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 19854 0.17% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12327 0.10% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2486397 21.06% 83.68% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1602376 13.57% 97.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 324614 2.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5425627 62.17% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 15090 0.17% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10661 0.12% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1878240 21.52% 84.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1141614 13.08% 97.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 250097 2.87% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11806375 # Type of FU issued -system.cpu1.iq.rate 0.630176 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 293300 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.024843 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 41494201 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 14236824 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 11389686 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 315458 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 147457 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 145351 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11926347 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 169810 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 115792 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8726606 # Type of FU issued +system.cpu1.iq.rate 0.630763 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 232632 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.026658 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 30722514 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10791679 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8409842 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 192938 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 91772 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 89511 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8852667 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 103053 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 90033 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 308768 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1081 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4102 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 143102 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 271460 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 498 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 125337 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 395 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 55406 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 380 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 50736 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 153042 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 303896 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 248843 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13398271 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 36703 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2456737 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1657029 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 586577 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4501 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 243181 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4102 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 36741 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 118067 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 154808 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11654930 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2396476 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 151445 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 119993 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 268498 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 245239 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9936241 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 29107 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1865226 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1191683 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 435120 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4465 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 239666 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3940 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28286 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 93108 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 121394 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8606074 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1816179 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 120532 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 723658 # number of nop insts executed -system.cpu1.iew.exec_refs 3982565 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1739472 # Number of branches executed -system.cpu1.iew.exec_stores 1586089 # Number of stores executed -system.cpu1.iew.exec_rate 0.622093 # Inst execution rate -system.cpu1.iew.wb_sent 11565622 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11535037 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5422471 # num instructions producing a value -system.cpu1.iew.wb_consumers 7736628 # num instructions consuming a value +system.cpu1.iew.exec_nop 494140 # number of nop insts executed +system.cpu1.iew.exec_refs 2943760 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1279494 # Number of branches executed +system.cpu1.iew.exec_stores 1127581 # Number of stores executed +system.cpu1.iew.exec_rate 0.622051 # Inst execution rate +system.cpu1.iew.wb_sent 8526125 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8499353 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4051784 # num instructions producing a value +system.cpu1.iew.wb_consumers 5752933 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.615694 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.700883 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614337 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.704299 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1839025 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 185017 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142916 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 17538839 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.655077 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.643008 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1506985 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126157 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 110245 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 12932417 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.645119 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.622232 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 13431880 76.58% 76.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1875136 10.69% 87.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 688221 3.92% 91.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 418119 2.38% 93.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 312509 1.78% 95.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 131127 0.75% 96.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 110360 0.63% 96.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 156367 0.89% 97.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 415120 2.37% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 9905025 76.59% 76.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1407731 10.89% 87.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 501740 3.88% 91.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 308618 2.39% 93.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 224670 1.74% 95.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 96970 0.75% 96.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 89070 0.69% 96.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 100805 0.78% 97.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 297788 2.30% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 17538839 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 11489295 # Number of instructions committed -system.cpu1.commit.committedOps 11489295 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 12932417 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8342954 # Number of instructions committed +system.cpu1.commit.committedOps 8342954 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3661896 # Number of memory references committed -system.cpu1.commit.loads 2147969 # Number of loads committed -system.cpu1.commit.membars 61867 # Number of memory barriers committed -system.cpu1.commit.branches 1640602 # Number of branches committed -system.cpu1.commit.fp_insts 143665 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 10598150 # Number of committed integer instructions. -system.cpu1.commit.function_calls 183822 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 606334 5.28% 5.28% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6800030 59.19% 64.46% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 19654 0.17% 64.63% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.63% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 12323 0.11% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 2209836 19.23% 83.99% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1514745 13.18% 97.17% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 324614 2.83% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2660112 # Number of memory references committed +system.cpu1.commit.loads 1593766 # Number of loads committed +system.cpu1.commit.membars 39768 # Number of memory barriers committed +system.cpu1.commit.branches 1189273 # Number of branches committed +system.cpu1.commit.fp_insts 87820 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7729091 # Number of committed integer instructions. +system.cpu1.commit.function_calls 132492 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 404429 4.85% 4.85% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 4960733 59.46% 64.31% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 14917 0.18% 64.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10656 0.13% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1633534 19.58% 84.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1066829 12.79% 97.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 250097 3.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 11489295 # Class of committed instruction -system.cpu1.commit.bw_lim_events 415120 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 8342954 # Class of committed instruction +system.cpu1.commit.bw_lim_events 297788 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 30366198 # The number of ROB reads -system.cpu1.rob.rob_writes 26995045 # The number of ROB writes -system.cpu1.timesIdled 163095 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 853636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3782985916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 10886479 # Number of Instructions Simulated -system.cpu1.committedOps 10886479 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.720945 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.720945 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.581076 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.581076 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14951888 # number of integer regfile reads -system.cpu1.int_regfile_writes 8155185 # number of integer regfile writes -system.cpu1.fp_regfile_reads 77020 # number of floating regfile reads -system.cpu1.fp_regfile_writes 77068 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1117526 # number of misc regfile reads -system.cpu1.misc_regfile_writes 276759 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 138501 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.617684 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3193598 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 138812 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.006642 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 39570817000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.617684 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962144 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.962144 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15087685 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15087685 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1906947 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1906947 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1195571 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1195571 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 44901 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 44901 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 43886 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 43886 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3102518 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3102518 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3102518 # number of overall hits -system.cpu1.dcache.overall_hits::total 3102518 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 266692 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 266692 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 262982 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 262982 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8052 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8052 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4916 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 4916 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 529674 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 529674 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 529674 # number of overall misses -system.cpu1.dcache.overall_misses::total 529674 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4020623652 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4020623652 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8531401983 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8531401983 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 76759992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 76759992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 36344731 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 36344731 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12552025635 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12552025635 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12552025635 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12552025635 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2173639 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2173639 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1458553 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1458553 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 52953 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 52953 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 48802 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 48802 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3632192 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3632192 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3632192 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3632192 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.122694 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.122694 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.180303 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.180303 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152059 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152059 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100734 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100734 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.145828 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.145828 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.145828 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.145828 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15075.906484 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15075.906484 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32441.011107 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32441.011107 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9533.034277 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9533.034277 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7393.151139 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7393.151139 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23697.643522 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23697.643522 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 379144 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 215 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 18342 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.670810 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 23.888889 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 22401053 # The number of ROB reads +system.cpu1.rob.rob_writes 19972727 # The number of ROB writes +system.cpu1.timesIdled 110858 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 625910 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3787862669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 7942043 # Number of Instructions Simulated +system.cpu1.committedOps 7942043 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.741995 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.741995 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.574055 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.574055 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11080172 # number of integer regfile reads +system.cpu1.int_regfile_writes 6056867 # number of integer regfile writes +system.cpu1.fp_regfile_reads 49492 # number of floating regfile reads +system.cpu1.fp_regfile_writes 48750 # number of floating regfile writes +system.cpu1.misc_regfile_reads 911686 # number of misc regfile reads +system.cpu1.misc_regfile_writes 198554 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 93396 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.127271 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2362095 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 93708 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 25.206973 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1032235519500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.127271 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959233 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.959233 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.609375 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11044469 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11044469 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1462423 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1462423 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 846221 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 846221 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29364 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 29364 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27945 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 27945 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2308644 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2308644 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2308644 # number of overall hits +system.cpu1.dcache.overall_hits::total 2308644 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 178507 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 178507 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 183677 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 183677 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4603 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4603 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2762 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2762 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 362184 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 362184 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 362184 # number of overall misses +system.cpu1.dcache.overall_misses::total 362184 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2741731463 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2741731463 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7132330313 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7132330313 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 45481992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 45481992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20461911 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 20461911 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9874061776 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9874061776 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9874061776 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9874061776 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1640930 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1640930 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1029898 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1029898 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33967 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 33967 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 30707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2670828 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2670828 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2670828 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2670828 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108784 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.108784 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178345 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.178345 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.089947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.089947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135607 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135607 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135607 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135607 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9880.945470 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9880.945470 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7408.367487 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7408.367487 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 351094 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 268 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 15302 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.944321 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 17.866667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 93139 # number of writebacks -system.cpu1.dcache.writebacks::total 93139 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 164682 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 164682 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 213530 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 213530 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 378212 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 378212 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 378212 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 378212 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 102010 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 102010 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 49452 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 49452 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7397 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7397 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4916 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 4916 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 151462 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 151462 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 151462 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 151462 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1194457513 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1194457513 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1312928589 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1312928589 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54001007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54001007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26510269 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26510269 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2507386102 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2507386102 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2507386102 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2507386102 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24847500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24847500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 692513000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 692513000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717360500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717360500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046931 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046931 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033905 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033905 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.139690 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.139690 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100734 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100734 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041700 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.041700 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041700 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.041700 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11709.219812 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11709.219812 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26549.554902 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26549.554902 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7300.392997 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7300.392997 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5392.650325 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5392.650325 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16554.555611 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 60059 # number of writebacks +system.cpu1.dcache.writebacks::total 60059 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 108966 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 108966 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 150714 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 150714 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 427 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 259680 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 259680 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 259680 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 259680 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69541 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 69541 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32963 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 32963 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4176 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4176 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2762 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2762 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 102504 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 102504 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 102504 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 102504 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 829052502 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 829052502 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081287205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081287205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31817008 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31817008 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14937089 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14937089 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1910339707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1910339707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1910339707 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1910339707 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24846500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24846500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 618764500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 618764500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643611000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643611000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042379 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042379 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032006 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.122943 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.122943 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.089947 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.089947 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038379 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038379 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7619.015326 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7619.015326 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5408.069877 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5408.069877 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1415,95 +1420,95 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 306147 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.962529 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1618659 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 306656 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.278419 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878409820250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.962529 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919849 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919849 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id +system.cpu1.icache.tags.replacements 205003 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.613699 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1269898 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 205514 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.179131 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1878408675250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.613699 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919167 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919167 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2241410 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2241410 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1618659 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1618659 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1618659 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1618659 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1618659 # number of overall hits -system.cpu1.icache.overall_hits::total 1618659 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316046 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316046 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316046 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316046 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316046 # number of overall misses -system.cpu1.icache.overall_misses::total 316046 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4251188208 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4251188208 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4251188208 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4251188208 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4251188208 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4251188208 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1934705 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1934705 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1934705 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1934705 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1934705 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1934705 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.163356 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.163356 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.163356 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.163356 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.163356 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.163356 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13451.169159 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13451.169159 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13451.169159 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13451.169159 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1687783 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1687783 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1269898 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1269898 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1269898 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1269898 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1269898 # number of overall hits +system.cpu1.icache.overall_hits::total 1269898 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 212310 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 212310 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 212310 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 212310 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 212310 # number of overall misses +system.cpu1.icache.overall_misses::total 212310 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2888653039 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2888653039 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2888653039 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2888653039 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2888653039 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2888653039 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1482208 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1482208 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1482208 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1482208 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1482208 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1482208 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.143239 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.143239 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.143239 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.143239 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.143239 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.143239 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13605.826570 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13605.826570 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 412 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.307692 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.846154 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9341 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 9341 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 9341 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 9341 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 9341 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 9341 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 306705 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 306705 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 306705 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 306705 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 306705 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 306705 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3543296218 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3543296218 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3543296218 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3543296218 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3543296218 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3543296218 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158528 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.158528 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.158528 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11552.782700 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6735 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6735 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6735 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6735 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6735 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6735 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 205575 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 205575 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 205575 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 205575 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 205575 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 205575 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2403236890 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2403236890 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2403236890 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2403236890 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2403236890 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2403236890 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.138695 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.138695 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.138695 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1517,13 +1522,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7368 # Transaction distribution -system.iobus.trans_dist::ReadResp 7368 # Transaction distribution -system.iobus.trans_dist::WriteReq 55198 # Transaction distribution -system.iobus.trans_dist::WriteResp 13646 # Transaction distribution +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 54536 # Transaction distribution +system.iobus.trans_dist::WriteResp 12984 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13082 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1534,12 +1539,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 41682 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123826 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1550,13 +1555,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 78554 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2740162 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12437000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73266 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2734938 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1576,52 +1581,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406224779 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406222784 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28036000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27376000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010550 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42026793 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41693 # number of replacements -system.iocache.tags.tagsinuse 0.465320 # Cycle average of tags in use +system.iocache.tags.replacements 41701 # number of replacements +system.iocache.tags.tagsinuse 0.465228 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710336865000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.465320 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029083 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029083 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710337218000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.465228 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.029077 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.tags.tag_accesses 375597 # Number of tag accesses +system.iocache.tags.data_accesses 375597 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 181 # number of ReadReq misses +system.iocache.ReadReq_misses::total 181 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13658910846 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13658910846 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21134383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21134383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21134383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21134383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 181 # number of demand (read+write) misses +system.iocache.demand_misses::total 181 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 181 # number of overall misses +system.iocache.overall_misses::total 181 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22038383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22038383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13652440608 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13652440608 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22038383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22038383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22038383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22038383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 181 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 181 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 181 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 181 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 181 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 181 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1630,40 +1635,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328718.493598 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328718.493598 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122164.063584 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122164.063584 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 207096 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121759.022099 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121759.022099 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121759.022099 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206720 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23572 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23552 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.785678 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.777174 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 181 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11498106946 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11498106946 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12137383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12137383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12137383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12137383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 181 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 181 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 181 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 181 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12625383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12625383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11491649194 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11491649194 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12625383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12625383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12625383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12625383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1672,189 +1677,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276716.089382 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276716.089382 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345011 # number of replacements -system.l2c.tags.tagsinuse 65255.839207 # Cycle average of tags in use -system.l2c.tags.total_refs 2587062 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410177 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.307184 # Average number of references to valid blocks. +system.l2c.tags.replacements 345072 # number of replacements +system.l2c.tags.tagsinuse 65237.196274 # Cycle average of tags in use +system.l2c.tags.total_refs 2611817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410198 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.367210 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53401.606938 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5320.695867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6228.167915 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 214.693065 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 90.675422 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.814844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081187 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.095034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001384 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995725 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2663 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5629 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5286 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51350 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27100727 # Number of tag accesses -system.l2c.tags.data_accesses 27100727 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 808308 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 697381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 305176 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 93224 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1904089 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 804982 # number of Writeback hits -system.l2c.Writeback_hits::total 804982 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 430 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 602 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 137834 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 34568 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172402 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 808308 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 835215 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 305176 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 127792 # number of demand (read+write) hits -system.l2c.demand_hits::total 2076491 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 808308 # number of overall hits -system.l2c.overall_hits::cpu0.data 835215 # number of overall hits -system.l2c.overall_hits::cpu1.inst 305176 # number of overall hits -system.l2c.overall_hits::cpu1.data 127792 # number of overall hits -system.l2c.overall_hits::total 2076491 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 582978000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2598737500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3382222000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606134500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3988356500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268783 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012318 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.131455 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.939478 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828861 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.903620 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.883991 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.936937 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.910857 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421539 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249399 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.405351 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164384 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164384 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53167.825985 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76666.454082 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53787.048176 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.083673 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.050744 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.503902 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10061.356955 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.805288 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.493099 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70998.038549 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94425.922444 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72353.628002 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1992,101 +1997,101 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296777 # Transaction distribution -system.membus.trans_dist::ReadResp 296698 # Transaction distribution -system.membus.trans_dist::WriteReq 13646 # Transaction distribution -system.membus.trans_dist::WriteResp 13646 # Transaction distribution -system.membus.trans_dist::Writeback 123016 # Transaction distribution +system.membus.trans_dist::ReadReq 296649 # Transaction distribution +system.membus.trans_dist::ReadResp 296568 # Transaction distribution +system.membus.trans_dist::WriteReq 12984 # Transaction distribution +system.membus.trans_dist::WriteResp 12984 # Transaction distribution +system.membus.trans_dist::Writeback 123204 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14268 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9480 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6314 # Transaction distribution -system.membus.trans_dist::ReadExReq 122151 # Transaction distribution -system.membus.trans_dist::ReadExResp 121466 # Transaction distribution -system.membus.trans_dist::BadAddressError 79 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41682 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 933549 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 975389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1100201 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78554 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31488576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31567130 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 9668 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5310 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4924 # Transaction distribution +system.membus.trans_dist::ReadExReq 121989 # Transaction distribution +system.membus.trans_dist::ReadExResp 121610 # Transaction distribution +system.membus.trans_dist::BadAddressError 81 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 923282 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 963804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1088624 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73266 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31500992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31574258 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36884698 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 18563 # Total snoops (count) -system.membus.snoop_fanout::samples 600049 # Request fanout histogram +system.membus.pkt_size::total 36891826 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 10884 # Total snoops (count) +system.membus.snoop_fanout::samples 591178 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600049 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 591178 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600049 # Request fanout histogram -system.membus.reqLayer0.occupancy 40411498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 591178 # Request fanout histogram +system.membus.reqLayer0.occupancy 38973998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1927899500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1927807998 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 99500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3832783452 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3829664091 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43159450 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43225207 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2231232 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2231137 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13646 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13646 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 804982 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 14411 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 23963 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296031 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296031 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1644513 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3224840 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 613391 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 402307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5885051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52619264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123882452 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19627904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14694726 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 210824346 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 91368 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3390565 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012306 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110249 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2228449 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2228352 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12984 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12984 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822515 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9795 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5388 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15183 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301926 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301926 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1830333 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3396960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 411121 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 269188 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5907602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58566720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131328844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13154944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9749222 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 212799730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 73699 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3402430 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012266 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110070 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3348840 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41725 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3360696 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41734 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3390565 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4912159072 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3402430 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4987291538 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3705712969 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4124247177 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5664612723 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5936070669 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1381251781 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 692182943 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 925874109 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 467054772 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2120,32 +2125,32 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6735 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 170888 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 59399 40.36% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1921 1.31% 41.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 339 0.23% 41.99% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 85372 58.01% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 147162 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 58699 49.14% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1921 1.61% 50.86% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 339 0.28% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 58360 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 119450 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1860822176500 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61176000 0.00% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 541931500 0.03% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 152116500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39608995500 2.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901186396000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988215 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6564 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 186274 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65832 40.54% 40.54% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1922 1.18% 41.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 173 0.11% 41.91% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94323 58.09% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162381 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64799 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1922 1.46% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 173 0.13% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64626 49.09% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131651 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1859979639500 97.83% 97.83% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61305500 0.00% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 538798500 0.03% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 78674500 0.00% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40515747500 2.13% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1901174165500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984309 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683596 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811691 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685156 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810754 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed @@ -2177,60 +2182,60 @@ system.cpu0.kern.syscall::144 2 0.86% 99.14% # nu system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 232 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 432 0.28% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3241 2.09% 2.37% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed -system.cpu0.kern.callpal::swpipl 140334 90.29% 92.69% # number of callpals executed -system.cpu0.kern.callpal::rdps 6381 4.11% 96.80% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::rti 4436 2.85% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 155429 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7000 # number of protection mode switches +system.cpu0.kern.callpal::wripir 266 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3573 2.09% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155550 90.98% 93.26% # number of callpals executed +system.cpu0.kern.callpal::rdps 6382 3.73% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4604 2.69% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 391 0.23% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 170980 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7167 # number of protection mode switches system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1354 system.cpu0.kern.mode_good::user 1355 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.193429 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188921 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.324237 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899184407000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2001981000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.317883 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1899194834000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1979323500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3242 # number of times the context was actually changed +system.cpu0.kern.swap_context 3574 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2589 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 70429 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 23508 38.03% 38.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 3.11% 41.14% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 432 0.70% 41.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 35949 58.16% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 61809 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 22831 47.98% 47.98% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 4.04% 52.02% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 432 0.91% 52.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 22399 47.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 47582 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869145937500 98.33% 98.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 530408500 0.03% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 194479500 0.01% 98.37% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30989632500 1.63% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900860458000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.971201 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2428 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 53091 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16423 36.25% 36.25% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 4.24% 40.49% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 266 0.59% 41.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26695 58.92% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45304 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16079 47.18% 47.18% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 5.63% 52.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 266 0.78% 53.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15813 46.40% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34078 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870417466500 98.40% 98.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 530332500 0.03% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 120265000 0.01% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29780754000 1.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900848818000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979054 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.623077 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769823 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.592358 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.752207 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed @@ -2246,35 +2251,35 @@ system.cpu1.kern.syscall::74 9 9.57% 96.81% # nu system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 94 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 339 0.53% 0.53% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1656 2.59% 3.12% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.13% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 56045 87.56% 90.70% # number of callpals executed -system.cpu1.kern.callpal::rdps 2366 3.70% 94.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.40% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.41% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.41% # number of callpals executed -system.cpu1.kern.callpal::rti 3411 5.33% 99.74% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.19% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 173 0.37% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 989 2.11% 2.49% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.49% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40205 85.85% 88.36% # number of callpals executed +system.cpu1.kern.callpal::rdps 2366 5.05% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed +system.cpu1.kern.callpal::rti 2912 6.22% 99.64% # number of callpals executed +system.cpu1.kern.callpal::callsys 124 0.26% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 64005 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1702 # number of protection mode switches +system.cpu1.kern.callpal::total 46833 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1197 # number of protection mode switches system.cpu1.kern.mode_switch::user 384 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2700 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 740 +system.cpu1.kern.mode_switch::idle 2372 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 574 system.cpu1.kern.mode_good::user 384 -system.cpu1.kern.mode_good::idle 356 -system.cpu1.kern.mode_switch_good::kernel 0.434783 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 190 +system.cpu1.kern.mode_switch_good::kernel 0.479532 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.131852 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309235 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6130779500 0.32% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 692688500 0.04% 0.36% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893719133000 99.64% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1657 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.080101 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.290412 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3852720500 0.20% 0.20% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 690217500 0.04% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1895996394000 99.76% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 990 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |