diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3548 |
1 files changed, 1927 insertions, 1621 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 56627054e..8de825134 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896442 # Number of seconds simulated -sim_ticks 1896441913500 # Number of ticks simulated -final_tick 1896441913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903702 # Number of seconds simulated +sim_ticks 1903702212500 # Number of ticks simulated +final_tick 1903702212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132187 # Simulator instruction rate (inst/s) -host_op_rate 132187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4418345683 # Simulator tick rate (ticks/s) -host_mem_usage 311512 # Number of bytes of host memory used -host_seconds 429.22 # Real time elapsed on the host -sim_insts 56737124 # Number of instructions simulated -sim_ops 56737124 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 937984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24915648 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 39872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 337088 # Number of bytes read from this memory -system.physmem.bytes_read::total 28881280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 937984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 39872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7850944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7850944 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389307 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5267 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451270 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122671 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122671 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 494602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13138102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1397716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 177748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15229193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 494602 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4139828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4139828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4139828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 494602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13138102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 177748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19369021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451270 # Total number of read requests seen -system.physmem.writeReqs 122671 # Total number of write requests seen -system.physmem.cpureqs 578881 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28881280 # Total number of bytes read from memory -system.physmem.bytesWritten 7850944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28881280 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7850944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4936 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28331 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28037 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28154 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27902 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28043 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7715 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7756 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7541 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7897 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7761 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7706 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7423 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis +host_inst_rate 94355 # Simulator instruction rate (inst/s) +host_op_rate 94355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3162860632 # Simulator tick rate (ticks/s) +host_mem_usage 314400 # Number of bytes of host memory used +host_seconds 601.89 # Real time elapsed on the host +sim_insts 56791782 # Number of instructions simulated +sim_ops 56791782 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 898816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24768192 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 430592 # Number of bytes read from this memory +system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 898816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7790720 # Number of bytes written to this memory +system.physmem.bytes_written::total 7790720 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387003 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6728 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121730 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121730 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 472141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13010539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 226187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15141931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 472141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4092405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4092405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4092405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 472141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13010539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 226187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19234336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450402 # Total number of read requests seen +system.physmem.writeReqs 121730 # Total number of write requests seen +system.physmem.cpureqs 577215 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28825728 # Total number of bytes read from memory +system.physmem.bytesWritten 7790720 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7790720 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5081 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28209 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27366 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28620 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7522 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7235 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7644 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6897 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7004 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7923 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7633 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8079 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry -system.physmem.totGap 1896440622000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry +system.physmem.totGap 1903701167000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451270 # Categorize read packet sizes +system.physmem.readPktSize::6 450402 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 122671 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 320077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59739 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121730 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -138,224 +138,395 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.physmem.totQLat 7836942250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15642141000 # Sum of mem lat for all requests -system.physmem.totBusLat 2256015000 # Total cycles spent in databus access -system.physmem.totBankLat 5549183750 # Total cycles spent in bank access -system.physmem.avgQLat 17368.99 # Average queueing delay per request -system.physmem.avgBankLat 12298.64 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 910.430717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.153261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2362.806871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14303 35.57% 35.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6082 15.12% 50.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3751 9.33% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2511 6.24% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1745 4.34% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1426 3.55% 74.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1071 2.66% 76.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 838 2.08% 78.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 669 1.66% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 518 1.29% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 558 1.39% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 522 1.30% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 270 0.67% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 231 0.57% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 190 0.47% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 283 0.70% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 119 0.30% 87.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 115 0.29% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 106 0.26% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 202 0.50% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 170 0.42% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 105 0.26% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 478 1.19% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 629 1.56% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 105 0.26% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 36 0.09% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 35 0.09% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 97 0.24% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 7 0.02% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 13 0.03% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 52 0.13% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 1 0.00% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.76% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40212 # Bytes accessed per row activation +system.physmem.totQLat 6402871500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13861687750 # Sum of mem lat for all requests +system.physmem.totBusLat 2251705000 # Total cycles spent in databus access +system.physmem.totBankLat 5207111250 # Total cycles spent in bank access +system.physmem.avgQLat 14217.83 # Average queueing delay per request +system.physmem.avgBankLat 11562.60 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34667.64 # Average memory access latency -system.physmem.avgRdBW 15.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.14 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30780.43 # Average memory access latency +system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.84 # Average write queue length over time -system.physmem.readRowHits 423356 # Number of row buffer hits during reads -system.physmem.writeRowHits 94009 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.64 # Row buffer hit rate for writes -system.physmem.avgGap 3304243.16 # Average gap between requests -system.l2c.replacements 344349 # number of replacements -system.l2c.tagsinuse 65273.956353 # Cycle average of tags in use -system.l2c.total_refs 2577923 # Total number of references to valid blocks. -system.l2c.sampled_refs 409542 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.294649 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53748.349121 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5295.726441 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5975.264441 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 194.705269 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 59.911080 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820135 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080806 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006036 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133237 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940601 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795359 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.892390 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914343 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949219 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.931953 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428583 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.186907 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.401253 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.063410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165793 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.063410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165793 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50443.521644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72273.242630 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 51731.979750 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10071.008172 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.064545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.386869 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.803922 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.115226 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.849735 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68696.865849 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 97466.194672 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70212.348628 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -493,39 +664,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.474409 # Cycle average of tags in use +system.iocache.replacements 41695 # number of replacements +system.iocache.tagsinuse 0.492474 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1705455708000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.474409 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029651 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029651 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.warmup_cycle 1710349466000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.492474 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030780 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030780 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21041998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21041998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10633425431 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10633425431 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10654467429 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10654467429 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10654467429 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10654467429 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21568883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21568883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10518241771 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10518241771 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10539810654 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10539810654 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10539810654 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10539810654 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -534,40 +705,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120931.022989 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255906.464936 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255906.464936 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255343.608997 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255343.608997 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285994 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123250.760000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123250.760000 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 253134.428451 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 253134.428451 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 252589.705802 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 252589.705802 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 276539 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27316 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27281 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.469835 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.136689 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11993249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8471449424 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8471449424 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8483442673 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8483442673 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8483442673 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8483442673 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12468133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8356835276 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8356835276 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8369303409 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8369303409 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8369303409 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8369303409 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -576,14 +747,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68926.718391 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68926.718391 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203875.852522 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203875.852522 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71246.474286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71246.474286 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 201117.522045 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 201117.522045 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -597,35 +768,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12584062 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10588139 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 341886 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8301483 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5323497 # Number of BTB hits +system.cpu0.branchPred.lookups 12372167 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10430268 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 327512 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8051050 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5251093 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.127060 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 804999 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33376 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.222462 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 787082 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28165 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8950032 # DTB read hits -system.cpu0.dtb.read_misses 34820 # DTB read misses -system.cpu0.dtb.read_acv 539 # DTB read access violations -system.cpu0.dtb.read_accesses 674081 # DTB read accesses -system.cpu0.dtb.write_hits 5877992 # DTB write hits -system.cpu0.dtb.write_misses 8366 # DTB write misses -system.cpu0.dtb.write_acv 348 # DTB write access violations -system.cpu0.dtb.write_accesses 235610 # DTB write accesses -system.cpu0.dtb.data_hits 14828024 # DTB hits -system.cpu0.dtb.data_misses 43186 # DTB misses -system.cpu0.dtb.data_acv 887 # DTB access violations -system.cpu0.dtb.data_accesses 909691 # DTB accesses -system.cpu0.itb.fetch_hits 1040487 # ITB hits -system.cpu0.itb.fetch_misses 31672 # ITB misses -system.cpu0.itb.fetch_acv 1020 # ITB acv -system.cpu0.itb.fetch_accesses 1072159 # ITB accesses +system.cpu0.dtb.read_hits 8811099 # DTB read hits +system.cpu0.dtb.read_misses 30390 # DTB read misses +system.cpu0.dtb.read_acv 555 # DTB read access violations +system.cpu0.dtb.read_accesses 626499 # DTB read accesses +system.cpu0.dtb.write_hits 5759352 # DTB write hits +system.cpu0.dtb.write_misses 7345 # DTB write misses +system.cpu0.dtb.write_acv 331 # DTB write access violations +system.cpu0.dtb.write_accesses 208988 # DTB write accesses +system.cpu0.dtb.data_hits 14570451 # DTB hits +system.cpu0.dtb.data_misses 37735 # DTB misses +system.cpu0.dtb.data_acv 886 # DTB access violations +system.cpu0.dtb.data_accesses 835487 # DTB accesses +system.cpu0.itb.fetch_hits 988720 # ITB hits +system.cpu0.itb.fetch_misses 28459 # ITB misses +system.cpu0.itb.fetch_acv 940 # ITB acv +system.cpu0.itb.fetch_accesses 1017179 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,269 +809,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 103751291 # number of cpu cycles simulated +system.cpu0.numCycles 113576100 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25592047 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 64430414 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12584062 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6128496 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12114182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1732019 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37108557 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 208707 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 355709 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 408 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7808396 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 232068 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76528583 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.841913 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.179850 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24795587 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63494847 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12372167 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6038175 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11937811 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1694344 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37245698 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31806 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195246 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 359396 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7671411 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 221670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 75653727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.839282 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.177028 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64414401 84.17% 84.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 777905 1.02% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1574114 2.06% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 716339 0.94% 88.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2604704 3.40% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 529326 0.69% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 586322 0.77% 93.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 831890 1.09% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4493582 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63715916 84.22% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 763032 1.01% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1559362 2.06% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 696709 0.92% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2577784 3.41% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 516509 0.68% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 573501 0.76% 93.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 819035 1.08% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4431879 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76528583 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121291 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.621008 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26850978 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36641611 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11018000 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 937421 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1080572 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 523116 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36832 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63252649 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 110299 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1080572 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27872767 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14726920 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18377517 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10342666 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4128139 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59880890 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6989 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 638699 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1446922 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 40104744 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72926681 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72541237 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 385444 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35232895 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4871841 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1468873 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 214348 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11259122 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9368607 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6150188 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1144221 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 763596 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53152910 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1825418 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51980474 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87912 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5962808 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3052808 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1237037 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76528583 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.679230 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328773 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 75653727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.108933 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559051 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26076145 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36746783 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10850479 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 927296 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1053023 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507905 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35356 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62314637 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105308 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1053023 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27090322 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15013520 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18214120 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10165522 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4117218 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58954969 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7221 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 636497 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1465868 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39489312 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71817747 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71438623 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 379124 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34689683 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4799621 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1442009 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 210125 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11209509 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9215492 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6028586 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1140138 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 729797 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52283270 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1794569 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51124724 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87475 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5854476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3047065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1215266 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 75653727 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.675773 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.327184 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53422858 69.81% 69.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10519380 13.75% 83.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4737419 6.19% 89.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3110993 4.07% 93.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2482363 3.24% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1230781 1.61% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 656198 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 315996 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52595 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52928215 69.96% 69.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10364815 13.70% 83.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4648030 6.14% 89.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3048990 4.03% 93.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2439160 3.22% 97.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1210231 1.60% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 645067 0.85% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 315070 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54149 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76528583 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 75653727 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 81649 11.89% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 319979 46.59% 58.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285231 41.53% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82277 12.13% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 315255 46.46% 58.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 280962 41.41% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3782 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35814992 68.90% 68.91% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57898 0.11% 69.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.02% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15714 0.03% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9315059 17.92% 86.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5946213 11.44% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 824933 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35245093 68.94% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56186 0.11% 69.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15594 0.03% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9165347 17.93% 87.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5826893 11.40% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 809947 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51980474 # Type of FU issued -system.cpu0.iq.rate 0.501010 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 686859 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013214 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 180712322 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60686814 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50945996 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 551979 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267326 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260492 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52374713 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288838 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 545458 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51124724 # Type of FU issued +system.cpu0.iq.rate 0.450136 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 678494 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 178124739 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59681238 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50082929 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 544404 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 263662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 256861 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51514533 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 284900 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 542155 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1121947 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2762 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13266 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 454260 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1111126 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3856 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12844 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 447697 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18544 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 124618 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 153340 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1080572 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10513662 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 794213 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58228726 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 618999 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9368607 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6150188 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1608738 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 580049 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5099 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13266 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 168319 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356582 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 524901 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51585627 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9008604 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 394846 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1053023 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10729289 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 792549 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57283617 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 622169 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9215492 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6028586 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1581349 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 577410 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6280 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12844 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 162347 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 348099 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 510446 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50735914 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8864635 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 388809 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3250398 # number of nop insts executed -system.cpu0.iew.exec_refs 14908735 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8218209 # Number of branches executed -system.cpu0.iew.exec_stores 5900131 # Number of stores executed -system.cpu0.iew.exec_rate 0.497205 # Inst execution rate -system.cpu0.iew.wb_sent 51301062 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51206488 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25493361 # num instructions producing a value -system.cpu0.iew.wb_consumers 34352042 # num instructions consuming a value +system.cpu0.iew.exec_nop 3205778 # number of nop insts executed +system.cpu0.iew.exec_refs 14644864 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8078425 # Number of branches executed +system.cpu0.iew.exec_stores 5780229 # Number of stores executed +system.cpu0.iew.exec_rate 0.446713 # Inst execution rate +system.cpu0.iew.wb_sent 50428595 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50339790 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25084021 # num instructions producing a value +system.cpu0.iew.wb_consumers 33790368 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.493550 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742121 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443225 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742342 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6443785 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 588381 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 491234 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75448011 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685042 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.601476 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6311482 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 579303 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 475138 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 74600704 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681919 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.596319 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56013876 74.24% 74.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8117892 10.76% 85.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4422865 5.86% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2392310 3.17% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1343441 1.78% 95.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 564278 0.75% 96.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 477580 0.63% 97.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 442296 0.59% 97.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1673473 2.22% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55419889 74.29% 74.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8033545 10.77% 85.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4371447 5.86% 90.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2356278 3.16% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1324268 1.78% 95.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 555518 0.74% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 469565 0.63% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 427219 0.57% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1642975 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75448011 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51685042 # Number of instructions committed -system.cpu0.commit.committedOps 51685042 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 74600704 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50871658 # Number of instructions committed +system.cpu0.commit.committedOps 50871658 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13942588 # Number of memory references committed -system.cpu0.commit.loads 8246660 # Number of loads committed -system.cpu0.commit.membars 199926 # Number of memory barriers committed -system.cpu0.commit.branches 7810095 # Number of branches committed -system.cpu0.commit.fp_insts 258326 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47876421 # Number of committed integer instructions. -system.cpu0.commit.function_calls 664533 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1673473 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13685255 # Number of memory references committed +system.cpu0.commit.loads 8104366 # Number of loads committed +system.cpu0.commit.membars 196950 # Number of memory barriers committed +system.cpu0.commit.branches 7686240 # Number of branches committed +system.cpu0.commit.fp_insts 254806 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47114322 # Number of committed integer instructions. +system.cpu0.commit.function_calls 650737 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1642975 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 131700376 # The number of ROB reads -system.cpu0.rob.rob_writes 117338865 # The number of ROB writes -system.cpu0.timesIdled 1069961 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27222708 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3689125904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48725185 # Number of Instructions Simulated -system.cpu0.committedOps 48725185 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 48725185 # Number of Instructions Simulated -system.cpu0.cpi 2.129315 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.129315 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.469634 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.469634 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67898060 # number of integer regfile reads -system.cpu0.int_regfile_writes 37063784 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127956 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129360 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1719000 # number of misc regfile reads -system.cpu0.misc_regfile_writes 824833 # number of misc regfile writes +system.cpu0.rob.rob_reads 129943858 # The number of ROB reads +system.cpu0.rob.rob_writes 115419344 # The number of ROB writes +system.cpu0.timesIdled 1091777 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 37922373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693821721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47948786 # Number of Instructions Simulated +system.cpu0.committedOps 47948786 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47948786 # Number of Instructions Simulated +system.cpu0.cpi 2.368696 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.368696 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.422173 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.422173 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66777793 # number of integer regfile reads +system.cpu0.int_regfile_writes 36448823 # number of integer regfile writes +system.cpu0.fp_regfile_reads 126128 # number of floating regfile reads +system.cpu0.fp_regfile_writes 127569 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1693303 # number of misc regfile reads +system.cpu0.misc_regfile_writes 810480 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,245 +1103,375 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 889638 # number of replacements -system.cpu0.icache.tagsinuse 510.303457 # Cycle average of tags in use -system.cpu0.icache.total_refs 6872883 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 890147 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.721065 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20517812000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.303457 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996686 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996686 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6872883 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6872883 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6872883 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6872883 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6872883 # number of overall hits -system.cpu0.icache.overall_hits::total 6872883 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 935512 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 935512 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 935512 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 935512 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 935512 # number of overall misses -system.cpu0.icache.overall_misses::total 935512 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13284271991 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13284271991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13284271991 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13284271991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13284271991 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13284271991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808395 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7808395 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7808395 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7808395 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7808395 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7808395 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119808 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119808 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119808 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119808 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119808 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119808 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14200.001701 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14200.001701 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14200.001701 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14200.001701 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5547 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 2537 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.240741 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 845.666667 # average number of cycles each access was blocked +system.toL2Bus.throughput 111431458 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2199741 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2199647 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13135 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13135 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 819443 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10566 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6236 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16802 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343057 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301508 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1737096 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3343563 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 452207 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 314296 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5847162 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 55584064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 129094452 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 14469760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 11514982 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 210663258 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210652954 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1479360 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4959879460 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3910967404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5778463419 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1017961113 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 540290711 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 1437243 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 54687 # Transaction distribution +system.iobus.trans_dist::WriteResp 54687 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 124112 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 74458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2736082 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2736082 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11417000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 378279654 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 27523000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.replacements 867916 # number of replacements +system.cpu0.icache.tagsinuse 509.785268 # Cycle average of tags in use +system.cpu0.icache.total_refs 6758563 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 868427 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.782534 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25769681000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.785268 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995674 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995674 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6758564 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6758564 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6758564 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6758564 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6758564 # number of overall hits +system.cpu0.icache.overall_hits::total 6758564 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 912847 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 912847 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 912847 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 912847 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 912847 # number of overall misses +system.cpu0.icache.overall_misses::total 912847 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13149310993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13149310993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13149310993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13149310993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13149310993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13149310993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7671411 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7671411 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7671411 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7671411 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7671411 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7671411 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118993 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118993 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118993 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118993 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118993 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118993 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14404.726086 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14404.726086 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14404.726086 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14404.726086 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3418 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 152 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.486842 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45203 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45203 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45203 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45203 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45203 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45203 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 890309 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 890309 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 890309 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 890309 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 890309 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 890309 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10926647992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10926647992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10926647992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10926647992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10926647992 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10926647992 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114019 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.114019 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.114019 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12272.871545 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44252 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44252 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 44252 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44252 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 44252 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44252 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868595 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 868595 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 868595 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 868595 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 868595 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 868595 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814937089 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814937089 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814937089 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10814937089 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814937089 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10814937089 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113225 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113225 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12451.069934 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1284134 # number of replacements -system.cpu0.dcache.tagsinuse 505.722211 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10611019 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1284646 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.259878 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.722211 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987739 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987739 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6528989 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6528989 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3717707 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3717707 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164546 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164546 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188999 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 188999 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10246696 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10246696 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10246696 # number of overall hits -system.cpu0.dcache.overall_hits::total 10246696 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1596925 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1596925 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1771522 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1771522 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2763 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2763 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3368447 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3368447 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3368447 # number of overall misses -system.cpu0.dcache.overall_misses::total 3368447 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34533208000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34533208000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68837486976 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 68837486976 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 293802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20678500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20678500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 103370694976 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 103370694976 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 103370694976 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 103370694976 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8125914 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8125914 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5489229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5489229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 184964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 184964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13615143 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13615143 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13615143 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13615143 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196523 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.196523 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322727 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322727 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110389 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110389 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014408 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014408 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247404 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247404 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247404 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247404 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21624.815192 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21624.815192 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38857.822243 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38857.822243 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14389.362327 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14389.362327 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7484.075280 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7484.075280 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30687.938678 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30687.938678 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2260715 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 49054 # number of cycles access was blocked +system.cpu0.dcache.replacements 1271376 # number of replacements +system.cpu0.dcache.tagsinuse 505.686526 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10390956 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1271888 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.169710 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 25830000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.686526 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987669 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987669 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6393137 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6393137 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3639350 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3639350 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 161427 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 161427 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185616 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 185616 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10032487 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10032487 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10032487 # number of overall hits +system.cpu0.dcache.overall_hits::total 10032487 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1573505 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1573505 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1738147 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1738147 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20045 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20045 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3020 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3020 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3311652 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3311652 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3311652 # number of overall misses +system.cpu0.dcache.overall_misses::total 3311652 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39654304500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39654304500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77521243901 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77521243901 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 292960500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 292960500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 22204000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 22204000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117175548401 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117175548401 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117175548401 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117175548401 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7966642 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7966642 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5377497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5377497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181472 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 181472 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 188636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13344139 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13344139 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13344139 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13344139 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197512 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323226 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323226 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110458 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110458 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248173 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248173 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248173 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248173 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25201.257384 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25201.257384 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44599.935392 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44599.935392 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14615.140933 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14615.140933 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7352.317881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7352.317881 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35382.808460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35382.808460 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2842539 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 840 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 51698 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 46.086252 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 54.983539 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 120 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 757117 # number of writebacks -system.cpu0.dcache.writebacks::total 757117 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 591865 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 591865 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494302 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1494302 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4660 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4660 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2086167 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2086167 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2086167 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2086167 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1005060 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1005060 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 277220 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 277220 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15758 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15758 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2763 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2763 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1282280 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1282280 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1282280 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1282280 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21590310000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21590310000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10033221203 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10033221203 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 180646500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 180646500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15152500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15152500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31623531203 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31623531203 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31623531203 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31623531203 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465155500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465155500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167706499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167706499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3632861999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3632861999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123686 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123686 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085195 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085195 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014408 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014408 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094180 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094180 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21481.613038 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21481.613038 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36192.270410 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36192.270410 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11463.796167 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11463.796167 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5484.075280 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5484.075280 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 746874 # number of writebacks +system.cpu0.dcache.writebacks::total 746874 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 575080 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 575080 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465992 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1465992 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2041072 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2041072 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2041072 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2041072 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 998425 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 998425 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272155 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272155 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3020 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3020 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1270580 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1270580 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1270580 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1270580 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26454916051 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26454916051 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11388682739 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11388682739 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172348003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172348003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 16164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 16164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 37843598790 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 37843598790 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 37843598790 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 37843598790 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459347502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459347502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2156087498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2156087498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3615435000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3615435000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085876 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085876 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095216 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095216 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26496.648272 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26496.648272 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41846.310885 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41846.310885 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11059.291774 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11059.291774 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5352.317881 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5352.317881 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1178,35 +1479,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2374472 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1973565 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 63683 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1357670 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 789569 # Number of BTB hits +system.cpu1.branchPred.lookups 2604526 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2153409 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 75247 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1513707 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 876072 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 58.156179 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 159848 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6979 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.875930 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 179167 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7740 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1755569 # DTB read hits -system.cpu1.dtb.read_misses 9259 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 277737 # DTB read accesses -system.cpu1.dtb.write_hits 1124169 # DTB write hits -system.cpu1.dtb.write_misses 1775 # DTB write misses -system.cpu1.dtb.write_acv 38 # DTB write access violations -system.cpu1.dtb.write_accesses 104346 # DTB write accesses -system.cpu1.dtb.data_hits 2879738 # DTB hits -system.cpu1.dtb.data_misses 11034 # DTB misses -system.cpu1.dtb.data_acv 44 # DTB access violations -system.cpu1.dtb.data_accesses 382083 # DTB accesses -system.cpu1.itb.fetch_hits 378886 # ITB hits -system.cpu1.itb.fetch_misses 5643 # ITB misses -system.cpu1.itb.fetch_acv 144 # ITB acv -system.cpu1.itb.fetch_accesses 384529 # ITB accesses +system.cpu1.dtb.read_hits 1932131 # DTB read hits +system.cpu1.dtb.read_misses 10237 # DTB read misses +system.cpu1.dtb.read_acv 25 # DTB read access violations +system.cpu1.dtb.read_accesses 320506 # DTB read accesses +system.cpu1.dtb.write_hits 1251341 # DTB write hits +system.cpu1.dtb.write_misses 1962 # DTB write misses +system.cpu1.dtb.write_acv 65 # DTB write access violations +system.cpu1.dtb.write_accesses 130037 # DTB write accesses +system.cpu1.dtb.data_hits 3183472 # DTB hits +system.cpu1.dtb.data_misses 12199 # DTB misses +system.cpu1.dtb.data_acv 90 # DTB access violations +system.cpu1.dtb.data_accesses 450543 # DTB accesses +system.cpu1.itb.fetch_hits 430844 # ITB hits +system.cpu1.itb.fetch_misses 6753 # ITB misses +system.cpu1.itb.fetch_acv 212 # ITB acv +system.cpu1.itb.fetch_accesses 437597 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1219,512 +1520,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14403389 # number of cpu cycles simulated +system.cpu1.numCycles 15794943 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5507969 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11118541 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2374472 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 949417 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1985955 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 349018 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 5777579 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25749 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 54503 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 55745 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1323443 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 42238 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 13629786 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.815753 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.191288 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6044274 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12313553 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2604526 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1055239 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2204838 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 395965 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6209579 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26246 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 62195 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 53260 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1481011 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50405 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14852690 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.829045 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.204427 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11643831 85.43% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 125140 0.92% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 217081 1.59% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 155934 1.14% 89.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 266080 1.95% 91.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 106134 0.78% 91.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 117650 0.86% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 192941 1.42% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 804995 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12647852 85.16% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 141564 0.95% 86.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 235652 1.59% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 175889 1.18% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 303768 2.05% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 119285 0.80% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 129403 0.87% 92.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 209113 1.41% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 890164 5.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13629786 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164855 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.771939 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5440584 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6013692 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1859543 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 99467 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 216499 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 99353 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5852 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10916304 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 17556 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 216499 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5632614 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 346968 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5076489 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1765081 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 592133 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10097386 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55596 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 134498 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 6632848 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12019300 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 11877082 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 142218 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5717715 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 915133 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 422143 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 38586 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1845577 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1850340 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1191384 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 164933 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 85198 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8855097 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 461396 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8635428 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27588 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1251794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 621930 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 331901 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13629786 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.633570 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.306468 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14852690 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164896 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.779588 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5971093 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6462269 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2062064 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 112088 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 245175 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 113398 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7205 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12081319 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21458 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 245175 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6179272 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 425366 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5395094 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1962879 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 644902 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11197795 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 57093 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 157527 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7361429 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13363056 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13213666 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 149390 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6300177 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1061252 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 451071 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 42573 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1993362 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2041709 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1326014 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 180090 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 100258 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9822573 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 491625 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9565946 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 29815 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1410113 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 705464 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 352077 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14852690 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644055 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.318534 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9807862 71.96% 71.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1774840 13.02% 84.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 743934 5.46% 90.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 492954 3.62% 94.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 425816 3.12% 97.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 193635 1.42% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 119802 0.88% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 63937 0.47% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 7006 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10648951 71.70% 71.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1930050 12.99% 84.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 818337 5.51% 90.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 551122 3.71% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 476075 3.21% 97.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 213789 1.44% 98.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 136394 0.92% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 69529 0.47% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8443 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13629786 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14852690 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2819 1.60% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 95112 53.88% 55.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 78586 44.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3207 1.63% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 106178 53.97% 55.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 87357 44.40% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5368636 62.17% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14579 0.17% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10813 0.13% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1836056 21.26% 83.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1146030 13.27% 97.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 254037 2.94% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5966011 62.37% 62.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16243 0.17% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10971 0.11% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2021702 21.13% 83.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1274955 13.33% 97.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 270775 2.83% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8635428 # Type of FU issued -system.cpu1.iq.rate 0.599541 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 176517 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020441 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 30899211 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10469267 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8392820 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 205536 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 100351 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 97198 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8701253 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 107174 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 85247 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9565946 # Type of FU issued +system.cpu1.iq.rate 0.605633 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 196742 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020567 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 33995446 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11620704 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9288457 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 215693 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 105258 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 101999 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9646700 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 112462 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 92569 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 244767 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 715 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1400 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 111607 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 282729 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1535 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1711 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 123624 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 264 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 323 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 14236 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 216499 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 208020 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 39541 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9780313 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 131211 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1850340 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1191384 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 418145 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33976 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1692 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1400 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28557 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 89287 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117844 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8559872 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1771461 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 75556 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 245175 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 256542 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 43339 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10829040 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 147658 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2041709 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1326014 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 444647 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 36382 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1620 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1711 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 33953 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 99696 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 133649 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9473535 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1949759 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 92411 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 463820 # number of nop insts executed -system.cpu1.iew.exec_refs 2903123 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1270722 # Number of branches executed -system.cpu1.iew.exec_stores 1131662 # Number of stores executed -system.cpu1.iew.exec_rate 0.594296 # Inst execution rate -system.cpu1.iew.wb_sent 8515413 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8490018 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3998147 # num instructions producing a value -system.cpu1.iew.wb_consumers 5641896 # num instructions consuming a value +system.cpu1.iew.exec_nop 514842 # number of nop insts executed +system.cpu1.iew.exec_refs 3209162 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1413585 # Number of branches executed +system.cpu1.iew.exec_stores 1259403 # Number of stores executed +system.cpu1.iew.exec_rate 0.599783 # Inst execution rate +system.cpu1.iew.wb_sent 9417236 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9390456 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4401006 # num instructions producing a value +system.cpu1.iew.wb_consumers 6190652 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.589446 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708653 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.594523 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710912 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1285480 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 129495 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 111745 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13413287 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.628190 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.573982 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1449457 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 139548 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 125475 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14607515 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.636458 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.578813 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10261662 76.50% 76.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1478959 11.03% 87.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 542849 4.05% 91.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 333012 2.48% 94.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 234215 1.75% 95.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 91771 0.68% 96.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 99946 0.75% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 99972 0.75% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 270901 2.02% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11126487 76.17% 76.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1625013 11.12% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 604004 4.13% 91.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 371910 2.55% 93.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 263907 1.81% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 102565 0.70% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 109537 0.75% 97.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 110097 0.75% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 293995 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13413287 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8426096 # Number of instructions committed -system.cpu1.commit.committedOps 8426096 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14607515 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9297065 # Number of instructions committed +system.cpu1.commit.committedOps 9297065 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2685350 # Number of memory references committed -system.cpu1.commit.loads 1605573 # Number of loads committed -system.cpu1.commit.membars 41432 # Number of memory barriers committed -system.cpu1.commit.branches 1197085 # Number of branches committed -system.cpu1.commit.fp_insts 95994 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7795496 # Number of committed integer instructions. -system.cpu1.commit.function_calls 132738 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 270901 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2961370 # Number of memory references committed +system.cpu1.commit.loads 1758980 # Number of loads committed +system.cpu1.commit.membars 44792 # Number of memory barriers committed +system.cpu1.commit.branches 1328076 # Number of branches committed +system.cpu1.commit.fp_insts 100787 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8610735 # Number of committed integer instructions. +system.cpu1.commit.function_calls 147103 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 293995 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 22771832 # The number of ROB reads -system.cpu1.rob.rob_writes 19637981 # The number of ROB writes -system.cpu1.timesIdled 118769 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 773603 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3777797828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8011939 # Number of Instructions Simulated -system.cpu1.committedOps 8011939 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8011939 # Number of Instructions Simulated -system.cpu1.cpi 1.797741 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.797741 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556254 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556254 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11010177 # number of integer regfile reads -system.cpu1.int_regfile_writes 6039470 # number of integer regfile writes -system.cpu1.fp_regfile_reads 53089 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52904 # number of floating regfile writes -system.cpu1.misc_regfile_reads 494875 # number of misc regfile reads -system.cpu1.misc_regfile_writes 202385 # number of misc regfile writes -system.cpu1.icache.replacements 202443 # number of replacements -system.cpu1.icache.tagsinuse 470.727745 # Cycle average of tags in use -system.cpu1.icache.total_refs 1113774 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 202955 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.487788 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1886714019000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.727745 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919390 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919390 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1113774 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1113774 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1113774 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1113774 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1113774 # number of overall hits -system.cpu1.icache.overall_hits::total 1113774 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 209669 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 209669 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 209669 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 209669 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 209669 # number of overall misses -system.cpu1.icache.overall_misses::total 209669 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2812457500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2812457500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2812457500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2812457500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2812457500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2812457500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1323443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1323443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1323443 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1323443 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1323443 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1323443 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158427 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.158427 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158427 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.158427 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158427 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.158427 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13413.797462 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13413.797462 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13413.797462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13413.797462 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 72 # number of cycles access was blocked +system.cpu1.rob.rob_reads 24970897 # The number of ROB reads +system.cpu1.rob.rob_writes 21736671 # The number of ROB writes +system.cpu1.timesIdled 134601 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 942253 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3790981004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8842996 # Number of Instructions Simulated +system.cpu1.committedOps 8842996 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8842996 # Number of Instructions Simulated +system.cpu1.cpi 1.786153 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.786153 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.559862 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.559862 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12205153 # number of integer regfile reads +system.cpu1.int_regfile_writes 6674473 # number of integer regfile writes +system.cpu1.fp_regfile_reads 55471 # number of floating regfile reads +system.cpu1.fp_regfile_writes 55305 # number of floating regfile writes +system.cpu1.misc_regfile_reads 527113 # number of misc regfile reads +system.cpu1.misc_regfile_writes 218222 # number of misc regfile writes +system.cpu1.icache.replacements 225540 # number of replacements +system.cpu1.icache.tagsinuse 470.721925 # Cycle average of tags in use +system.cpu1.icache.total_refs 1246547 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 226052 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.514426 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1877726350000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.721925 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919379 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919379 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1246547 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1246547 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1246547 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1246547 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1246547 # number of overall hits +system.cpu1.icache.overall_hits::total 1246547 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 234464 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 234464 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 234464 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 234464 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 234464 # number of overall misses +system.cpu1.icache.overall_misses::total 234464 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3166624000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3166624000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3166624000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3166624000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3166624000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3166624000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1481011 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1481011 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1481011 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1481011 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1481011 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1481011 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158313 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.158313 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158313 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.158313 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158313 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.158313 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.800464 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.800464 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13505.800464 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13505.800464 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.777778 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6654 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6654 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6654 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6654 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6654 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6654 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 203015 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 203015 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 203015 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 203015 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 203015 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 203015 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2347033500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2347033500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2347033500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2347033500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2347033500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2347033500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.153399 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.153399 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.153399 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11560.887127 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8347 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8347 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8347 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8347 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8347 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8347 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 226117 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 226117 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 226117 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 226117 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 226117 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 226117 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2628094387 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2628094387 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2628094387 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2628094387 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2628094387 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2628094387 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152677 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.152677 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.152677 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11622.719154 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 95898 # number of replacements -system.cpu1.dcache.tagsinuse 491.044785 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2359205 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 96213 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.520647 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39003208000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.044785 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.959072 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.959072 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1444297 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1444297 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 860369 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 860369 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29709 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29709 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28445 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 28445 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2304666 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2304666 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2304666 # number of overall hits -system.cpu1.dcache.overall_hits::total 2304666 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 191100 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 191100 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 182257 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 182257 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4958 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4958 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3002 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3002 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 373357 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 373357 # 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Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 43858959000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 491.736427 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.960423 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.960423 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1587502 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1587502 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 943251 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 943251 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32579 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 32579 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 31559 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 31559 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2530753 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2530753 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2530753 # number of overall hits +system.cpu1.dcache.overall_hits::total 2530753 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 209244 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 209244 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 218379 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 218379 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5510 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5510 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3216 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3216 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 427623 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 427623 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 427623 # number of overall misses +system.cpu1.dcache.overall_misses::total 427623 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2938034500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2938034500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7305073698 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7305073698 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 55149000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 55149000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 23385500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 23385500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10243108198 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10243108198 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10243108198 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10243108198 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1796746 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1796746 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1161630 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1161630 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38089 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 38089 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 34775 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 34775 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2958376 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2958376 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2958376 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2958376 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.116457 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.116457 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187994 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.187994 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.144661 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.144661 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092480 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092480 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.144547 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.144547 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.144547 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.144547 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14041.188756 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14041.188756 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33451.356119 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33451.356119 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10008.892922 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10008.892922 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7271.610697 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7271.610697 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23953.595101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23953.595101 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 227083 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3033 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4054 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 58.786020 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.014554 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 62482 # number of writebacks -system.cpu1.dcache.writebacks::total 62482 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 119560 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 119560 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148811 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 148811 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 417 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 417 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 268371 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 268371 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 268371 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 268371 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 71540 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 71540 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 33446 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 33446 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4541 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4541 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3000 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3000 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 104986 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 104986 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 104986 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 104986 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 843257000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 843257000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 841845993 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 841845993 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 36401500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 36401500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16047000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16047000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1685102993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1685102993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1685102993 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1685102993 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 603885500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 603885500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 621984000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 621984000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032079 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032079 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130989 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130989 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095399 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095399 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039203 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039203 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11787.209952 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11787.209952 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25170.304162 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25170.304162 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8016.185862 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8016.185862 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5349 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5349 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 72569 # number of writebacks +system.cpu1.dcache.writebacks::total 72569 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129770 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 129770 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 179212 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 179212 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 594 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 594 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 308982 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 308982 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 308982 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 308982 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79474 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 79474 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39167 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 39167 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4916 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4916 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3216 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3216 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 118641 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 118641 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 118641 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 118641 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 893939249 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 893939249 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081571527 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081571527 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37210004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37210004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16953500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16953500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1975510776 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1975510776 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1975510776 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1975510776 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23615501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23615501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 628297501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 628297501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 651913002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 651913002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044232 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044232 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.129066 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.129066 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092480 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092480 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040103 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040103 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11248.197511 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11248.197511 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27614.357163 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27614.357163 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7569.162734 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7569.162734 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5271.610697 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5271.610697 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1733,161 +2030,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6633 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 185817 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65566 40.59% 40.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.19% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 201 0.12% 41.99% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93709 58.01% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 161530 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64589 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 1.47% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 201 0.15% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64388 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131232 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1860847795500 98.12% 98.12% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64543000 0.00% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567978500 0.03% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 98193500 0.01% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34862560000 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896441070500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.985099 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6605 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 182638 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64421 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.21% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 210 0.13% 41.93% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92368 58.07% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 159055 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63463 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.49% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 210 0.16% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63253 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128982 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863089530500 97.87% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64074500 0.00% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567937500 0.03% 97.90% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 100797000 0.01% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39879064000 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903701403500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.985129 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.687106 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812431 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684793 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810927 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 211 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3552 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wripir 302 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3478 2.07% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 154681 90.79% 93.08% # number of callpals executed -system.cpu0.kern.callpal::rdps 6653 3.90% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.99% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rti 4593 2.70% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170374 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7193 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::swpipl 152288 90.83% 93.12% # number of callpals executed +system.cpu0.kern.callpal::rdps 6536 3.90% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::rti 4500 2.68% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 345 0.21% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 167660 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7044 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1285 +system.cpu0.kern.mode_good::user 1286 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.190324 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.182425 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.319865 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894375479500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2065583000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.308643 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901692288000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2009107500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3553 # number of times the context was actually changed +system.cpu0.kern.swap_context 3479 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2383 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 53842 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16791 36.23% 36.23% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 4.14% 40.37% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 284 0.61% 40.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27352 59.01% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 46348 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16391 47.23% 47.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 5.54% 52.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.82% 53.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16107 46.41% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34703 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871184919000 98.69% 98.69% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531151500 0.03% 98.71% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 127549500 0.01% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24258165000 1.28% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896101785000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976178 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 57331 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18009 36.73% 36.73% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.92% 40.65% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 302 0.62% 41.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28797 58.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49032 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17590 47.41% 47.41% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 5.19% 52.59% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 302 0.81% 53.41% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17288 46.59% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37104 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1873168497000 98.41% 98.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531845000 0.03% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 136792000 0.01% 98.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29552054000 1.55% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903389188000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976734 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.588878 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.748749 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.600340 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.756730 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 115 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 201 0.42% 0.42% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.43% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.43% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1067 2.24% 2.67% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.67% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.69% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41171 86.33% 89.01% # number of callpals executed -system.cpu1.kern.callpal::rdps 2098 4.40% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2971 6.23% 99.66% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.25% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 210 0.41% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1165 2.30% 2.72% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.73% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.75% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43701 86.29% 89.04% # number of callpals executed +system.cpu1.kern.callpal::rdps 2223 4.39% 93.43% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.43% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.44% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.44% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.44% # number of callpals executed +system.cpu1.kern.callpal::rti 3104 6.13% 99.57% # number of callpals executed +system.cpu1.kern.callpal::callsys 172 0.34% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 47692 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1242 # number of protection mode switches -system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2406 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 576 -system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 208 -system.cpu1.kern.mode_switch_good::kernel 0.463768 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 50643 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1414 # number of protection mode switches +system.cpu1.kern.mode_switch::user 459 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2447 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 685 +system.cpu1.kern.mode_good::user 459 +system.cpu1.kern.mode_good::idle 226 +system.cpu1.kern.mode_switch_good::kernel 0.484441 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086451 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286853 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4070064000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 689483000 0.04% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1891020032000 99.75% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1068 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.092358 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.317130 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4654463000 0.24% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 807268500 0.04% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1897916233000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1166 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |