diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3902 |
1 files changed, 1961 insertions, 1941 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 7571a76a8..c3ff68c1f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906957 # Number of seconds simulated -sim_ticks 1906956794000 # Number of ticks simulated -final_tick 1906956794000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.921764 # Number of seconds simulated +sim_ticks 1921763645000 # Number of ticks simulated +final_tick 1921763645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101212 # Simulator instruction rate (inst/s) -host_op_rate 101212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3411514986 # Simulator tick rate (ticks/s) -host_mem_usage 375140 # Number of bytes of host memory used -host_seconds 558.98 # Real time elapsed on the host -sim_insts 56575230 # Number of instructions simulated -sim_ops 56575230 # Number of ops (including micro ops) simulated +host_inst_rate 133766 # Simulator instruction rate (inst/s) +host_op_rate 133766 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4532754153 # Simulator tick rate (ticks/s) +host_mem_usage 384052 # Number of bytes of host memory used +host_seconds 423.97 # Real time elapsed on the host +sim_insts 56713315 # Number of instructions simulated +sim_ops 56713315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 862400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24773696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 117248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 514752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 874240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24774144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 514944 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26269056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 862400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 117248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 979648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861568 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861568 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13475 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1832 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8043 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26267328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 874240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7875136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7875136 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13660 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387096 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8046 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410454 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122837 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122837 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 452239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12991220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 61484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 269934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13775381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 452239 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 61484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4122573 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4122573 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4122573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 452239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12991220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 61484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 269934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17897953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410454 # Number of read requests accepted -system.physmem.writeReqs 122837 # Number of write requests accepted -system.physmem.readBursts 410454 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122837 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 7860160 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26269056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7861568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410427 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123049 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123049 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 454915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12891358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 267954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13668345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 454915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53617 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 508533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4097869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4097869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4097869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 454915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12891358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 267954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17766214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410427 # Number of read requests accepted +system.physmem.writeReqs 123049 # Number of write requests accepted +system.physmem.readBursts 410427 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123049 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26259904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 7874176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26267328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7875136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 46373 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26161 # Per bank write bursts -system.physmem.perBankRdBursts::1 25973 # Per bank write bursts -system.physmem.perBankRdBursts::2 26108 # Per bank write bursts -system.physmem.perBankRdBursts::3 25765 # Per bank write bursts -system.physmem.perBankRdBursts::4 25066 # Per bank write bursts -system.physmem.perBankRdBursts::5 25574 # Per bank write bursts -system.physmem.perBankRdBursts::6 25905 # Per bank write bursts -system.physmem.perBankRdBursts::7 25241 # Per bank write bursts -system.physmem.perBankRdBursts::8 25825 # Per bank write bursts -system.physmem.perBankRdBursts::9 26325 # Per bank write bursts -system.physmem.perBankRdBursts::10 25290 # Per bank write bursts -system.physmem.perBankRdBursts::11 25205 # Per bank write bursts -system.physmem.perBankRdBursts::12 25472 # Per bank write bursts -system.physmem.perBankRdBursts::13 25390 # Per bank write bursts -system.physmem.perBankRdBursts::14 25632 # Per bank write bursts -system.physmem.perBankRdBursts::15 25396 # Per bank write bursts -system.physmem.perBankWrBursts::0 8442 # Per bank write bursts -system.physmem.perBankWrBursts::1 7958 # Per bank write bursts -system.physmem.perBankWrBursts::2 8052 # Per bank write bursts -system.physmem.perBankWrBursts::3 7723 # Per bank write bursts -system.physmem.perBankWrBursts::4 7027 # Per bank write bursts -system.physmem.perBankWrBursts::5 7199 # Per bank write bursts -system.physmem.perBankWrBursts::6 7428 # Per bank write bursts -system.physmem.perBankWrBursts::7 6815 # Per bank write bursts -system.physmem.perBankWrBursts::8 7536 # Per bank write bursts -system.physmem.perBankWrBursts::9 7897 # Per bank write bursts -system.physmem.perBankWrBursts::10 7294 # Per bank write bursts -system.physmem.perBankWrBursts::11 7366 # Per bank write bursts -system.physmem.perBankWrBursts::12 7733 # Per bank write bursts -system.physmem.perBankWrBursts::13 8096 # Per bank write bursts -system.physmem.perBankWrBursts::14 8387 # Per bank write bursts -system.physmem.perBankWrBursts::15 7862 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 46661 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25500 # Per bank write bursts +system.physmem.perBankRdBursts::1 25969 # Per bank write bursts +system.physmem.perBankRdBursts::2 26011 # Per bank write bursts +system.physmem.perBankRdBursts::3 25727 # Per bank write bursts +system.physmem.perBankRdBursts::4 25508 # Per bank write bursts +system.physmem.perBankRdBursts::5 25811 # Per bank write bursts +system.physmem.perBankRdBursts::6 25519 # Per bank write bursts +system.physmem.perBankRdBursts::7 25160 # Per bank write bursts +system.physmem.perBankRdBursts::8 25451 # Per bank write bursts +system.physmem.perBankRdBursts::9 25839 # Per bank write bursts +system.physmem.perBankRdBursts::10 25659 # Per bank write bursts +system.physmem.perBankRdBursts::11 25030 # Per bank write bursts +system.physmem.perBankRdBursts::12 26076 # Per bank write bursts +system.physmem.perBankRdBursts::13 25978 # Per bank write bursts +system.physmem.perBankRdBursts::14 25473 # Per bank write bursts +system.physmem.perBankRdBursts::15 25600 # Per bank write bursts +system.physmem.perBankWrBursts::0 8066 # Per bank write bursts +system.physmem.perBankWrBursts::1 8046 # Per bank write bursts +system.physmem.perBankWrBursts::2 8027 # Per bank write bursts +system.physmem.perBankWrBursts::3 7668 # Per bank write bursts +system.physmem.perBankWrBursts::4 7376 # Per bank write bursts +system.physmem.perBankWrBursts::5 7761 # Per bank write bursts +system.physmem.perBankWrBursts::6 7583 # Per bank write bursts +system.physmem.perBankWrBursts::7 6991 # Per bank write bursts +system.physmem.perBankWrBursts::8 7326 # Per bank write bursts +system.physmem.perBankWrBursts::9 7600 # Per bank write bursts +system.physmem.perBankWrBursts::10 7532 # Per bank write bursts +system.physmem.perBankWrBursts::11 7413 # Per bank write bursts +system.physmem.perBankWrBursts::12 7962 # Per bank write bursts +system.physmem.perBankWrBursts::13 8267 # Per bank write bursts +system.physmem.perBankWrBursts::14 7722 # Per bank write bursts +system.physmem.perBankWrBursts::15 7694 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 1906952476500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1921759329500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410454 # Read request sizes (log2) +system.physmem.readPktSize::6 410427 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122837 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123049 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,187 +158,199 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.098216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.146393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.677441 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14983 23.10% 23.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11330 17.47% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5177 7.98% 48.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3304 5.09% 53.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2428 3.74% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1616 2.49% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1474 2.27% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1311 2.02% 64.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23234 35.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64857 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5518 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.361182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2842.300525 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5515 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 72 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 522.687084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.252168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.914363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14928 22.86% 22.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11344 17.37% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5465 8.37% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2873 4.40% 53.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2572 3.94% 56.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1636 2.51% 59.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3782 5.79% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1204 1.84% 67.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21501 32.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65305 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5548 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.956561 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2834.723442 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5545 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5518 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.257158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.834122 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.444866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4906 88.91% 88.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 212 3.84% 92.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 76 1.38% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 18 0.33% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 9 0.16% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 6 0.11% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 17 0.31% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 11 0.20% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 35 0.63% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 173 3.14% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.14% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.09% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 6 0.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 4 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5518 # Writes before turning the bus around for reads -system.physmem.totQLat 4043689250 # Total ticks spent queuing -system.physmem.totMemAccLat 11737339250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9854.77 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5548 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.176280 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.947134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.868875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4772 86.01% 86.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 155 2.79% 88.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 19 0.34% 89.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 186 3.35% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 8 0.14% 92.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.38% 93.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.74% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 18 0.32% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 27 0.49% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.16% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.36% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.43% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 29 0.52% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 158 2.85% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.04% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.07% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 14 0.25% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5548 # Writes before turning the bus around for reads +system.physmem.totQLat 4465229000 # Total ticks spent queuing +system.physmem.totMemAccLat 12158560250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10882.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28604.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29632.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing -system.physmem.readRowHits 369741 # Number of row buffer hits during reads -system.physmem.writeRowHits 98545 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.22 # Row buffer hit rate for writes -system.physmem.avgGap 3575819.72 # Average gap between requests -system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242910360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132540375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1605185400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392973120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57318973425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1093892654250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278138192210 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.251160 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1819616623000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63677380000 # Time in different power states +system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing +system.physmem.readRowHits 369445 # Number of row buffer hits during reads +system.physmem.writeRowHits 98595 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes +system.physmem.avgGap 3602335.12 # Average gap between requests +system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245919240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134182125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1600599000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 398636640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63180018945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1097637063000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1288716655350 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.590642 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1825809460500 # Time in different power states +system.physmem_0.memoryStateTime::REF 64171900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23660103250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31782207000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247408560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134994750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1595373000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402868080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57679570530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1093576349250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278189519450 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.278071 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1819088073250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63677380000 # Time in different power states +system.physmem_1.actEnergy 247786560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135201000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1599826800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 398623680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62993858085 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1097800353750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1288695886275 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.579840 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1826084104500 # Time in different power states +system.physmem_1.memoryStateTime::REF 64171900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24188666750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31507549250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16421216 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14369135 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 322041 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10416019 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5388507 # Number of BTB hits +system.cpu0.branchPred.lookups 16172722 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14147320 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 315974 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10263532 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5327857 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.732884 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 814349 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 18392 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 51.910561 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 805529 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17788 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9282981 # DTB read hits -system.cpu0.dtb.read_misses 32197 # DTB read misses -system.cpu0.dtb.read_acv 549 # DTB read access violations -system.cpu0.dtb.read_accesses 681404 # DTB read accesses -system.cpu0.dtb.write_hits 5956980 # DTB write hits -system.cpu0.dtb.write_misses 7300 # DTB write misses -system.cpu0.dtb.write_acv 382 # DTB write access violations -system.cpu0.dtb.write_accesses 235779 # DTB write accesses -system.cpu0.dtb.data_hits 15239961 # DTB hits -system.cpu0.dtb.data_misses 39497 # DTB misses -system.cpu0.dtb.data_acv 931 # DTB access violations -system.cpu0.dtb.data_accesses 917183 # DTB accesses -system.cpu0.itb.fetch_hits 1451467 # ITB hits -system.cpu0.itb.fetch_misses 20802 # ITB misses -system.cpu0.itb.fetch_acv 603 # ITB acv -system.cpu0.itb.fetch_accesses 1472269 # ITB accesses +system.cpu0.dtb.read_hits 9178933 # DTB read hits +system.cpu0.dtb.read_misses 32423 # DTB read misses +system.cpu0.dtb.read_acv 530 # DTB read access violations +system.cpu0.dtb.read_accesses 683199 # DTB read accesses +system.cpu0.dtb.write_hits 5878949 # DTB write hits +system.cpu0.dtb.write_misses 7260 # DTB write misses +system.cpu0.dtb.write_acv 384 # DTB write access violations +system.cpu0.dtb.write_accesses 235377 # DTB write accesses +system.cpu0.dtb.data_hits 15057882 # DTB hits +system.cpu0.dtb.data_misses 39683 # DTB misses +system.cpu0.dtb.data_acv 914 # DTB access violations +system.cpu0.dtb.data_accesses 918576 # DTB accesses +system.cpu0.itb.fetch_hits 1433805 # ITB hits +system.cpu0.itb.fetch_misses 20098 # ITB misses +system.cpu0.itb.fetch_acv 602 # ITB acv +system.cpu0.itb.fetch_accesses 1453903 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,598 +363,599 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 115722397 # number of cpu cycles simulated +system.cpu0.numCycles 146988157 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26666578 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 71121267 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16421216 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6202856 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 81967119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1079386 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 563 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29093 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 971886 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 464461 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8198819 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 234916 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 110639677 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.642819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.946891 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26434329 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70323281 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16172722 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6133386 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 112438747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1062414 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 847 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 925731 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 462393 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 403 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8125656 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 231201 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 140823886 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.499370 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.736005 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 97354556 87.99% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 847860 0.77% 88.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1824694 1.65% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 789927 0.71% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2609447 2.36% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576925 0.52% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 654110 0.59% 94.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 850099 0.77% 95.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5132059 4.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 127673480 90.66% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 835079 0.59% 91.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1817427 1.29% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 778983 0.55% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2600412 1.85% 94.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 568090 0.40% 95.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 652333 0.46% 95.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 824353 0.59% 96.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5073729 3.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 110639677 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.141902 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614585 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21680681 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78105435 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8575313 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1774700 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 503547 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 522363 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36577 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62219552 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 111460 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 503547 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22526069 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 50558199 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19082823 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9419071 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8549966 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 60053732 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 197896 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2013708 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 145060 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4631346 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 40115150 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72965738 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72822559 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 133404 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35357429 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4757713 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1490349 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 215164 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12632454 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9363221 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6214194 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1348186 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 960020 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53527289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1914294 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52757497 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 50335 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6507909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2851663 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1318911 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 110639677 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.476841 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.213091 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 140823886 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.110027 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.478428 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21407057 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108692435 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8462793 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1765937 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 495663 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 515138 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35957 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61540375 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 109013 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 495663 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22243524 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 77757616 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19856258 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9307175 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11163648 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59419645 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 199110 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2023904 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 235068 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7176378 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39704161 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72277966 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72138515 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 129817 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34987460 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4716693 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1464722 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 211632 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12540163 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9262921 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6150917 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1355884 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 997025 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52994830 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1876718 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52216371 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52644 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6477091 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2861227 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1292062 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 140823886 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.370792 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088351 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 88942477 80.39% 80.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9398072 8.49% 88.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3917958 3.54% 92.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2747278 2.48% 94.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2855598 2.58% 97.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1392573 1.26% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 913992 0.83% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 361366 0.33% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 110363 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 119350315 84.75% 84.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9307127 6.61% 91.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3871720 2.75% 94.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2724493 1.93% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2821208 2.00% 98.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1374944 0.98% 99.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 898986 0.64% 99.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 361887 0.26% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 113206 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 110639677 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 140823886 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 181613 18.32% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 474655 47.88% 66.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 334992 33.79% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 180499 18.19% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 473486 47.73% 65.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 338115 34.08% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36170574 68.56% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57549 0.11% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28793 0.05% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9634233 18.26% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6027526 11.42% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 833151 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35829212 68.62% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56563 0.11% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28580 0.05% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9526937 18.25% 87.04% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5949680 11.39% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 819736 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52757497 # Type of FU issued -system.cpu0.iq.rate 0.455897 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 991260 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018789 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 216609620 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61691492 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51347656 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 586645 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 275208 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 269627 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53428897 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 316072 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 584424 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52216371 # Type of FU issued +system.cpu0.iq.rate 0.355242 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 992101 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019000 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 245730281 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61098362 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50826597 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 571091 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 267903 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 262355 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52896880 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307812 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 579556 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1070558 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2876 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17548 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 473318 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1070231 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2809 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17956 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496898 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 412098 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18718 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 406168 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 503547 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 47448039 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 802619 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58859222 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 120684 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9363221 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6214194 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1691778 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39350 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 562336 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17548 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 158131 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 358107 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516238 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52248436 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9338690 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 509060 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 495663 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 74229287 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1063310 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58247929 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 119878 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9262921 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6150917 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1658630 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39535 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 822687 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17956 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 156887 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 351474 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 508361 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51713827 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9234499 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 502543 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3417639 # number of nop insts executed -system.cpu0.iew.exec_refs 15316719 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8298030 # Number of branches executed -system.cpu0.iew.exec_stores 5978029 # Number of stores executed -system.cpu0.iew.exec_rate 0.451498 # Inst execution rate -system.cpu0.iew.wb_sent 51729756 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51617283 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26562977 # num instructions producing a value -system.cpu0.iew.wb_consumers 36791821 # num instructions consuming a value +system.cpu0.iew.exec_nop 3376381 # number of nop insts executed +system.cpu0.iew.exec_refs 15134335 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8213447 # Number of branches executed +system.cpu0.iew.exec_stores 5899836 # Number of stores executed +system.cpu0.iew.exec_rate 0.351823 # Inst execution rate +system.cpu0.iew.wb_sent 51204042 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51088952 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26321891 # num instructions producing a value +system.cpu0.iew.wb_consumers 36458900 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.446044 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.721980 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.347572 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.721961 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6839384 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 595383 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 473671 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 109429659 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.474443 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.410223 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6803374 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 584656 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 464905 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 139620670 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.367725 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.257359 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 91094862 83.25% 83.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7261881 6.64% 89.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3995871 3.65% 93.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2069124 1.89% 95.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1633444 1.49% 96.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 582030 0.53% 97.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 441609 0.40% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 443115 0.40% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1907723 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 121488072 87.01% 87.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7189020 5.15% 92.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3942453 2.82% 94.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2051651 1.47% 96.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1610967 1.15% 97.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 576073 0.41% 98.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 437348 0.31% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 435843 0.31% 98.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1889243 1.35% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 109429659 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51918164 # Number of instructions committed -system.cpu0.commit.committedOps 51918164 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 139620670 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51342045 # Number of instructions committed +system.cpu0.commit.committedOps 51342045 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14033539 # Number of memory references committed -system.cpu0.commit.loads 8292663 # Number of loads committed -system.cpu0.commit.membars 202804 # Number of memory barriers committed -system.cpu0.commit.branches 7846921 # Number of branches committed -system.cpu0.commit.fp_insts 266538 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 48077974 # Number of committed integer instructions. -system.cpu0.commit.function_calls 666824 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2988262 5.76% 5.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33767854 65.04% 70.80% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 56339 0.11% 70.90% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.90% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28331 0.05% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8495467 16.36% 87.33% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5746879 11.07% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 833149 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13846709 # Number of memory references committed +system.cpu0.commit.loads 8192690 # Number of loads committed +system.cpu0.commit.membars 198882 # Number of memory barriers committed +system.cpu0.commit.branches 7762297 # Number of branches committed +system.cpu0.commit.fp_insts 259271 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47551840 # Number of committed integer instructions. +system.cpu0.commit.function_calls 657143 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2951360 5.75% 5.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33433980 65.12% 70.87% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55376 0.11% 70.98% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28117 0.05% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8391572 16.34% 87.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5660021 11.02% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 819736 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51918164 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1907723 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166079481 # The number of ROB reads -system.cpu0.rob.rob_writes 118719518 # The number of ROB writes -system.cpu0.timesIdled 511712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5082720 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698191192 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48933669 # Number of Instructions Simulated -system.cpu0.committedOps 48933669 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.364883 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.364883 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.422854 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.422854 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68649325 # number of integer regfile reads -system.cpu0.int_regfile_writes 37335516 # number of integer regfile writes -system.cpu0.fp_regfile_reads 132501 # number of floating regfile reads -system.cpu0.fp_regfile_writes 134063 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1824055 # number of misc regfile reads -system.cpu0.misc_regfile_writes 833586 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1296864 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.135915 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10665502 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1297376 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.220826 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26097500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.135915 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988547 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988547 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 51342045 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1889243 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 195675599 # The number of ROB reads +system.cpu0.rob.rob_writes 117488366 # The number of ROB writes +system.cpu0.timesIdled 519286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6164271 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3696539134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48394452 # Number of Instructions Simulated +system.cpu0.committedOps 48394452 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.037294 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.037294 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.329240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.329240 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67992315 # number of integer regfile reads +system.cpu0.int_regfile_writes 36972661 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128885 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130381 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1712039 # number of misc regfile reads +system.cpu0.misc_regfile_writes 819549 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1282830 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.258957 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10531989 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1283342 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.206689 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.258957 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988787 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988787 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 57664711 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 57664711 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6558537 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6558537 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3738792 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3738792 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165967 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 165967 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191452 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191452 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10297329 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10297329 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10297329 # number of overall hits -system.cpu0.dcache.overall_hits::total 10297329 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1618045 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1618045 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1793563 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1793563 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21339 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21339 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2425 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2425 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3411608 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3411608 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3411608 # number of overall misses -system.cpu0.dcache.overall_misses::total 3411608 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39371994500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39371994500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77781772548 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77781772548 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331348500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 331348500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20480000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20480000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117153767048 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117153767048 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117153767048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117153767048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8176582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8176582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5532355 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5532355 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 187306 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 187306 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193877 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 193877 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13708937 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13708937 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13708937 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13708937 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197888 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197888 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324195 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324195 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113926 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113926 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012508 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012508 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248860 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248860 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248860 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248860 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24333.065211 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24333.065211 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43367.181720 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43367.181720 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15527.836356 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15527.836356 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8445.360825 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8445.360825 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34339.750361 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34339.750361 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4364063 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4809 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 121083 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 97 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.041913 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 49.577320 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 56925383 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56925383 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6490454 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6490454 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3680062 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3680062 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162917 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 162917 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187619 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 187619 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10170516 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10170516 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10170516 # number of overall hits +system.cpu0.dcache.overall_hits::total 10170516 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1594902 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1594902 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1768783 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1768783 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20957 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20957 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2842 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2842 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3363685 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3363685 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3363685 # number of overall misses +system.cpu0.dcache.overall_misses::total 3363685 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54779472000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54779472000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114120076576 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114120076576 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 388638000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 388638000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44723000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44723000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 168899548576 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 168899548576 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 168899548576 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 168899548576 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8085356 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8085356 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5448845 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5448845 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183874 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183874 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190461 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 190461 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13534201 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13534201 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13534201 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13534201 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197258 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197258 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324616 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324616 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113975 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113975 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014922 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014922 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248532 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248532 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248532 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248532 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34346.606876 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34346.606876 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64518.980890 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64518.980890 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18544.543589 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18544.543589 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15736.453202 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15736.453202 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50212.653259 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50212.653259 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6977235 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 18493 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 125 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.354674 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 147.944000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 766891 # number of writebacks -system.cpu0.dcache.writebacks::total 766891 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 594303 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 594303 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523628 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1523628 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5200 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5200 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2117931 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2117931 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2117931 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2117931 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1023742 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1023742 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 269935 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 269935 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16139 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16139 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2425 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2425 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1293677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1293677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1293677 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1293677 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7035 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7035 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10024 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10024 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17059 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17059 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29563027500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29563027500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12280270109 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12280270109 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188351000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188351000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18055000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18055000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41843297609 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 41843297609 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41843297609 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 41843297609 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1480741500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1480741500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2153066498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153066498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3633807998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3633807998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012508 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012508 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094367 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094367 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28877.419799 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28877.419799 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45493.434008 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45493.434008 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11670.549600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11670.549600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7445.360825 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7445.360825 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210482.089552 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210482.089552 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214791.151038 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214791.151038 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 213014.127323 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 213014.127323 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 756224 # number of writebacks +system.cpu0.dcache.writebacks::total 756224 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579464 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 579464 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502811 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1502811 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5193 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5193 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082275 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2082275 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082275 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2082275 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015438 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1015438 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265972 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 265972 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15764 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15764 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2841 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2841 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1281410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281410 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1281410 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10125 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17170 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43462270000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43462270000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18192812239 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18192812239 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186019000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186019000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41882000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41882000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61655082239 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61655082239 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61655082239 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61655082239 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1482526500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1482526500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2174117500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2174117500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3656644000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3656644000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048813 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048813 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014916 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014916 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094679 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094679 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42801.500436 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42801.500436 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68401.231103 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68401.231103 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11800.241056 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11800.241056 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14741.992256 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14741.992256 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210436.692690 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210436.692690 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214727.654321 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214727.654321 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212967.035527 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212967.035527 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 927295 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.382377 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7224199 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 927807 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.786317 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28149280500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.382377 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994887 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994887 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9126911 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9126911 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7224199 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7224199 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7224199 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7224199 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7224199 # number of overall hits -system.cpu0.icache.overall_hits::total 7224199 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 974618 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 974618 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 974618 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 974618 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 974618 # number of overall misses -system.cpu0.icache.overall_misses::total 974618 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13621983991 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13621983991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13621983991 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13621983991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13621983991 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13621983991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8198817 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8198817 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8198817 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8198817 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8198817 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8198817 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118873 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118873 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118873 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118873 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118873 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118873 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13976.741647 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13976.741647 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13976.741647 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13976.741647 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5225 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 909478 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.072720 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7170024 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 909987 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.879260 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42291813500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.072720 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992330 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992330 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9035950 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9035950 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7170024 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7170024 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7170024 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7170024 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7170024 # number of overall hits +system.cpu0.icache.overall_hits::total 7170024 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 955631 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 955631 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 955631 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 955631 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 955631 # number of overall misses +system.cpu0.icache.overall_misses::total 955631 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14538250986 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14538250986 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14538250986 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14538250986 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14538250986 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14538250986 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8125655 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8125655 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8125655 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8125655 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8125655 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8125655 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117607 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117607 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117607 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117607 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117607 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117607 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15213.247567 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15213.247567 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15213.247567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15213.247567 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8860 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 285 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.738916 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 31.087719 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 46524 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 46524 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 46524 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 46524 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 46524 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 46524 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 928094 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 928094 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 928094 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 928094 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 928094 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 928094 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12135046494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12135046494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12135046494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12135046494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12135046494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12135046494 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113199 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113199 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13075.234291 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45336 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45336 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45336 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45336 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45336 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45336 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 910295 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 910295 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 910295 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 910295 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 910295 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 910295 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12844771491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12844771491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12844771491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12844771491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12844771491 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12844771491 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112027 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.112027 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.112027 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14110.559204 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3314305 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2896651 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 61906 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1740825 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 779195 # Number of BTB hits +system.cpu1.branchPred.lookups 3566695 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3123821 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 62988 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1777720 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 839763 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 44.760099 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 157645 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4636 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 47.238204 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 169438 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 5003 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1755656 # DTB read hits -system.cpu1.dtb.read_misses 9508 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 286377 # DTB read accesses -system.cpu1.dtb.write_hits 1073642 # DTB write hits -system.cpu1.dtb.write_misses 1995 # DTB write misses -system.cpu1.dtb.write_acv 40 # DTB write access violations -system.cpu1.dtb.write_accesses 108795 # DTB write accesses -system.cpu1.dtb.data_hits 2829298 # DTB hits -system.cpu1.dtb.data_misses 11503 # DTB misses -system.cpu1.dtb.data_acv 45 # DTB access violations -system.cpu1.dtb.data_accesses 395172 # DTB accesses -system.cpu1.itb.fetch_hits 497795 # ITB hits -system.cpu1.itb.fetch_misses 4809 # ITB misses -system.cpu1.itb.fetch_acv 84 # ITB acv -system.cpu1.itb.fetch_accesses 502604 # ITB accesses +system.cpu1.dtb.read_hits 1880373 # DTB read hits +system.cpu1.dtb.read_misses 9576 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 286028 # DTB read accesses +system.cpu1.dtb.write_hits 1172828 # DTB write hits +system.cpu1.dtb.write_misses 2034 # DTB write misses +system.cpu1.dtb.write_acv 35 # DTB write access violations +system.cpu1.dtb.write_accesses 108538 # DTB write accesses +system.cpu1.dtb.data_hits 3053201 # DTB hits +system.cpu1.dtb.data_misses 11610 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 394566 # DTB accesses +system.cpu1.itb.fetch_hits 516269 # ITB hits +system.cpu1.itb.fetch_misses 4737 # ITB misses +system.cpu1.itb.fetch_acv 64 # ITB acv +system.cpu1.itb.fetch_accesses 521006 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -955,563 +968,564 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 13378620 # number of cpu cycles simulated +system.cpu1.numCycles 14959639 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5528968 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12732566 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3314305 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 936840 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 6841586 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 246622 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 24765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 177717 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 60433 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1438917 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48462 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 12756788 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.998101 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.406721 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6140426 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13703075 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3566695 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1009201 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7602996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 256204 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 312 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 176452 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 62292 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1530550 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50498 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14135722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.969393 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.379564 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 10526481 82.52% 82.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 138708 1.09% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 230541 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 169879 1.33% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 284565 2.23% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 115144 0.90% 89.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 131557 1.03% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 159487 1.25% 92.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1000426 7.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11742806 83.07% 83.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 150793 1.07% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 240174 1.70% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 177797 1.26% 87.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 306821 2.17% 89.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 121463 0.86% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 138409 0.98% 91.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 186182 1.32% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1071277 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 12756788 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.247731 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.951710 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4581654 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6264793 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1608431 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 184437 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 117472 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 99495 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5921 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10317942 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 18589 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 117472 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4714026 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 446929 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4987547 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1661018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 829794 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 9788331 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3632 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 64825 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 14992 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 371131 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6443318 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 11674537 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 11622438 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 46696 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5463726 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 979592 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 407944 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 36440 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1686696 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1800249 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1144526 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 213224 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 121752 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8623787 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 466284 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8415044 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20175 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1448509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 669329 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 345933 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 12756788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.659652 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.379213 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14135722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.238421 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.916003 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5035823 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7049483 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1732735 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 195750 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 121930 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 104865 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6244 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11127162 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 19879 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 121930 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5174702 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 499846 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5538858 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1790125 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1010259 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10570144 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4276 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 68050 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 20115 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 516529 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6943229 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12595828 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12537363 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52773 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5938747 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1004482 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 436817 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 40607 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1800852 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1926573 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1243636 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 225182 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 130261 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9311043 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 502453 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9112092 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20417 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1494632 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 673391 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 369352 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14135722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644615 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.367603 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9236176 72.40% 72.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1557417 12.21% 84.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 656816 5.15% 89.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 459502 3.60% 93.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 405096 3.18% 96.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 217416 1.70% 98.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 137120 1.07% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 62655 0.49% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 24590 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10331729 73.09% 73.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1677616 11.87% 84.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 710014 5.02% 89.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 492260 3.48% 93.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 443396 3.14% 96.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 237464 1.68% 98.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 151784 1.07% 99.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 65612 0.46% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 25847 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 12756788 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14135722 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22931 9.91% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 125391 54.21% 64.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 82988 35.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 23101 9.34% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 135152 54.66% 64.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 89008 36.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5217804 62.01% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14291 0.17% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10471 0.12% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1829208 21.74% 84.10% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1094853 13.01% 97.11% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 243140 2.89% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5665609 62.18% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16110 0.18% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10836 0.12% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1960524 21.52% 84.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1194738 13.11% 97.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 258998 2.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8415044 # Type of FU issued -system.cpu1.iq.rate 0.628992 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 231310 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027488 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 29661025 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10457474 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8106737 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 177336 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 85037 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 82464 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8548271 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 94565 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87834 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9112092 # Type of FU issued +system.cpu1.iq.rate 0.609112 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247261 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027135 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 32423377 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11214835 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8782259 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 204207 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 97217 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 94699 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9246642 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 109193 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94025 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 257024 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 716 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4046 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 124034 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 261324 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4031 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 123982 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 425 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 63290 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 65647 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 117472 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 288545 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 130999 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9554579 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 24166 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1800249 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1144526 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 424658 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4139 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 125975 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4046 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28597 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 88577 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117174 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8309020 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1771054 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 106024 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 121930 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 296920 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 166801 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10329862 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 27466 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1926573 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1243636 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 455903 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4091 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 161850 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4031 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28253 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 94223 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 122476 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8997942 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1896570 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 114150 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 464508 # number of nop insts executed -system.cpu1.iew.exec_refs 2851870 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1230259 # Number of branches executed -system.cpu1.iew.exec_stores 1080816 # Number of stores executed -system.cpu1.iew.exec_rate 0.621067 # Inst execution rate -system.cpu1.iew.wb_sent 8217653 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8189201 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3916216 # num instructions producing a value -system.cpu1.iew.wb_consumers 5553340 # num instructions consuming a value +system.cpu1.iew.exec_nop 516366 # number of nop insts executed +system.cpu1.iew.exec_refs 3077114 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1335580 # Number of branches executed +system.cpu1.iew.exec_stores 1180544 # Number of stores executed +system.cpu1.iew.exec_rate 0.601481 # Inst execution rate +system.cpu1.iew.wb_sent 8905860 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8876958 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4235192 # num instructions producing a value +system.cpu1.iew.wb_consumers 6022422 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.612111 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.705200 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.593394 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.703237 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1470840 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 120351 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 107539 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 12487025 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642311 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620138 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1521482 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 133101 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 111980 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13855601 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.631015 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.609308 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 9576588 76.69% 76.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1351659 10.82% 87.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 487280 3.90% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 294734 2.36% 93.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 217151 1.74% 95.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 92181 0.74% 96.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 81385 0.65% 96.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 96065 0.77% 97.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 289982 2.32% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10693520 77.18% 77.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1462734 10.56% 87.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 528018 3.81% 91.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 318233 2.30% 93.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 242012 1.75% 95.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 100894 0.73% 96.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 90931 0.66% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 102553 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 316706 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 12487025 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8020551 # Number of instructions committed -system.cpu1.commit.committedOps 8020551 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13855601 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8743092 # Number of instructions committed +system.cpu1.commit.committedOps 8743092 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2563717 # Number of memory references committed -system.cpu1.commit.loads 1543225 # Number of loads committed -system.cpu1.commit.membars 37500 # Number of memory barriers committed -system.cpu1.commit.branches 1142801 # Number of branches committed -system.cpu1.commit.fp_insts 80747 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7435629 # Number of committed integer instructions. -system.cpu1.commit.function_calls 128494 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 382508 4.77% 4.77% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 4766897 59.43% 64.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14118 0.18% 64.38% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10465 0.13% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1580725 19.71% 84.24% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1020940 12.73% 96.97% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 243139 3.03% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2784903 # Number of memory references committed +system.cpu1.commit.loads 1665249 # Number of loads committed +system.cpu1.commit.membars 42287 # Number of memory barriers committed +system.cpu1.commit.branches 1247450 # Number of branches committed +system.cpu1.commit.fp_insts 93039 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8096711 # Number of committed integer instructions. +system.cpu1.commit.function_calls 139604 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 427747 4.89% 4.89% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5200103 59.48% 64.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 15945 0.18% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10829 0.12% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1707536 19.53% 84.23% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1120175 12.81% 97.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 258998 2.96% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8020551 # Class of committed instruction -system.cpu1.commit.bw_lim_events 289982 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 21604416 # The number of ROB reads -system.cpu1.rob.rob_writes 19248787 # The number of ROB writes -system.cpu1.timesIdled 107122 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 621832 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3799884834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 7641561 # Number of Instructions Simulated -system.cpu1.committedOps 7641561 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.750771 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.750771 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.571177 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.571177 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 10694286 # number of integer regfile reads -system.cpu1.int_regfile_writes 5846668 # number of integer regfile writes -system.cpu1.fp_regfile_reads 46070 # number of floating regfile reads -system.cpu1.fp_regfile_writes 45105 # number of floating regfile writes -system.cpu1.misc_regfile_reads 889333 # number of misc regfile reads -system.cpu1.misc_regfile_writes 191018 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 88757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.801602 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2280391 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 89062 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 25.604534 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1034185237500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.801602 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960550 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.960550 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 10633162 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 10633162 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1420631 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1420631 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 810208 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 810208 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 27933 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 27933 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 26395 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 26395 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2230839 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2230839 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2230839 # number of overall hits -system.cpu1.dcache.overall_hits::total 2230839 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 166361 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 166361 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 175617 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 175617 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4254 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4254 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2523 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2523 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 341978 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 341978 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 341978 # number of overall misses -system.cpu1.dcache.overall_misses::total 341978 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2085855500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2085855500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6615792667 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6615792667 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 40341500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 40341500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21053500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 21053500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8701648167 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8701648167 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8701648167 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8701648167 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1586992 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1586992 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 985825 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 985825 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 32187 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 32187 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 28918 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 28918 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2572817 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2572817 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2572817 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2572817 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.104828 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.104828 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178142 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.178142 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.132165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.132165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087247 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087247 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132920 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.132920 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132920 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.132920 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12538.127927 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12538.127927 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37671.709840 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37671.709840 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9483.192290 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9483.192290 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8344.629409 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8344.629409 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 25445.052509 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 25445.052509 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 379425 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 575 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15060 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.194223 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 47.916667 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 8743092 # Class of committed instruction +system.cpu1.commit.bw_lim_events 316706 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 23719092 # The number of ROB reads +system.cpu1.rob.rob_writes 20805392 # The number of ROB writes +system.cpu1.timesIdled 122607 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 823917 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3827854089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8318863 # Number of Instructions Simulated +system.cpu1.committedOps 8318863 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.798279 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.798279 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556087 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556087 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11586341 # number of integer regfile reads +system.cpu1.int_regfile_writes 6325577 # number of integer regfile writes +system.cpu1.fp_regfile_reads 52057 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51356 # number of floating regfile writes +system.cpu1.misc_regfile_reads 501983 # number of misc regfile reads +system.cpu1.misc_regfile_writes 207801 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 98586 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.617617 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2459541 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 98896 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.869975 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 61777830500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.617617 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950425 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.950425 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11508888 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11508888 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1514240 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1514240 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 887339 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 887339 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 31145 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 31145 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29838 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 29838 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2401579 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2401579 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2401579 # number of overall hits +system.cpu1.dcache.overall_hits::total 2401579 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 186104 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 186104 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 193582 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 193582 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4934 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4934 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2994 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2994 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 379686 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 379686 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 379686 # number of overall misses +system.cpu1.dcache.overall_misses::total 379686 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2502679500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2502679500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9084892318 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9084892318 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46731500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46731500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48320000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 48320000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11587571818 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11587571818 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11587571818 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11587571818 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1700344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1700344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1080921 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1080921 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36079 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 36079 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32832 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 32832 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2781265 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2781265 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2781265 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2781265 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109451 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.109451 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179090 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.179090 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136755 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136755 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136516 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.136516 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136516 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.136516 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13447.746959 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13447.746959 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46930.460053 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46930.460053 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9471.321443 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9471.321443 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16138.944556 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16138.944556 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30518.828237 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 30518.828237 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 537858 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1114 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 16003 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.609823 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 123.777778 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 56462 # number of writebacks -system.cpu1.dcache.writebacks::total 56462 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 100117 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 100117 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 144305 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 144305 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 244422 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 244422 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 244422 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 244422 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 66244 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 66244 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 31312 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 31312 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3781 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3781 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2522 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2522 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 97556 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 97556 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 97556 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 97556 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2884 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2884 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3042 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3042 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 801271000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 801271000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1099670460 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1099670460 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31948000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31948000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18531500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18531500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1900941460 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1900941460 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1900941460 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1900941460 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29727000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29727000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 636171000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 636171000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 665898000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 665898000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.041742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031762 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117470 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117470 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.037918 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.037918 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12095.752068 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12095.752068 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35119.777082 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35119.777082 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8449.616504 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8449.616504 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7347.938144 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7347.938144 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188145.569620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188145.569620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220586.338419 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220586.338419 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 218901.380671 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 218901.380671 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 63787 # number of writebacks +system.cpu1.dcache.writebacks::total 63787 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 112960 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 112960 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 158580 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 158580 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 271540 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 271540 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 271540 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 271540 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73144 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 73144 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35002 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 35002 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4480 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4480 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2993 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2993 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 108146 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 108146 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 108146 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 108146 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2930 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3080 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 925590000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 925590000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553309551 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1553309551 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37834000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37834000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45327000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45327000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2478899551 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2478899551 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2478899551 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2478899551 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 28469500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 28469500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 648479500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 648479500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676949000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676949000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043017 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043017 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032382 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032382 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124172 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124172 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091161 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091161 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038884 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038884 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12654.353057 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12654.353057 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44377.737015 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44377.737015 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8445.089286 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8445.089286 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15144.336786 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15144.336786 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189796.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189796.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221324.061433 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 221324.061433 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 219788.636364 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 219788.636364 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 200477 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.242239 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1230816 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 200989 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.123798 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882066156500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.242239 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918442 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.918442 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1639971 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1639971 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1230816 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1230816 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1230816 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1230816 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1230816 # number of overall hits -system.cpu1.icache.overall_hits::total 1230816 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 208101 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 208101 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 208101 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 208101 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 208101 # number of overall misses -system.cpu1.icache.overall_misses::total 208101 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2838828500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2838828500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2838828500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2838828500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2838828500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2838828500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1438917 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1438917 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1438917 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1438917 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1438917 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1438917 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.144623 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.144623 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.144623 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.144623 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.144623 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.144623 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.589901 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13641.589901 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13641.589901 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13641.589901 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 462 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 222828 # number of replacements +system.cpu1.icache.tags.tagsinuse 467.348174 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1300089 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 223338 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.821172 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1895764140500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.348174 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912789 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.912789 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1753949 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1753949 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1300089 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1300089 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1300089 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1300089 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1300089 # number of overall hits +system.cpu1.icache.overall_hits::total 1300089 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 230461 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 230461 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 230461 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 230461 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 230461 # number of overall misses +system.cpu1.icache.overall_misses::total 230461 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3280299500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3280299500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3280299500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3280299500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3280299500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3280299500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1530550 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1530550 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1530550 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1530550 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1530550 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1530550 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150574 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.150574 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150574 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.150574 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150574 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.150574 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.642569 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14233.642569 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14233.642569 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14233.642569 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 780 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.400000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.571429 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7047 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7047 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7047 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7047 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7047 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7047 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 201054 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 201054 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 201054 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 201054 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 201054 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 201054 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2552554500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2552554500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2552554500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2552554500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2552554500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2552554500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.139726 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.139726 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.139726 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12695.865290 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7062 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7062 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7062 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7062 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7062 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7062 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223399 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 223399 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 223399 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 223399 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 223399 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 223399 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2948315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2948315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2948315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2948315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2948315500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2948315500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.145960 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.145960 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13197.532218 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1527,10 +1541,10 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7371 # Transaction distribution system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 54460 # Transaction distribution -system.iobus.trans_dist::WriteResp 54460 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54607 # Transaction distribution +system.iobus.trans_dist::WriteResp 54607 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1541,12 +1555,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40202 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123662 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1557,13 +1571,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 72634 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734282 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 10965000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73826 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2735458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11255000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1583,52 +1597,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216128229 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215099741 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27294000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27445000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.504095 # Cycle average of tags in use +system.iocache.tags.replacements 41696 # number of replacements +system.iocache.tags.tagsinuse 0.507802 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711315950000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.504095 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031506 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031506 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1725999022000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.507802 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031738 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031738 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.tags.tag_accesses 375552 # Number of tag accesses +system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses +system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses -system.iocache.demand_misses::total 178 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 178 # number of overall misses -system.iocache.overall_misses::total 178 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22218883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22218883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907321346 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907321346 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22218883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22218883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22218883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22218883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses +system.iocache.demand_misses::total 176 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 176 # number of overall misses +system.iocache.overall_misses::total 176 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22249883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22249883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427997858 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427997858 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22249883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22249883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22249883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22249883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1637,40 +1651,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124825.185393 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124825.185393 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.725501 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118100.725501 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124825.185393 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124825.185393 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126419.789773 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126419.789773 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.446332 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130631.446332 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126419.789773 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126419.789773 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13318883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13318883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829721346 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829721346 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13318883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13318883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13318883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13318883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13449883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13449883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350397858 # 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number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 155099500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 879940500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 32258819000 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 823353 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 823353 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2908 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1232 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4140 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 401 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 392 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 793 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 274611 # 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number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 87483 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2510373 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 927784 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1294082 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 201024 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 87483 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2510373 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941541 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.813312 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.903382 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.877805 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.933673 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.163785 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20846.420745 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20682.634731 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.540107 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.977273 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.885246 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20795.264624 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78686.950306 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99977.129554 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 79960.958820 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68476.578575 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67661.174174 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98060.972615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68476.578575 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197982.089552 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175645.569620 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197491.450021 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203275.039904 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208450.589459 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204431.399132 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201092.268011 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 206746.712689 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 201947.987662 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938372 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.810089 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.898016 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.893709 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.945263 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.919872 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.424719 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.243604 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.406588 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013474 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270321 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012303 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254274 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71779.934688 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71691.391941 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71754.807692 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71285.194175 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71790.645880 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71548.780488 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129416.394357 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 148234.089047 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130545.015195 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124263.473250 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114195.362953 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130834.344660 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114245.434061 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197936.692690 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177296.666667 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197506.393329 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203210.666667 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209194.197952 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204553.581003 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201046.709377 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 207640.746753 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202049.654321 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7193 # Transaction distribution -system.membus.trans_dist::ReadResp 296434 # Transaction distribution -system.membus.trans_dist::WriteReq 12908 # Transaction distribution -system.membus.trans_dist::WriteResp 12908 # Transaction distribution -system.membus.trans_dist::Writeback 122837 # Transaction distribution -system.membus.trans_dist::CleanEvict 263082 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9353 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4872 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4824 # Transaction distribution -system.membus.trans_dist::ReadExReq 122000 # Transaction distribution -system.membus.trans_dist::ReadExResp 121659 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289315 # Transaction distribution -system.membus.trans_dist::BadAddressError 74 # Transaction distribution +system.membus.trans_dist::ReadReq 7195 # Transaction distribution +system.membus.trans_dist::ReadResp 296388 # Transaction distribution +system.membus.trans_dist::WriteReq 13055 # Transaction distribution +system.membus.trans_dist::WriteResp 13055 # Transaction distribution +system.membus.trans_dist::Writeback 123049 # Transaction distribution +system.membus.trans_dist::CleanEvict 262884 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10279 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5759 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5112 # Transaction distribution +system.membus.trans_dist::ReadExReq 122086 # Transaction distribution +system.membus.trans_dist::ReadExResp 121678 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289268 # Transaction distribution +system.membus.trans_dist::BadAddressError 75 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1184934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1225284 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1350114 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72634 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31472384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31545018 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1227712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1352540 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73826 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31484224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31558050 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34203258 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10191 # Total snoops (count) -system.membus.snoop_fanout::samples 873294 # Request fanout histogram +system.membus.pkt_size::total 34216290 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11781 # Total snoops (count) +system.membus.snoop_fanout::samples 875308 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 873294 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875308 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 873294 # Request fanout histogram -system.membus.reqLayer0.occupancy 36159500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875308 # Request fanout histogram +system.membus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1354680439 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1356119148 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 95500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 92500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2187139696 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2187698407 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72110882 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69909650 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2235424 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12908 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12908 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 946207 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1643079 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9387 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4947 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14334 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302784 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302784 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1129148 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1099173 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 5063061 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2531463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 338644 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1334 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1266 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2238892 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13055 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13055 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 943078 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1635745 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10313 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5834 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16147 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301580 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301580 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1133694 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1098094 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2591178 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3901537 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 531442 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 279415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7303572 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59378176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131958120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 12865536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9234898 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213436730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 458492 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5507130 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.077786 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.267834 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2554026 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3861302 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 573119 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 309440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7297887 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58240320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130381048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 14295680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10315306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213232354 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462162 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5511701 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.123436 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.329209 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 5078755 92.22% 92.22% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 428375 7.78% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4831850 87.67% 87.67% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 679365 12.33% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 482 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5507130 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3369225418 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5511701 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3368234918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1393343588 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1366825726 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1972546779 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1954242307 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 301679801 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 335428339 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 151036436 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 167784154 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2152,161 +2172,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6502 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 187776 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 66469 40.53% 40.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.17% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 149 0.09% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 95308 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 163983 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 65388 49.23% 49.23% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.45% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 149 0.11% 50.89% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 65239 49.11% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 132833 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864137851500 97.75% 97.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61127000 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 545976000 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 68164000 0.00% 97.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42142829000 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906955947500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983737 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6535 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 184475 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65083 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.20% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 93355 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 160682 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64077 49.21% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.48% 50.79% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63891 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130212 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864797723000 97.04% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61900500 0.00% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 553477500 0.03% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 85562000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56264153500 2.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1921762816500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984543 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684507 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810041 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed -system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 225 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684388 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810371 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed +system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 228 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 249 0.14% 0.14% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3603 2.09% 2.23% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 157157 91.07% 93.34% # number of callpals executed -system.cpu0.kern.callpal::rdps 6335 3.67% 97.01% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.01% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 97.02% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rti 4619 2.68% 99.70% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.22% 99.92% # number of callpals executed +system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3533 2.09% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::swpipl 153850 90.93% 93.22% # number of callpals executed +system.cpu0.kern.callpal::rdps 6345 3.75% 96.97% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::rti 4587 2.71% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 172559 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7164 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches +system.cpu0.kern.callpal::total 169199 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7137 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1347 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1342 -system.cpu0.kern.mode_good::user 1343 +system.cpu0.kern.mode_good::kernel 1346 +system.cpu0.kern.mode_good::user 1347 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.187326 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188595 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.315622 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904989354500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1966585000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.317421 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1919561135500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2201673000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3604 # number of times the context was actually changed +system.cpu0.kern.swap_context 3534 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2444 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 51472 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 15731 36.02% 36.02% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 4.41% 40.43% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 249 0.57% 41.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 25763 59.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 43668 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 15435 47.07% 47.07% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.87% 52.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 249 0.76% 53.69% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15186 46.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 32795 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874760769500 98.33% 98.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 538410500 0.03% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 114320500 0.01% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31218212000 1.64% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1906631712500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981184 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 55164 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 17245 36.53% 36.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 4.08% 40.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 27750 58.79% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 47204 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16874 47.30% 47.30% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.40% 52.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 284 0.80% 53.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16590 46.51% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 35673 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874997277000 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 538569500 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 135298500 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45735704500 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1921406849500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978487 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.589450 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.751008 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed -system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed -system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 101 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.597838 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.755720 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed +system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed +system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 98 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 149 0.33% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 911 2.02% 2.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.36% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 2.38% # number of callpals executed -system.cpu1.kern.callpal::swpipl 38628 85.51% 87.88% # number of callpals executed -system.cpu1.kern.callpal::rdps 2426 5.37% 93.25% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2865 6.34% 99.61% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.29% 99.90% # number of callpals executed +system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1056 2.16% 2.55% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed +system.cpu1.kern.callpal::swpipl 42024 86.04% 88.61% # number of callpals executed +system.cpu1.kern.callpal::rdps 2414 4.94% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.56% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::rti 2970 6.08% 99.65% # number of callpals executed +system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 45176 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1151 # number of protection mode switches -system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2341 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 568 -system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 173 -system.cpu1.kern.mode_switch_good::kernel 0.493484 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 48843 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1253 # number of protection mode switches +system.cpu1.kern.mode_switch::user 392 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2414 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 600 +system.cpu1.kern.mode_good::user 392 +system.cpu1.kern.mode_good::idle 208 +system.cpu1.kern.mode_switch_good::kernel 0.478851 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.073900 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.292256 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3648998000 0.19% 0.19% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 689386500 0.04% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1901995153000 99.77% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 912 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.086164 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.295639 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4354098000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 702561000 0.04% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1916032066000 99.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1057 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |