diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3856 |
1 files changed, 1933 insertions, 1923 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 1b3e8deca..1db8d7737 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.924156 # Number of seconds simulated -sim_ticks 1924156135000 # Number of ticks simulated -final_tick 1924156135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.929078 # Number of seconds simulated +sim_ticks 1929077876500 # Number of ticks simulated +final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131013 # Simulator instruction rate (inst/s) -host_op_rate 131013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4442767791 # Simulator tick rate (ticks/s) -host_mem_usage 340636 # Number of bytes of host memory used -host_seconds 433.10 # Real time elapsed on the host -sim_insts 56741431 # Number of instructions simulated -sim_ops 56741431 # Number of ops (including micro ops) simulated +host_inst_rate 158135 # Simulator instruction rate (inst/s) +host_op_rate 158134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5371969736 # Simulator tick rate (ticks/s) +host_mem_usage 339544 # Number of bytes of host memory used +host_seconds 359.10 # Real time elapsed on the host +sim_insts 56786201 # Number of instructions simulated +sim_ops 56786201 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 858624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24610432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 114304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 675520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 856320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24603328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 123072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 684608 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26259840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 858624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 114304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 972928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7862976 # Number of bytes written to this memory -system.physmem.bytes_written::total 7862976 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1786 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10555 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26268288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 856320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 979392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7871488 # Number of bytes written to this memory +system.physmem.bytes_written::total 7871488 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13380 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384427 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10697 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410310 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122859 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122859 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 446234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12790247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 351073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13647458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 446234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 505639 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4086454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4086454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4086454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 446234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12790247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 351073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17733912 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410310 # Number of read requests accepted -system.physmem.writeReqs 122859 # Number of write requests accepted -system.physmem.readBursts 410310 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122859 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26253184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 7861568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26259840 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7862976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122992 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122992 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 443901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12753932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 354889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13617018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 443901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 507700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4080441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4080441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4080441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 443901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12753932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 354889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17697459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410442 # Number of read requests accepted +system.physmem.writeReqs 122992 # Number of write requests accepted +system.physmem.readBursts 410442 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122992 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue +system.physmem.bytesWritten 7869440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26268288 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7871488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26222 # Per bank write bursts -system.physmem.perBankRdBursts::1 25818 # Per bank write bursts -system.physmem.perBankRdBursts::2 25998 # Per bank write bursts -system.physmem.perBankRdBursts::3 25425 # Per bank write bursts -system.physmem.perBankRdBursts::4 25236 # Per bank write bursts -system.physmem.perBankRdBursts::5 25660 # Per bank write bursts -system.physmem.perBankRdBursts::6 25903 # Per bank write bursts -system.physmem.perBankRdBursts::7 25509 # Per bank write bursts -system.physmem.perBankRdBursts::8 25730 # Per bank write bursts -system.physmem.perBankRdBursts::9 25899 # Per bank write bursts -system.physmem.perBankRdBursts::10 25820 # Per bank write bursts -system.physmem.perBankRdBursts::11 25243 # Per bank write bursts -system.physmem.perBankRdBursts::12 25580 # Per bank write bursts -system.physmem.perBankRdBursts::13 25319 # Per bank write bursts -system.physmem.perBankRdBursts::14 25297 # Per bank write bursts -system.physmem.perBankRdBursts::15 25547 # Per bank write bursts -system.physmem.perBankWrBursts::0 8465 # Per bank write bursts -system.physmem.perBankWrBursts::1 7798 # Per bank write bursts -system.physmem.perBankWrBursts::2 8098 # Per bank write bursts -system.physmem.perBankWrBursts::3 7477 # Per bank write bursts -system.physmem.perBankWrBursts::4 7191 # Per bank write bursts -system.physmem.perBankWrBursts::5 7211 # Per bank write bursts -system.physmem.perBankWrBursts::6 7415 # Per bank write bursts -system.physmem.perBankWrBursts::7 7062 # Per bank write bursts -system.physmem.perBankWrBursts::8 7370 # Per bank write bursts -system.physmem.perBankWrBursts::9 7621 # Per bank write bursts -system.physmem.perBankWrBursts::10 7713 # Per bank write bursts -system.physmem.perBankWrBursts::11 7334 # Per bank write bursts -system.physmem.perBankWrBursts::12 7954 # Per bank write bursts -system.physmem.perBankWrBursts::13 8039 # Per bank write bursts -system.physmem.perBankWrBursts::14 8051 # Per bank write bursts -system.physmem.perBankWrBursts::15 8038 # Per bank write bursts +system.physmem.perBankRdBursts::0 26358 # Per bank write bursts +system.physmem.perBankRdBursts::1 25853 # Per bank write bursts +system.physmem.perBankRdBursts::2 25982 # Per bank write bursts +system.physmem.perBankRdBursts::3 25455 # Per bank write bursts +system.physmem.perBankRdBursts::4 25391 # Per bank write bursts +system.physmem.perBankRdBursts::5 25779 # Per bank write bursts +system.physmem.perBankRdBursts::6 25718 # Per bank write bursts +system.physmem.perBankRdBursts::7 25362 # Per bank write bursts +system.physmem.perBankRdBursts::8 25502 # Per bank write bursts +system.physmem.perBankRdBursts::9 25880 # Per bank write bursts +system.physmem.perBankRdBursts::10 25847 # Per bank write bursts +system.physmem.perBankRdBursts::11 25125 # Per bank write bursts +system.physmem.perBankRdBursts::12 25573 # Per bank write bursts +system.physmem.perBankRdBursts::13 25368 # Per bank write bursts +system.physmem.perBankRdBursts::14 25415 # Per bank write bursts +system.physmem.perBankRdBursts::15 25720 # Per bank write bursts +system.physmem.perBankWrBursts::0 8608 # Per bank write bursts +system.physmem.perBankWrBursts::1 7821 # Per bank write bursts +system.physmem.perBankWrBursts::2 8027 # Per bank write bursts +system.physmem.perBankWrBursts::3 7496 # Per bank write bursts +system.physmem.perBankWrBursts::4 7316 # Per bank write bursts +system.physmem.perBankWrBursts::5 7320 # Per bank write bursts +system.physmem.perBankWrBursts::6 7241 # Per bank write bursts +system.physmem.perBankWrBursts::7 6937 # Per bank write bursts +system.physmem.perBankWrBursts::8 7156 # Per bank write bursts +system.physmem.perBankWrBursts::9 7588 # Per bank write bursts +system.physmem.perBankWrBursts::10 7741 # Per bank write bursts +system.physmem.perBankWrBursts::11 7304 # Per bank write bursts +system.physmem.perBankWrBursts::12 7945 # Per bank write bursts +system.physmem.perBankWrBursts::13 8097 # Per bank write bursts +system.physmem.perBankWrBursts::14 8174 # Per bank write bursts +system.physmem.perBankWrBursts::15 8189 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 1924155087500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1929076824500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410310 # Read request sizes (log2) +system.physmem.readPktSize::6 410442 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122859 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122992 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -158,187 +158,194 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65042 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 524.503429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 321.000815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 410.854297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14739 22.66% 22.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11347 17.45% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5326 8.19% 48.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2916 4.48% 52.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2591 3.98% 56.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1650 2.54% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3760 5.78% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1191 1.83% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21522 33.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65042 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5512 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.419267 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2843.464031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5509 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 522.399241 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.882184 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.899985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14976 22.92% 22.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11360 17.39% 40.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5432 8.31% 48.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2850 4.36% 52.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2530 3.87% 56.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1671 2.56% 59.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3857 5.90% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1188 1.82% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21470 32.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65334 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5522 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.304962 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2840.771031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5519 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5512 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5512 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.285377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.129455 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.189692 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4905 88.99% 88.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 46 0.83% 89.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 19 0.34% 90.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 46 0.83% 91.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 202 3.66% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 8 0.15% 94.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 9 0.16% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 26 0.47% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 191 3.47% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.09% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 3 0.05% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.16% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.09% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.09% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 8 0.15% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5512 # Writes before turning the bus around for reads -system.physmem.totQLat 4435069250 # Total ticks spent queuing -system.physmem.totMemAccLat 12126431750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10811.81 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5522 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5522 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.267294 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.111227 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.252131 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4917 89.04% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 44 0.80% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 22 0.40% 90.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 38 0.69% 90.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 207 3.75% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.11% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 12 0.22% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 27 0.49% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 186 3.37% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.11% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 8 0.14% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.14% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 6 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.07% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5522 # Writes before turning the bus around for reads +system.physmem.totQLat 4416821750 # Total ticks spent queuing +system.physmem.totMemAccLat 12110471750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10764.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29561.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29514.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing -system.physmem.readRowHits 369385 # Number of row buffer hits during reads -system.physmem.writeRowHits 98616 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.27 # Row buffer hit rate for writes -system.physmem.avgGap 3608902.78 # Average gap between requests -system.physmem.pageHitRate 87.79 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245503440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133955250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1605013800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 393446160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125676364320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63335469060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1098934930500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1290324682530 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.593273 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1827969159500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64251720000 # Time in different power states +system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.77 # Average write queue length when enqueuing +system.physmem.readRowHits 369361 # Number of row buffer hits during reads +system.physmem.writeRowHits 98593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.16 # Row buffer hit rate for writes +system.physmem.avgGap 3616336.46 # Average gap between requests +system.physmem.pageHitRate 87.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 246047760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134252250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1606004400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 393763680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63271865610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101943260750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1293592968690 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.576874 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832974418500 # Time in different power states +system.physmem_0.memoryStateTime::REF 64416040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31933066750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31684384000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246214080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134343000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1594593000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402537600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125676364320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62736550965 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1099460297250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1290250900215 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.554927 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1828845452000 # Time in different power states -system.physmem_1.memoryStateTime::REF 64251720000 # Time in different power states +system.physmem_1.actEnergy 247877280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135250500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1594554000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 403017120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63221156415 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101987750750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1293587380305 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.573972 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1833051648500 # Time in different power states +system.physmem_1.memoryStateTime::REF 64416040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31056774250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31607167750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 15943421 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13949758 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 305064 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10079074 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5240379 # Number of BTB hits +system.cpu0.branchPred.lookups 17100345 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14625316 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 474432 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10759421 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4832502 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.992663 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 792227 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17177 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 44.914145 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 945329 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 34555 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5020643 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 507910 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4512733 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 209375 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9007287 # DTB read hits -system.cpu0.dtb.read_misses 30074 # DTB read misses -system.cpu0.dtb.read_acv 538 # DTB read access violations -system.cpu0.dtb.read_accesses 622567 # DTB read accesses -system.cpu0.dtb.write_hits 5740520 # DTB write hits -system.cpu0.dtb.write_misses 6136 # DTB write misses -system.cpu0.dtb.write_acv 351 # DTB write access violations -system.cpu0.dtb.write_accesses 205436 # DTB write accesses -system.cpu0.dtb.data_hits 14747807 # DTB hits -system.cpu0.dtb.data_misses 36210 # DTB misses -system.cpu0.dtb.data_acv 889 # DTB access violations -system.cpu0.dtb.data_accesses 828003 # DTB accesses -system.cpu0.itb.fetch_hits 1373369 # ITB hits -system.cpu0.itb.fetch_misses 18540 # ITB misses -system.cpu0.itb.fetch_acv 561 # ITB acv -system.cpu0.itb.fetch_accesses 1391909 # ITB accesses +system.cpu0.dtb.read_hits 9634816 # DTB read hits +system.cpu0.dtb.read_misses 36704 # DTB read misses +system.cpu0.dtb.read_acv 586 # DTB read access violations +system.cpu0.dtb.read_accesses 618265 # DTB read accesses +system.cpu0.dtb.write_hits 5807101 # DTB write hits +system.cpu0.dtb.write_misses 8981 # DTB write misses +system.cpu0.dtb.write_acv 421 # DTB write access violations +system.cpu0.dtb.write_accesses 195454 # DTB write accesses +system.cpu0.dtb.data_hits 15441917 # DTB hits +system.cpu0.dtb.data_misses 45685 # DTB misses +system.cpu0.dtb.data_acv 1007 # DTB access violations +system.cpu0.dtb.data_accesses 813719 # DTB accesses +system.cpu0.itb.fetch_hits 1375653 # ITB hits +system.cpu0.itb.fetch_misses 7396 # ITB misses +system.cpu0.itb.fetch_acv 601 # ITB acv +system.cpu0.itb.fetch_accesses 1383049 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,596 +358,600 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 146208045 # number of cpu cycles simulated +system.cpu0.numCycles 146500468 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26065681 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69138767 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 15943421 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6032606 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 111931288 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1030760 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 960 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 863166 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 466353 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7979260 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223234 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 139872418 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.494299 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.727987 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26225748 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 74880065 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 17100345 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6285741 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 112740313 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1369370 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 398 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 147220 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 425638 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 504 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8642043 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 322305 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 140254918 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.533885 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.795707 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 126942613 90.76% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 822727 0.59% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1793626 1.28% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 758856 0.54% 93.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2553230 1.83% 94.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559004 0.40% 95.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 640050 0.46% 95.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 814516 0.58% 96.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4987796 3.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 126345960 90.08% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 903115 0.64% 90.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1906918 1.36% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 803345 0.57% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2649453 1.89% 94.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 589849 0.42% 94.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 700559 0.50% 95.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 843084 0.60% 96.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5512635 3.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 139872418 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.109046 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472879 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21051176 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108291493 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8312277 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1736520 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 480951 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 505721 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 34877 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 60486220 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 106478 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 480951 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21868372 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 77772833 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19641346 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9147803 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10961111 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58426169 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 200234 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2003921 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 229197 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7028864 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39061354 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71018610 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 70882139 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 127236 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34481529 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4579825 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1435923 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 207898 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12319734 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9087403 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6005193 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1334507 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 982358 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52110504 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1852436 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51364410 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 50265 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6320051 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2764098 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1275155 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 139872418 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.367223 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.083437 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 140254918 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.116726 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.511125 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20974212 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 107876486 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8907132 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1841497 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 655590 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 626155 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29675 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 64967024 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 87739 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 655590 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21855511 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 78567360 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18275925 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9798485 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11102045 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 62456562 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 201631 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2042440 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 306402 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7083961 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 42144620 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 75447660 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 75312247 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 126226 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34366321 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7778299 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1457881 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 236313 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12541674 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10026235 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6171298 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1512964 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 977849 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 55240015 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1897630 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 53565100 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 74212 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9657224 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4199823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1322202 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 140254918 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.381912 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.107336 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 118742134 84.89% 84.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9166235 6.55% 91.45% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3802026 2.72% 94.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2678681 1.92% 96.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2780722 1.99% 98.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1354022 0.97% 99.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 885059 0.63% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 353584 0.25% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109955 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 118450817 84.45% 84.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9324559 6.65% 91.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3896910 2.78% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2805800 2.00% 95.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2901850 2.07% 97.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1433856 1.02% 98.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 954902 0.68% 99.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 366563 0.26% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 119661 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 139872418 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 140254918 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 178057 18.55% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 457973 47.71% 66.26% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 323912 33.74% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 172960 16.73% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 530801 51.33% 68.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 330287 31.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3341 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35317882 68.76% 68.77% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56025 0.11% 68.88% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.88% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 27459 0.05% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1664 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9346041 18.20% 87.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5809377 11.31% 98.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 802621 1.56% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3306 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36704403 68.52% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56318 0.11% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 27375 0.05% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 10076531 18.81% 87.50% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5896825 11.01% 98.51% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 798690 1.49% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51364410 # Type of FU issued -system.cpu0.iq.rate 0.351310 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 959944 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018689 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 243048711 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60036028 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50017442 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 562736 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 263720 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 258274 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52017534 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 303479 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 574771 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 53565100 # Type of FU issued +system.cpu0.iq.rate 0.365631 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1034048 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019305 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 247915569 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 66533789 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51792941 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 577809 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 279350 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 262536 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 54284218 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 311624 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 608466 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1026959 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3812 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17061 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 487007 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2001818 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4069 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18629 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 679305 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18708 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 390954 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18387 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 376944 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 480951 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 74383875 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 944737 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57300574 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 113056 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9087403 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6005193 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1637090 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39248 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 704660 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17061 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 148957 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 344315 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 493272 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50873166 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9059669 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 491244 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 655590 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 75078561 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 955285 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 60714699 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 160012 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10026235 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6171298 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1682472 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 42874 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 711273 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18629 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 185912 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 515422 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 701334 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52870028 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9698038 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 695072 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3337634 # number of nop insts executed -system.cpu0.iew.exec_refs 14819622 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8093106 # Number of branches executed -system.cpu0.iew.exec_stores 5759953 # Number of stores executed -system.cpu0.iew.exec_rate 0.347951 # Inst execution rate -system.cpu0.iew.wb_sent 50383521 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50275716 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25952077 # num instructions producing a value -system.cpu0.iew.wb_consumers 35940166 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.343864 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.722091 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 6643709 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 577281 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 452311 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 138699255 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.364540 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.252346 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3577054 # number of nop insts executed +system.cpu0.iew.exec_refs 15531241 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8401878 # Number of branches executed +system.cpu0.iew.exec_stores 5833203 # Number of stores executed +system.cpu0.iew.exec_rate 0.360886 # Inst execution rate +system.cpu0.iew.wb_sent 52244753 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 52055477 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26703720 # num instructions producing a value +system.cpu0.iew.wb_consumers 36905470 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.355326 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723571 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10154720 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 575428 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 626255 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 138489248 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.363854 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.249176 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 120842585 87.13% 87.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7068214 5.10% 92.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3896866 2.81% 95.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2026273 1.46% 96.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1580895 1.14% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 566091 0.41% 98.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 426311 0.31% 98.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 427447 0.31% 98.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1864573 1.34% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 120648787 87.12% 87.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7115506 5.14% 92.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3823437 2.76% 95.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2034446 1.47% 96.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1589267 1.15% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 580000 0.42% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 430694 0.31% 98.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 453916 0.33% 98.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1813195 1.31% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 138699255 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50561379 # Number of instructions committed -system.cpu0.commit.committedOps 50561379 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 138489248 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50389922 # Number of instructions committed +system.cpu0.commit.committedOps 50389922 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13578630 # Number of memory references committed -system.cpu0.commit.loads 8060444 # Number of loads committed -system.cpu0.commit.membars 196368 # Number of memory barriers committed -system.cpu0.commit.branches 7652854 # Number of branches committed -system.cpu0.commit.fp_insts 255352 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46813547 # Number of committed integer instructions. -system.cpu0.commit.function_calls 647795 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2921820 5.78% 5.78% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32972422 65.21% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54875 0.11% 71.10% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.10% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 26997 0.05% 71.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1664 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8256812 16.33% 87.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5524169 10.93% 98.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 802620 1.59% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13516410 # Number of memory references committed +system.cpu0.commit.loads 8024417 # Number of loads committed +system.cpu0.commit.membars 195679 # Number of memory barriers committed +system.cpu0.commit.branches 7630866 # Number of branches committed +system.cpu0.commit.fp_insts 253714 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46654336 # Number of committed integer instructions. +system.cpu0.commit.function_calls 644656 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2912807 5.78% 5.78% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32876835 65.24% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54961 0.11% 71.13% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.13% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 26901 0.05% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1652 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8220096 16.31% 87.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5497981 10.91% 98.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 798689 1.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 50561379 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1864573 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 193850877 # The number of ROB reads -system.cpu0.rob.rob_writes 115577492 # The number of ROB writes -system.cpu0.timesIdled 518122 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6335627 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3701455446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47642888 # Number of Instructions Simulated -system.cpu0.committedOps 47642888 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 3.068833 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.068833 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.325857 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.325857 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66867100 # number of integer regfile reads -system.cpu0.int_regfile_writes 36418674 # number of integer regfile writes -system.cpu0.fp_regfile_reads 126247 # number of floating regfile reads -system.cpu0.fp_regfile_writes 127860 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1687235 # number of misc regfile reads -system.cpu0.misc_regfile_writes 805033 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1264949 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.087207 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10332814 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1265389 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.165721 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 50389922 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1813195 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 197034230 # The number of ROB reads +system.cpu0.rob.rob_writes 122856265 # The number of ROB writes +system.cpu0.timesIdled 490676 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6245550 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3710936476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47480420 # Number of Instructions Simulated +system.cpu0.committedOps 47480420 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.085492 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.085492 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.324097 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.324097 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 69229174 # number of integer regfile reads +system.cpu0.int_regfile_writes 37925510 # number of integer regfile writes +system.cpu0.fp_regfile_reads 125098 # number of floating regfile reads +system.cpu0.fp_regfile_writes 133204 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1692059 # number of misc regfile reads +system.cpu0.misc_regfile_writes 801866 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1263704 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.064166 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10905904 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1264137 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.627154 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.087207 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988452 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988452 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 440 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.859375 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 55743901 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 55743901 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6363552 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6363552 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3619661 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3619661 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160076 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160076 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184973 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 184973 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9983213 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9983213 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9983213 # number of overall hits -system.cpu0.dcache.overall_hits::total 9983213 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1569683 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1569683 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1696149 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1696149 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20607 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20607 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2893 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2893 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3265832 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3265832 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3265832 # number of overall misses -system.cpu0.dcache.overall_misses::total 3265832 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54492082500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54492082500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110535541459 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 110535541459 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385765500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 385765500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44605000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44605000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 165027623959 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 165027623959 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 165027623959 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 165027623959 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7933235 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7933235 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5315810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5315810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 180683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187866 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187866 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13249045 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13249045 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13249045 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13249045 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197862 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197862 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.319076 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.319076 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114051 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114051 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015399 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015399 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246496 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.246496 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.246496 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.246496 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34715.342206 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34715.342206 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65168.532634 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65168.532634 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18720.119377 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18720.119377 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15418.250951 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15418.250951 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50531.571728 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50531.571728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50531.571728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50531.571728 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6758088 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 13420 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 113551 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 96 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.515883 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 139.791667 # average number of cycles each access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.064166 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988407 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988407 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 433 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.845703 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 58069444 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 58069444 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6953524 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6953524 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3586613 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3586613 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 178977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 178977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184325 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 184325 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10540137 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10540137 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10540137 # number of overall hits +system.cpu0.dcache.overall_hits::total 10540137 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1569058 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1569058 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1703592 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1703592 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20226 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20226 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2959 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2959 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3272650 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3272650 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3272650 # number of overall misses +system.cpu0.dcache.overall_misses::total 3272650 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54620758000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54620758000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110116261626 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 110116261626 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 348212000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 348212000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46063500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46063500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 164737019626 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 164737019626 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 164737019626 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 164737019626 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8522582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8522582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5290205 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5290205 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 199203 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 199203 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187284 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187284 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13812787 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13812787 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13812787 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13812787 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184106 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.184106 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322028 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.322028 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101535 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101535 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015800 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015800 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236929 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.236929 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236929 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.236929 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34811.178427 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34811.178427 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64637.695895 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64637.695895 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17216.058539 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17216.058539 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15567.252450 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15567.252450 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50337.500077 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6721817 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 17671 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 111036 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 742386 # number of writebacks -system.cpu0.dcache.writebacks::total 742386 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 562218 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 562218 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1439926 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1439926 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4884 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4884 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2002144 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2002144 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2002144 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2002144 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007465 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1007465 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256223 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256223 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15723 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15723 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2893 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2893 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263688 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1263688 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263688 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1263688 # number of overall MSHR misses +system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks +system.cpu0.dcache.writebacks::total 741086 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 559859 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449235 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1449235 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5567 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5567 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2009094 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2009094 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2009094 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2009094 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1009199 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1009199 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254357 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 254357 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14659 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14659 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2959 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2959 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263556 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1263556 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263556 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1263556 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10093 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10093 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17124 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17124 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43361344000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43361344000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17653250388 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17653250388 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186143500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186143500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41712000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41712000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61014594388 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61014594388 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61014594388 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 61014594388 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1559676000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1559676000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293857500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293857500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3853533500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3853533500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126993 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126993 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048200 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048200 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087020 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087020 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015399 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015399 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095380 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095380 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095380 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095380 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43040.050027 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43040.050027 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68897.992717 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68897.992717 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.930230 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.930230 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14418.250951 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14418.250951 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48282.957809 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48282.957809 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48282.957809 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48282.957809 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221828.473901 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221828.473901 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227272.119291 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227272.119291 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225036.994861 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225036.994861 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10105 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10105 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17136 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17136 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43480023500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43480023500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17474692057 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17474692057 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 173733500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 173733500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 43104500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 43104500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60954715557 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 60954715557 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2296787000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2296787000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3855733000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3855733000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.073588 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.073588 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015800 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015800 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091477 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091477 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43083.696575 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43083.696575 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68701.439540 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68701.439540 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11851.661096 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11851.661096 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 894689 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.080310 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7039625 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 895201 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.863737 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42372449500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.080310 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992344 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992344 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 911237 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 911749 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.418764 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42368821500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.249711 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992675 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 196 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8874714 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8874714 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7039625 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7039625 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7039625 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7039625 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7039625 # number of overall hits -system.cpu0.icache.overall_hits::total 7039625 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 939633 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 939633 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 939633 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 939633 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 939633 # number of overall misses -system.cpu0.icache.overall_misses::total 939633 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14412797481 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14412797481 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14412797481 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14412797481 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14412797481 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14412797481 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7979258 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7979258 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7979258 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7979258 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7979258 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7979258 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117759 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117759 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117759 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117759 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117759 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117759 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15338.751918 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15338.751918 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15338.751918 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15338.751918 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15338.751918 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15338.751918 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 9737 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9554008 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9554008 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7675800 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7675800 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7675800 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7675800 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7675800 # number of overall hits +system.cpu0.icache.overall_hits::total 7675800 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 966240 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 966240 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 966240 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 966240 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 966240 # number of overall misses +system.cpu0.icache.overall_misses::total 966240 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14731064486 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14731064486 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14731064486 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14731064486 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14731064486 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14731064486 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8642040 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8642040 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8642040 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8642040 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8642040 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8642040 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111807 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111807 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111807 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111807 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111807 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111807 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15245.761391 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15245.761391 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15245.761391 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15245.761391 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 11439 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.784512 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 894689 # number of writebacks -system.cpu0.icache.writebacks::total 894689 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44177 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44177 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44177 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44177 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44177 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44177 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895456 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 895456 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 895456 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 895456 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 895456 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 895456 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12742984487 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12742984487 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12742984487 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12742984487 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12742984487 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12742984487 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112223 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.112223 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.112223 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14230.720981 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14230.720981 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14230.720981 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks +system.cpu0.icache.writebacks::total 911237 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54272 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54272 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54272 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54272 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54272 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 911968 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 911968 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 911968 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 911968 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 911968 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 911968 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12931897989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12931897989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12931897989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12931897989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12931897989 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12931897989 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105527 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105527 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105527 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3770405 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3287478 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 72852 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2172402 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 929208 # Number of BTB hits +system.cpu1.branchPred.lookups 4129053 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2303722 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 822541 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 42.773299 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 184259 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 5155 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 35.704872 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 211273 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8217 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1287279 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 153619 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1133660 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 37557 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2058998 # DTB read hits -system.cpu1.dtb.read_misses 11600 # DTB read misses -system.cpu1.dtb.read_acv 21 # DTB read access violations -system.cpu1.dtb.read_accesses 345698 # DTB read accesses -system.cpu1.dtb.write_hits 1317225 # DTB write hits -system.cpu1.dtb.write_misses 3094 # DTB write misses -system.cpu1.dtb.write_acv 53 # DTB write access violations -system.cpu1.dtb.write_accesses 138357 # DTB write accesses -system.cpu1.dtb.data_hits 3376223 # DTB hits -system.cpu1.dtb.data_misses 14694 # DTB misses -system.cpu1.dtb.data_acv 74 # DTB access violations -system.cpu1.dtb.data_accesses 484055 # DTB accesses -system.cpu1.itb.fetch_hits 573986 # ITB hits -system.cpu1.itb.fetch_misses 6844 # ITB misses -system.cpu1.itb.fetch_acv 105 # ITB acv -system.cpu1.itb.fetch_accesses 580830 # ITB accesses +system.cpu1.dtb.read_hits 2247369 # DTB read hits +system.cpu1.dtb.read_misses 13283 # DTB read misses +system.cpu1.dtb.read_acv 72 # DTB read access violations +system.cpu1.dtb.read_accesses 382556 # DTB read accesses +system.cpu1.dtb.write_hits 1356336 # DTB write hits +system.cpu1.dtb.write_misses 3091 # DTB write misses +system.cpu1.dtb.write_acv 71 # DTB write access violations +system.cpu1.dtb.write_accesses 152961 # DTB write accesses +system.cpu1.dtb.data_hits 3603705 # DTB hits +system.cpu1.dtb.data_misses 16374 # DTB misses +system.cpu1.dtb.data_acv 143 # DTB access violations +system.cpu1.dtb.data_accesses 535517 # DTB accesses +system.cpu1.itb.fetch_hits 615373 # ITB hits +system.cpu1.itb.fetch_misses 3011 # ITB misses +system.cpu1.itb.fetch_acv 117 # ITB acv +system.cpu1.itb.fetch_accesses 618384 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -953,568 +964,567 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16344557 # number of cpu cycles simulated +system.cpu1.numCycles 16726806 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6567420 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 14895137 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3770405 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1113467 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 8326976 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 284690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 333 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 274833 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 63331 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1681040 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 57489 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15400785 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.967167 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.371525 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6696452 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16370488 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4129053 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1187433 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 8741861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 347188 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 25893 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 58137 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 49356 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1820963 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 76422 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15745356 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.039703 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.449166 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12783684 83.01% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 166452 1.08% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 261215 1.70% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 200313 1.30% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 351067 2.28% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 133990 0.87% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 151147 0.98% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 199120 1.29% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1153797 7.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12876670 81.78% 81.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 185062 1.18% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 297924 1.89% 84.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 209767 1.33% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 372753 2.37% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 143050 0.91% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 159866 1.02% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 207293 1.32% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1292971 8.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15400785 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.230683 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.911321 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5395420 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7755332 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1888719 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 226049 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 135264 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 116204 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7167 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12211095 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22842 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 135264 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5551383 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 663921 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5888186 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1958901 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1203128 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11612321 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4312 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 84745 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 20732 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 660077 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 7621170 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13919150 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13857621 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 55424 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6464282 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1156880 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 465120 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 44099 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2006629 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2105779 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1396456 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 250989 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 150424 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 10250493 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 528025 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10010931 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 21465 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1679970 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 786543 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 387236 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15400785 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.650027 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.374650 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15745356 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.246852 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.978698 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5498623 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7777976 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2045729 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 256320 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 166707 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 143442 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7016 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 13354105 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22028 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 166707 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5670233 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 826473 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5769862 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2131801 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1180278 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12651091 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3750 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 88341 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 32960 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 615086 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 8374295 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 15046844 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 14984377 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 56291 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6609856 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1764431 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 476570 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 48769 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2080322 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2346654 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1454994 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 292964 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 152733 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11085695 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 541496 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10671183 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 25309 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2321405 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1075261 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 398456 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15745356 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.677735 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.406788 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11244282 73.01% 73.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1815288 11.79% 84.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 776099 5.04% 89.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 545502 3.54% 93.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 489702 3.18% 96.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 259974 1.69% 98.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 169251 1.10% 99.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 72741 0.47% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 27946 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11382155 72.29% 72.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1870956 11.88% 84.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 802175 5.09% 89.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 575742 3.66% 92.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 534921 3.40% 96.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 285738 1.81% 98.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 185455 1.18% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 78165 0.50% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 30049 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15400785 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15745356 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 26802 9.62% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 149738 53.73% 63.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 102168 36.66% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27488 9.05% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 170713 56.19% 65.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 105586 34.76% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3957 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6209301 62.03% 62.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16861 0.17% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11959 0.12% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1978 0.02% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2148593 21.46% 83.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1341864 13.40% 97.24% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 276418 2.76% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3991 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6611083 61.95% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16524 0.15% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 12068 0.11% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1990 0.02% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2360403 22.12% 84.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1384355 12.97% 97.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 280769 2.63% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10010931 # Type of FU issued -system.cpu1.iq.rate 0.612493 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 278708 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027840 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 35509985 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 12361464 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9636562 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 212834 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 101438 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 98868 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10172012 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 113670 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 100974 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10671183 # Type of FU issued +system.cpu1.iq.rate 0.637969 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 303787 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 37199457 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 13849868 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10195275 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 217360 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 103372 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 100900 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10854739 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 116240 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 112250 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 300733 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 901 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4546 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 138575 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 494389 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1075 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4794 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 168808 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 436 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 85477 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 442 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 89761 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 135264 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 341224 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 281245 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 11333478 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 30763 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2105779 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1396456 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 478482 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4958 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 275268 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4546 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 33466 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 102178 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 135644 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9885056 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2078095 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 125874 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 166707 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 440216 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 341566 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 12247032 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 53191 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2346654 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1454994 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 491166 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 5461 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 335179 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4794 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 42007 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 137108 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 179115 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10495256 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2269179 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 175926 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 554960 # number of nop insts executed -system.cpu1.iew.exec_refs 3404439 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1465257 # Number of branches executed -system.cpu1.iew.exec_stores 1326344 # Number of stores executed -system.cpu1.iew.exec_rate 0.604792 # Inst execution rate -system.cpu1.iew.wb_sent 9770196 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9735430 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4636977 # num instructions producing a value -system.cpu1.iew.wb_consumers 6583946 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.595637 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.704285 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1707241 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 140789 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 123833 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 15089302 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.633097 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.610231 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 619841 # number of nop insts executed +system.cpu1.iew.exec_refs 3634984 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1567515 # Number of branches executed +system.cpu1.iew.exec_stores 1365805 # Number of stores executed +system.cpu1.iew.exec_rate 0.627451 # Inst execution rate +system.cpu1.iew.wb_sent 10344393 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 10296175 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4904906 # num instructions producing a value +system.cpu1.iew.wb_consumers 6922372 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.615549 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708559 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2337439 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 143040 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 155210 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 15327667 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.637432 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.616488 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11642359 77.16% 77.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1582874 10.49% 87.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 578528 3.83% 91.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 347459 2.30% 93.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 270616 1.79% 95.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 111368 0.74% 96.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 102382 0.68% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 112638 0.75% 97.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 341078 2.26% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11807980 77.04% 77.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1622081 10.58% 87.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 578152 3.77% 91.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 357481 2.33% 93.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 274261 1.79% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 117588 0.77% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 104376 0.68% 96.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 117710 0.77% 97.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 348038 2.27% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 15089302 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9552993 # Number of instructions committed -system.cpu1.commit.committedOps 9552993 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 15327667 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9770342 # Number of instructions committed +system.cpu1.commit.committedOps 9770342 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3062927 # Number of memory references committed -system.cpu1.commit.loads 1805046 # Number of loads committed -system.cpu1.commit.membars 44912 # Number of memory barriers committed -system.cpu1.commit.branches 1363215 # Number of branches committed -system.cpu1.commit.fp_insts 97092 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8861525 # Number of committed integer instructions. -system.cpu1.commit.function_calls 149395 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 458406 4.80% 4.80% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5679268 59.45% 64.25% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16577 0.17% 64.42% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 11953 0.13% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1978 0.02% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1849958 19.37% 83.93% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1258435 13.17% 97.11% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 276418 2.89% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3138451 # Number of memory references committed +system.cpu1.commit.loads 1852265 # Number of loads committed +system.cpu1.commit.membars 45725 # Number of memory barriers committed +system.cpu1.commit.branches 1397481 # Number of branches committed +system.cpu1.commit.fp_insts 99132 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9064844 # Number of committed integer instructions. +system.cpu1.commit.function_calls 152839 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 468541 4.80% 4.80% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5805964 59.42% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16275 0.17% 64.39% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 12061 0.12% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1990 0.02% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1897990 19.43% 83.96% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1286752 13.17% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 280769 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 9552993 # Class of committed instruction -system.cpu1.commit.bw_lim_events 341078 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 25912274 # The number of ROB reads -system.cpu1.rob.rob_writes 22828201 # The number of ROB writes -system.cpu1.timesIdled 132318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 943772 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3831967714 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9098543 # Number of Instructions Simulated -system.cpu1.committedOps 9098543 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.796393 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.796393 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556671 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556671 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12770865 # number of integer regfile reads -system.cpu1.int_regfile_writes 6910748 # number of integer regfile writes -system.cpu1.fp_regfile_reads 54739 # number of floating regfile reads -system.cpu1.fp_regfile_writes 53934 # number of floating regfile writes -system.cpu1.misc_regfile_reads 528553 # number of misc regfile reads -system.cpu1.misc_regfile_writes 224621 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 116660 # number of replacements -system.cpu1.dcache.tags.tagsinuse 487.079416 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2668588 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 117172 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 22.774963 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048837209000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.079416 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951327 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.951327 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 9770342 # Class of committed instruction +system.cpu1.commit.bw_lim_events 348038 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 26989101 # The number of ROB reads +system.cpu1.rob.rob_writes 24630830 # The number of ROB writes +system.cpu1.timesIdled 131471 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 981450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3841428948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9305781 # Number of Instructions Simulated +system.cpu1.committedOps 9305781 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.797464 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.797464 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556339 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556339 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13488576 # number of integer regfile reads +system.cpu1.int_regfile_writes 7349661 # number of integer regfile writes +system.cpu1.fp_regfile_reads 55714 # number of floating regfile reads +system.cpu1.fp_regfile_writes 55051 # number of floating regfile writes +system.cpu1.misc_regfile_reads 538402 # number of misc regfile reads +system.cpu1.misc_regfile_writes 228232 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 120114 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.559727 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2854712 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 120626 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.665810 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 62007957000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.559727 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950312 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.950312 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12701896 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12701896 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1640446 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1640446 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 950506 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 950506 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 34609 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 34609 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32422 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 32422 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2590952 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2590952 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2590952 # number of overall hits -system.cpu1.dcache.overall_hits::total 2590952 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 211694 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 211694 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 265779 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 265779 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5362 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5362 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3043 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3043 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 477473 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 477473 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 477473 # number of overall misses -system.cpu1.dcache.overall_misses::total 477473 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2807776500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2807776500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12432535778 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12432535778 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 52442500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 52442500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 46465500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 46465500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15240312278 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15240312278 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15240312278 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15240312278 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1852140 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1852140 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1216285 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1216285 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39971 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 39971 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35465 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35465 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3068425 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3068425 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3068425 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3068425 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114297 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.114297 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218517 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.218517 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134147 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134147 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085803 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085803 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.155608 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.155608 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.155608 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.155608 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13263.373076 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13263.373076 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46777.720505 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 46777.720505 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9780.399105 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9780.399105 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15269.635228 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15269.635228 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31918.689178 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 31918.689178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31918.689178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 31918.689178 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 748281 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 2150 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 22290 # number of cycles access was blocked +system.cpu1.dcache.tags.tag_accesses 13510694 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 13510694 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1801260 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1801260 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 972413 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 972413 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 37246 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 37246 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 33039 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 33039 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2773673 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2773673 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2773673 # number of overall hits +system.cpu1.dcache.overall_hits::total 2773673 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 221542 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 221542 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 271468 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 271468 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5109 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5109 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3089 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3089 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 493010 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 493010 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 493010 # number of overall misses +system.cpu1.dcache.overall_misses::total 493010 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2936746000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2936746000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12570320655 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12570320655 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51167000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 51167000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47352500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 47352500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15507066655 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15507066655 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15507066655 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15507066655 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2022802 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2022802 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1243881 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1243881 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 42355 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 42355 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 36128 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 36128 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3266683 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3266683 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3266683 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3266683 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109522 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.109522 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218243 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.218243 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120623 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120623 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085502 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085502 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.150921 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.150921 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.150921 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.150921 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13255.933412 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13255.933412 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46304.981269 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46304.981269 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10015.071443 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10015.071443 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15329.394626 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15329.394626 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 31453.858248 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 759613 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1583 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 22564 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.570256 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 179.166667 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 77506 # number of writebacks -system.cpu1.dcache.writebacks::total 77506 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 130194 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 130194 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 220941 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 220941 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 639 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 639 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 351135 # 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number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 126338 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 126338 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 126338 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 126338 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks +system.cpu1.dcache.writebacks::total 79554 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 136401 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 226329 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 226329 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 689 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 689 # 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number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1028731500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1028731500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2065280441 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2065280441 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40973500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40973500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43423500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43423500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3094011941 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3094011941 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3094011941 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3094011941 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32188500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32188500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 693701000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 693701000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 725889500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 725889500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044003 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044003 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036865 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036865 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.118161 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.118161 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085775 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085775 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041174 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.041174 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041174 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.041174 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12622.472393 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12622.472393 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46060.940296 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46060.940296 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8675.312302 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8675.312302 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14274.654832 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14274.654832 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24489.955049 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24489.955049 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24489.955049 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24489.955049 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198694.444444 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198694.444444 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232941.907320 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232941.907320 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231175 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231175 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2990 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2990 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3152 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3152 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1075350000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1075350000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2078906462 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2078906462 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39137500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39137500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44267500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44267500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3154256462 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3154256462 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 696582500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 696582500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 728758500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 728758500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036289 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104356 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104356 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085391 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085391 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039881 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039881 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12630.225156 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12630.225156 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46055.660560 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46055.660560 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8854.638009 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8854.638009 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 236774 # number of replacements -system.cpu1.icache.tags.tagsinuse 467.367156 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1435165 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 237286 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.048250 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1897657857500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.367156 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912826 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.912826 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 244089 # number of replacements +system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 244601 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.398997 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1896682174500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 469.435893 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.916867 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.916867 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1918394 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1918394 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1435165 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1435165 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1435165 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1435165 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1435165 # number of overall hits -system.cpu1.icache.overall_hits::total 1435165 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 245875 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 245875 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 245875 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 245875 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 245875 # number of overall misses -system.cpu1.icache.overall_misses::total 245875 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3543557000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3543557000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3543557000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3543557000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3543557000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3543557000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1681040 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1681040 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1681040 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1681040 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1681040 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1681040 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146264 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.146264 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146264 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.146264 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146264 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.146264 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14412.026436 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14412.026436 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14412.026436 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14412.026436 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14412.026436 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14412.026436 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 967 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2065632 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2065632 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1565201 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1565201 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1565201 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1565201 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1565201 # number of overall hits +system.cpu1.icache.overall_hits::total 1565201 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 255762 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 255762 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 255762 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 255762 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 255762 # number of overall misses +system.cpu1.icache.overall_misses::total 255762 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3690348499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3690348499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3690348499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3690348499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3690348499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3690348499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1820963 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1820963 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1820963 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1820963 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1820963 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1820963 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.140454 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.140454 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.140454 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.140454 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.140454 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.140454 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14428.838135 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14428.838135 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14428.838135 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14428.838135 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 721 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 56 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.574468 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 236774 # number of writebacks -system.cpu1.icache.writebacks::total 236774 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8521 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8521 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8521 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8521 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8521 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8521 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 237354 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 237354 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 237354 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 237354 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 237354 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 237354 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3178535500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3178535500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3178535500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3178535500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3178535500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3178535500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.141195 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.141195 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.141195 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13391.539641 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13391.539641 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13391.539641 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks +system.cpu1.icache.writebacks::total 244089 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 11093 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 11093 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 11093 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 11093 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 11093 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244669 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 244669 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 244669 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 244669 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 244669 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 244669 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3289647499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3289647499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3289647499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3289647499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3289647499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3289647499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.134362 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.134362 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.134362 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1530,9 +1540,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7368 # Transaction distribution system.iobus.trans_dist::ReadResp 7368 # Transaction distribution -system.iobus.trans_dist::WriteReq 54623 # Transaction distribution -system.iobus.trans_dist::WriteResp 54623 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11936 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54647 # Transaction distribution +system.iobus.trans_dist::WriteResp 54647 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11984 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1541,11 +1551,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40528 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40576 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 124030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47936 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1554,43 +1564,43 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73938 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 74130 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12379500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735754 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12444500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 818500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 814000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 176000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14310000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14015000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5965001 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6047501 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 87000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215710405 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215709165 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27481000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.518954 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.551900 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1726981777000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.518954 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.032435 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.032435 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1726981964000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.551900 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.034494 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.034494 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1604,14 +1614,14 @@ system.iocache.demand_misses::tsunami.ide 175 # n system.iocache.demand_misses::total 175 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 175 # number of overall misses system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 23088383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 23088383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246547022 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5246547022 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 23088383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 23088383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 23088383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 23088383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22072883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22072883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22072883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22072883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1628,19 +1638,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 131933.617143 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 131933.617143 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126264.608731 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126264.608731 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 131933.617143 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131933.617143 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 131933.617143 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131933.617143 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126130.760000 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126130.760000 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 0 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1654,14 +1664,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 175 system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14338383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14338383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167138735 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3167138735 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 14338383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14338383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 14338383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14338383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13322883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13322883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13322883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13322883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1670,199 +1680,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81933.617143 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76221.090080 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76221.090080 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81933.617143 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81933.617143 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345132 # number of replacements -system.l2c.tags.tagsinuse 65190.773198 # Cycle average of tags in use -system.l2c.tags.total_refs 3987579 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410285 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.719047 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 11177481000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53112.873337 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5260.284322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6538.875697 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 210.626415 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 68.113427 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.810438 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.099775 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001039 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65153 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3005 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4362 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5957 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51615 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994156 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38355291 # Number of tag accesses -system.l2c.tags.data_accesses 38355291 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 819892 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 819892 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 858364 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 858364 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 165 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 273 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 438 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 47 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 77 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 148311 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 29871 # 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number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14283104501 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1490098001 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 15773202502 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1664693504 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 243245008 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1907938512 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31265371007 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 114963503 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 31380334510 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1664693504 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 45548475508 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 243245008 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1605061504 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 49061475524 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1664693504 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 45548475508 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 243245008 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1605061504 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 49061475524 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1471043500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 30151000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1501194500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2180387500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 660346500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2840734000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3651431000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 690497500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4341928500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943299 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.805278 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.898423 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.899573 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935897 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.917735 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430716 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.247506 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.406491 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013424 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.272479 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254224 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305136 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.092772 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305136 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.092772 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68903.825137 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69046.944198 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68945.534331 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68539.192399 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68930.365297 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68738.649593 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128639.037171 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150611.859338 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 130408.047773 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123796.224956 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114173.496328 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131830.356033 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114227.470162 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118387.523773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 149137.453198 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 119385.166976 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118387.523773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 149137.453198 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 119385.166976 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209320.011378 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186126.543210 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208797.650494 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215752.154959 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220821.188717 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216907.046133 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213111.159776 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219031.210191 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214028.498816 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941646 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783217 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.889069 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.871486 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.941053 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.905447 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430500 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.247793 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.406018 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013234 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273040 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.011350 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254056 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.091192 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162109 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.091192 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162109 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68985.614165 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69017.410714 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68994.909945 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68584.101382 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68937.360179 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68763.337117 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128400.151934 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150408.600081 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130199.944711 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124669.270256 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114219.328490 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129172.475281 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114267.789098 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118316.948095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 148658.099843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119350.368973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118316.948095 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 148658.099843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119350.368973 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209222.514578 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186117.283951 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208702.140970 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215773.132113 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220851.672241 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216932.722413 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213085.375817 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219066.465736 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214014.614550 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7193 # Transaction distribution -system.membus.trans_dist::ReadResp 296309 # Transaction distribution -system.membus.trans_dist::WriteReq 13071 # Transaction distribution -system.membus.trans_dist::WriteResp 13071 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122859 # Transaction distribution -system.membus.trans_dist::CleanEvict 263080 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10389 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5858 # Transaction distribution +system.membus.trans_dist::ReadResp 297247 # Transaction distribution +system.membus.trans_dist::WriteReq 13095 # Transaction distribution +system.membus.trans_dist::WriteResp 13095 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122992 # Transaction distribution +system.membus.trans_dist::CleanEvict 263076 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10346 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5952 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 122048 # Transaction distribution -system.membus.trans_dist::ReadExResp 121637 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289192 # Transaction distribution -system.membus.trans_dist::BadAddressError 76 # Transaction distribution +system.membus.trans_dist::ReadExReq 121253 # Transaction distribution +system.membus.trans_dist::ReadExResp 120834 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 290100 # Transaction distribution +system.membus.trans_dist::BadAddressError 46 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40528 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181775 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1222455 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182230 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 92 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1222898 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1305892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73938 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31464576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31538514 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1306335 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 74130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31481536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31555666 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34196754 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 11972 # Total snoops (count) -system.membus.snoop_fanout::samples 875257 # Request fanout histogram +system.membus.pkt_size::total 34213906 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12142 # Total snoops (count) +system.membus.snoop_fanout::samples 875570 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 875257 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875570 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 875257 # Request fanout histogram -system.membus.reqLayer0.occupancy 36588499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875570 # Request fanout histogram +system.membus.reqLayer0.occupancy 36438999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1355446474 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1356482971 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 101000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2176763250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2177455750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 924363 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 936113 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 5062297 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2530952 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 339931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1332 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1264 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5114760 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2557108 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 345514 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1336 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2238586 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13071 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13071 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 942766 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1131462 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825685 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10428 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5935 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16363 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301553 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301553 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1132810 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1098675 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 76 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2266679 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13095 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13095 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 943643 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1155325 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 827144 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10512 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6044 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16556 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299688 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299688 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1156637 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1102911 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 46 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2685333 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3847367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 711442 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373868 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7618010 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114552128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128359012 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30341632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12338926 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 285591698 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 462928 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2998059 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.119755 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.324954 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2735017 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3843601 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 733385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 384537 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7696540 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116675136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128186756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31277824 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12692238 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288831954 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 463427 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3024601 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.120612 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.326035 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2639295 88.03% 88.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 358495 11.96% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 268 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2660134 87.95% 87.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 364147 12.04% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 303 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 17 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2998059 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4499211916 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3024601 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4550078915 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 295885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1344759827 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1369499398 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1928238108 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1926492121 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 358125739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 368355265 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 195506142 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 200907831 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2153,170 +2163,170 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6521 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 181676 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64229 40.40% 40.40% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.49% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1930 1.21% 41.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 188 0.12% 41.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92486 58.18% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158964 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63227 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 180918 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 63985 40.38% 40.38% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.47% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1935 1.22% 41.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 191 0.12% 41.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92196 58.19% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158438 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 62993 49.19% 49.19% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1930 1.50% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63039 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128515 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866746585000 97.03% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63847000 0.00% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 578525000 0.03% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 89345000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56353429000 2.93% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1923831731000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984400 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1935 1.51% 50.81% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 191 0.15% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 62802 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128052 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1871632607000 97.04% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 66355000 0.00% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 578065000 0.03% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 91849500 0.00% 97.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56349581000 2.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1928718457500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984496 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681606 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808453 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.65% 3.65% # number of syscalls executed -system.cpu0.kern.syscall::3 16 8.33% 11.98% # number of syscalls executed -system.cpu0.kern.syscall::4 4 2.08% 14.06% # number of syscalls executed -system.cpu0.kern.syscall::6 28 14.58% 28.65% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.52% 29.17% # number of syscalls executed -system.cpu0.kern.syscall::17 8 4.17% 33.33% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.65% 36.98% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.08% 39.06% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.52% 39.58% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.56% 41.15% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.12% 44.27% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.04% 45.31% # number of syscalls executed -system.cpu0.kern.syscall::45 31 16.15% 61.46% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.56% 63.02% # number of syscalls executed -system.cpu0.kern.syscall::48 8 4.17% 67.19% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.69% 71.88% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.52% 72.40% # number of syscalls executed -system.cpu0.kern.syscall::59 6 3.12% 75.52% # number of syscalls executed -system.cpu0.kern.syscall::71 21 10.94% 86.46% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.56% 88.02% # number of syscalls executed -system.cpu0.kern.syscall::74 5 2.60% 90.62% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.52% 91.15% # number of syscalls executed -system.cpu0.kern.syscall::90 2 1.04% 92.19% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.65% 95.83% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.04% 96.88% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.04% 97.92% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.52% 98.44% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.52% 98.96% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.04% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 192 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.681179 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808215 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.68% 3.68% # number of syscalls executed +system.cpu0.kern.syscall::3 15 7.89% 11.58% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.11% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 28 14.74% 28.42% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.53% 28.95% # number of syscalls executed +system.cpu0.kern.syscall::17 8 4.21% 33.16% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.68% 36.84% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.11% 38.95% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.53% 39.47% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.58% 41.05% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.16% 44.21% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.05% 45.26% # number of syscalls executed +system.cpu0.kern.syscall::45 31 16.32% 61.58% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.58% 63.16% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.21% 67.37% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.74% 72.11% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.53% 72.63% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.63% 75.26% # number of syscalls executed +system.cpu0.kern.syscall::71 21 11.05% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.58% 87.89% # number of syscalls executed +system.cpu0.kern.syscall::74 5 2.63% 90.53% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.53% 91.05% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.05% 92.11% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.68% 95.79% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.05% 96.84% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.05% 97.89% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.53% 98.42% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.53% 98.95% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.05% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 190 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 288 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3442 2.06% 2.23% # number of callpals executed -system.cpu0.kern.callpal::tbi 49 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 152297 91.02% 93.29% # number of callpals executed -system.cpu0.kern.callpal::rdps 6331 3.78% 97.07% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.07% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.07% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.08% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.08% # number of callpals executed -system.cpu0.kern.callpal::rti 4417 2.64% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 330 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167317 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6879 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1175 # number of protection mode switches +system.cpu0.kern.callpal::wripir 292 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3426 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151781 91.02% 93.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6336 3.80% 97.08% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.08% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.08% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.09% # number of callpals executed +system.cpu0.kern.callpal::rti 4399 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 318 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 166759 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6855 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1159 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1175 -system.cpu0.kern.mode_good::user 1175 +system.cpu0.kern.mode_good::kernel 1159 +system.cpu0.kern.mode_good::user 1159 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170810 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.169074 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.291780 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1921452590000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2041385500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.289244 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1925885387000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1988942000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3443 # number of times the context was actually changed +system.cpu0.kern.swap_context 3427 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2563 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 58062 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18132 36.97% 36.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 3.93% 40.90% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 288 0.59% 41.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28696 58.51% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49044 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17757 47.43% 47.43% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 5.15% 52.57% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 288 0.77% 53.34% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17469 46.66% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37442 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1877611262500 97.58% 97.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 563601000 0.03% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 141411000 0.01% 97.62% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45839038500 2.38% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1924155313000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979318 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2571 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58929 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18404 37.04% 37.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1933 3.89% 40.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 292 0.59% 41.51% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 29063 58.49% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49692 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 18019 47.45% 47.45% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1933 5.09% 52.55% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 292 0.77% 53.31% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17727 46.69% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37971 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1882485952500 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 565596500 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 145516500 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45879988500 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1929077054000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979081 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.608761 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.763437 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.75% 0.75% # number of syscalls executed -system.cpu1.kern.syscall::3 14 10.45% 11.19% # number of syscalls executed -system.cpu1.kern.syscall::6 14 10.45% 21.64% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.75% 22.39% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.22% 27.61% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.24% 29.85% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.49% 31.34% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.24% 33.58% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.24% 35.82% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.73% 39.55% # number of syscalls executed -system.cpu1.kern.syscall::45 23 17.16% 56.72% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.24% 58.96% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.49% 60.45% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.75% 61.19% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.75% 61.94% # number of syscalls executed -system.cpu1.kern.syscall::71 33 24.63% 86.57% # number of syscalls executed -system.cpu1.kern.syscall::74 11 8.21% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.75% 95.52% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.49% 97.01% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.24% 99.25% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.75% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 134 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.609951 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.764127 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.74% 0.74% # number of syscalls executed +system.cpu1.kern.syscall::3 15 11.03% 11.76% # number of syscalls executed +system.cpu1.kern.syscall::6 14 10.29% 22.06% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.74% 22.79% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.15% 27.94% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.21% 30.15% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.47% 31.62% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.21% 33.82% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.21% 36.03% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.68% 39.71% # number of syscalls executed +system.cpu1.kern.syscall::45 23 16.91% 56.62% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.21% 58.82% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.47% 60.29% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.74% 61.03% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.47% 62.50% # number of syscalls executed +system.cpu1.kern.syscall::71 33 24.26% 86.76% # number of syscalls executed +system.cpu1.kern.syscall::74 11 8.09% 94.85% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.74% 95.59% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.47% 97.06% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.21% 99.26% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.74% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 136 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wripir 191 0.37% 0.37% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1149 2.26% 2.64% # number of callpals executed -system.cpu1.kern.callpal::tbi 4 0.01% 2.64% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.66% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43675 85.89% 88.55% # number of callpals executed -system.cpu1.kern.callpal::rdps 2435 4.79% 93.34% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.34% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.35% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.35% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.35% # number of callpals executed -system.cpu1.kern.callpal::rti 3152 6.20% 99.55% # number of callpals executed -system.cpu1.kern.callpal::callsys 185 0.36% 99.92% # number of callpals executed -system.cpu1.kern.callpal::imb 41 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1171 2.27% 2.65% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 2.66% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed +system.cpu1.kern.callpal::swpipl 44279 85.92% 88.59% # number of callpals executed +system.cpu1.kern.callpal::rdps 2440 4.73% 93.33% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.33% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.34% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.34% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.34% # number of callpals executed +system.cpu1.kern.callpal::rti 3187 6.18% 99.53% # number of callpals executed +system.cpu1.kern.callpal::callsys 197 0.38% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 45 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 50850 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1515 # number of protection mode switches -system.cpu1.kern.mode_switch::user 561 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2424 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 773 -system.cpu1.kern.mode_good::user 561 -system.cpu1.kern.mode_good::idle 212 -system.cpu1.kern.mode_switch_good::kernel 0.510231 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 51536 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1550 # number of protection mode switches +system.cpu1.kern.mode_switch::user 578 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 794 +system.cpu1.kern.mode_good::user 578 +system.cpu1.kern.mode_good::idle 216 +system.cpu1.kern.mode_switch_good::kernel 0.512258 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.087459 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.343556 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4865757000 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 846470000 0.04% 0.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1918443078000 99.70% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1150 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.088670 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.347940 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4980780500 0.26% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 920793000 0.05% 0.31% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1923175472500 99.69% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1172 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |