diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual')
| -rwxr-xr-x | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 8 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2752 |
2 files changed, 1382 insertions, 1378 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 70213a160..da3261384 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:47:49 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:11:03 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 106949500 -Exiting @ tick 1897464893500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107002000 +Exiting @ tick 1899401490000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 89ae1dc03..af2074343 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,179 +1,179 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897465 # Number of seconds simulated -sim_ticks 1897464893500 # Number of ticks simulated -final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.899401 # Number of seconds simulated +sim_ticks 1899401490000 # Number of ticks simulated +final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189830 # Simulator instruction rate (inst/s) -host_op_rate 189830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6418636186 # Simulator tick rate (ticks/s) -host_mem_usage 296280 # Number of bytes of host memory used -host_seconds 295.62 # Real time elapsed on the host -sim_insts 56117221 # Number of instructions simulated -sim_ops 56117221 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30408512 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10470144 # Number of bytes written to this memory -system.physmem.num_reads 475133 # Number of read requests responded to by this memory -system.physmem.num_writes 163596 # Number of write requests responded to by this memory +host_inst_rate 189434 # Simulator instruction rate (inst/s) +host_op_rate 189434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6363739723 # Simulator tick rate (ticks/s) +host_mem_usage 296196 # Number of bytes of host memory used +host_seconds 298.47 # Real time elapsed on the host +sim_insts 56540749 # Number of instructions simulated +sim_ops 56540749 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 30421696 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10508736 # Number of bytes written to this memory +system.physmem.num_reads 475339 # Number of read requests responded to by this memory +system.physmem.num_writes 164199 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16025863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 579367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5517965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21543827 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397850 # number of replacements -system.l2c.tagsinuse 35109.782430 # Cycle average of tags in use -system.l2c.total_refs 2482376 # Total number of references to valid blocks. -system.l2c.sampled_refs 433566 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.725486 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22866.713220 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4068.067496 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7937.521810 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 126.484558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 110.995347 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.348918 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.062074 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.121117 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001930 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001694 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.535733 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 955732 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 764474 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 109195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 38109 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1867510 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 827202 # number of Writeback hits -system.l2c.Writeback_hits::total 827202 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 45 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 168180 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 11095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 955732 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 932654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 109195 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 49204 # number of demand (read+write) hits -system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 955732 # number of overall hits -system.l2c.overall_hits::cpu0.data 932654 # number of overall hits -system.l2c.overall_hits::cpu1.inst 109195 # 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number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 102548000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 110604500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16117985000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2465000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1619000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 4084000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 420000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 629500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5974507500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 563694000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6538201500 # 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mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.837812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39448.492462 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.041511 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40004.297994 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40004.032258 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.712329 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40298.511698 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40214.276765 # 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average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -293,81 +293,81 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.463236 # Cycle average of tags in use +system.iocache.replacements 41698 # number of replacements +system.iocache.tagsinuse 0.205020 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # 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average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137570.653598 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64638062 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6181.319881 # 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number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63209.028249 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.230266 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -385,22 +385,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9525013 # DTB read hits -system.cpu0.dtb.read_misses 35809 # DTB read misses -system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_accesses 640960 # DTB read accesses -system.cpu0.dtb.write_hits 6193277 # DTB write hits -system.cpu0.dtb.write_misses 8191 # DTB write misses -system.cpu0.dtb.write_acv 352 # DTB write access violations -system.cpu0.dtb.write_accesses 218947 # DTB write accesses -system.cpu0.dtb.data_hits 15718290 # DTB hits -system.cpu0.dtb.data_misses 44000 # DTB misses -system.cpu0.dtb.data_acv 948 # DTB access violations -system.cpu0.dtb.data_accesses 859907 # DTB accesses -system.cpu0.itb.fetch_hits 1059968 # ITB hits -system.cpu0.itb.fetch_misses 28334 # ITB misses -system.cpu0.itb.fetch_acv 968 # ITB acv -system.cpu0.itb.fetch_accesses 1088302 # ITB accesses +system.cpu0.dtb.read_hits 8814586 # DTB read hits +system.cpu0.dtb.read_misses 32972 # DTB read misses +system.cpu0.dtb.read_acv 518 # DTB read access violations +system.cpu0.dtb.read_accesses 619797 # DTB read accesses +system.cpu0.dtb.write_hits 5858085 # DTB write hits +system.cpu0.dtb.write_misses 6892 # DTB write misses +system.cpu0.dtb.write_acv 315 # DTB write access violations +system.cpu0.dtb.write_accesses 207416 # DTB write accesses +system.cpu0.dtb.data_hits 14672671 # DTB hits +system.cpu0.dtb.data_misses 39864 # DTB misses +system.cpu0.dtb.data_acv 833 # DTB access violations +system.cpu0.dtb.data_accesses 827213 # DTB accesses +system.cpu0.itb.fetch_hits 1034325 # ITB hits +system.cpu0.itb.fetch_misses 27665 # ITB misses +system.cpu0.itb.fetch_acv 1025 # ITB acv +system.cpu0.itb.fetch_accesses 1061990 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -413,279 +413,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112143855 # number of cpu cycles simulated +system.cpu0.numCycles 105407779 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13691834 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11482212 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 486842 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 12387016 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 6381871 # Number of BTB hits +system.cpu0.BPredUnit.lookups 12543533 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 10518625 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 389841 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9001573 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5310644 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 919331 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37475 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28027181 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69568075 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13691834 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 7301202 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 13494473 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2151438 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34839073 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 192820 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 330609 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8536872 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 297084 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 78309049 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.888378 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.203941 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 819125 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 58295 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 26579965 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63634622 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12543533 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6129769 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12006508 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1822886 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32559683 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31957 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 177706 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 213013 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 154 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7876403 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 267953 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 72741022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.874811 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.212644 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64814576 82.77% 82.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 945457 1.21% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1900376 2.43% 86.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 913364 1.17% 87.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2830968 3.62% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 643425 0.82% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 763526 0.98% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1019235 1.30% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4478122 5.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 60734514 83.49% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 798536 1.10% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1573590 2.16% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 701435 0.96% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2536566 3.49% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 541598 0.74% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 587478 0.81% 92.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 932961 1.28% 94.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4334344 5.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78309049 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.122092 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.620347 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29152885 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34531702 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12346249 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 922431 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1355781 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 563186 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 37995 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68107436 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115019 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1355781 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30289459 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12441617 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18623001 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11519994 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4079195 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64318914 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6762 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 463310 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1470134 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 43045469 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 78042276 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77610485 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 431791 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36467151 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6578318 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1575666 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238414 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11470150 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10031617 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6527341 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1189503 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 776121 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56398484 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2006474 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54915556 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 111021 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7522313 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3811151 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1368811 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78309049 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.701267 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.347671 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 72741022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.119000 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.603699 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27434990 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 32338165 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10959738 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 873036 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1135092 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 524168 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 38246 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62454506 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 104596 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1135092 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28444580 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11348794 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17719135 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10252710 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3840709 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59087115 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6759 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 385226 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1425299 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39461950 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71535536 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71092330 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 443206 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34168968 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5292982 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1501174 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 229517 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10778320 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9311808 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6175617 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1139122 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 734045 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52101492 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1888432 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50847383 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 113537 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6290735 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3199038 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1282649 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 72741022 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.699019 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.352112 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54156181 69.16% 69.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10641057 13.59% 82.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5191025 6.63% 89.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3329795 4.25% 93.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2517318 3.21% 96.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1471186 1.88% 98.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 638979 0.82% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 264076 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 99432 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50396766 69.28% 69.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9972815 13.71% 82.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4663131 6.41% 89.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3055348 4.20% 93.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2346789 3.23% 96.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1299072 1.79% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 640768 0.88% 99.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 275526 0.38% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 90807 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78309049 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 72741022 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 63169 8.93% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 344330 48.66% 57.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 300145 42.41% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 76308 11.21% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 321562 47.25% 58.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 282678 41.54% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3325 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37729557 68.70% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60298 0.11% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9958587 18.13% 86.99% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6269977 11.42% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 876476 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3304 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34794736 68.43% 68.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54066 0.11% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15533 0.03% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1651 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9216611 18.13% 86.70% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5928101 11.66% 98.36% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 833381 1.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54915556 # Type of FU issued -system.cpu0.iq.rate 0.489688 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 707644 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012886 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 188337006 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65642365 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53492231 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 621820 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 297359 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294491 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55293187 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326688 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 545095 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50847383 # Type of FU issued +system.cpu0.iq.rate 0.482387 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 680548 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013384 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 174615866 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59997059 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 49635166 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 614007 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 294188 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 289709 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51201778 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 322849 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 529914 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1437170 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 14653 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12768 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 528040 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1228237 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2717 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10847 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496354 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18971 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 166861 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 15126 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 162620 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1355781 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8686714 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 606542 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61919404 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 833136 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10031617 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6527341 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1771520 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 483474 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10610 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12768 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 354996 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356258 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 711254 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54276592 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9587869 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 638964 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1135092 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7799066 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 574299 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57208008 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 766721 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9311808 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6175617 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1662895 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 472481 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 9295 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10847 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 216142 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 364728 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 580870 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50321201 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8875076 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 526182 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3514446 # number of nop insts executed -system.cpu0.iew.exec_refs 15803723 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8658040 # Number of branches executed -system.cpu0.iew.exec_stores 6215854 # Number of stores executed -system.cpu0.iew.exec_rate 0.483991 # Inst execution rate -system.cpu0.iew.wb_sent 53903758 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53786722 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26555285 # num instructions producing a value -system.cpu0.iew.wb_consumers 35742632 # num instructions consuming a value +system.cpu0.iew.exec_nop 3218084 # number of nop insts executed +system.cpu0.iew.exec_refs 14754207 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7980527 # Number of branches executed +system.cpu0.iew.exec_stores 5879131 # Number of stores executed +system.cpu0.iew.exec_rate 0.477396 # Inst execution rate +system.cpu0.iew.wb_sent 50024045 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 49924875 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24623982 # num instructions producing a value +system.cpu0.iew.wb_consumers 33198875 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.479623 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742958 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.473636 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.741711 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 53643051 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 53643051 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 8183882 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 637663 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 648245 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76953268 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.697086 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608248 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 50284711 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 50284711 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6832336 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 605783 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 542146 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 71605930 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.702242 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.623363 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56721555 73.71% 73.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8492436 11.04% 84.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4533561 5.89% 90.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2497224 3.25% 93.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1462149 1.90% 95.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 614089 0.80% 96.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 448311 0.58% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 488630 0.63% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1695313 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 52797293 73.73% 73.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7885539 11.01% 84.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4166098 5.82% 90.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2329305 3.25% 93.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1331723 1.86% 95.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 575927 0.80% 96.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 415417 0.58% 97.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 456992 0.64% 97.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1647636 2.30% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76953268 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53643051 # Number of instructions committed -system.cpu0.commit.committedOps 53643051 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 71605930 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50284711 # Number of instructions committed +system.cpu0.commit.committedOps 50284711 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14593748 # Number of memory references committed -system.cpu0.commit.loads 8594447 # Number of loads committed -system.cpu0.commit.membars 217509 # Number of memory barriers committed -system.cpu0.commit.branches 8090596 # Number of branches committed -system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49625357 # Number of committed integer instructions. -system.cpu0.commit.function_calls 704226 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1695313 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13762834 # Number of memory references committed +system.cpu0.commit.loads 8083571 # Number of loads committed +system.cpu0.commit.membars 205088 # Number of memory barriers committed +system.cpu0.commit.branches 7564309 # Number of branches committed +system.cpu0.commit.fp_insts 287246 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46527621 # Number of committed integer instructions. +system.cpu0.commit.function_calls 644133 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1647636 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 136894487 # The number of ROB reads -system.cpu0.rob.rob_writes 125011331 # The number of ROB writes -system.cpu0.timesIdled 1231743 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33834806 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3682779567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50529139 # Number of Instructions Simulated -system.cpu0.committedOps 50529139 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 50529139 # Number of Instructions Simulated -system.cpu0.cpi 2.219390 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.219390 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.450574 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.450574 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71166140 # number of integer regfile reads -system.cpu0.int_regfile_writes 38904534 # number of integer regfile writes -system.cpu0.fp_regfile_reads 143931 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146323 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1862401 # number of misc regfile reads -system.cpu0.misc_regfile_writes 887781 # number of misc regfile writes +system.cpu0.rob.rob_reads 126892294 # The number of ROB reads +system.cpu0.rob.rob_writes 115369853 # The number of ROB writes +system.cpu0.timesIdled 1161435 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32666757 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693390286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47376653 # Number of Instructions Simulated +system.cpu0.committedOps 47376653 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47376653 # Number of Instructions Simulated +system.cpu0.cpi 2.224889 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.224889 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.449461 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.449461 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65983871 # number of integer regfile reads +system.cpu0.int_regfile_writes 36054560 # number of integer regfile writes +system.cpu0.fp_regfile_reads 141566 # number of floating regfile reads +system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads +system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -717,211 +717,211 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 970410 # number of replacements -system.cpu0.icache.tagsinuse 510.008513 # Cycle average of tags in use -system.cpu0.icache.total_refs 7511566 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 970922 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.736529 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23358767000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.008513 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7511566 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7511566 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7511566 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7511566 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7511566 # number of overall hits -system.cpu0.icache.overall_hits::total 7511566 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1025306 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1025306 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1025306 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1025306 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1025306 # number of overall misses -system.cpu0.icache.overall_misses::total 1025306 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15323045497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 15323045497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 15323045497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 15323045497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 15323045497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 15323045497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8536872 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8536872 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8536872 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8536872 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8536872 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8536872 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120103 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120103 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120103 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14944.851095 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1297498 # number of cycles access was blocked +system.cpu0.icache.replacements 923652 # number of replacements +system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use +system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.006511 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996106 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996106 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6902434 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6902434 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6902434 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6902434 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6902434 # number of overall hits +system.cpu0.icache.overall_hits::total 6902434 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 973969 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 973969 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 973969 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 973969 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 973969 # number of overall misses +system.cpu0.icache.overall_misses::total 973969 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14544794497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14544794497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14544794497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14544794497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14544794497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14544794497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7876403 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7876403 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7876403 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7876403 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 107 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 220 # number of writebacks -system.cpu0.icache.writebacks::total 220 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54249 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54249 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54249 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54249 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54249 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54249 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 971057 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 971057 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 971057 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 971057 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 971057 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 971057 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11617533498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11617533498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11617533498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11617533498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11617533498 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11617533498 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 196 # number of writebacks +system.cpu0.icache.writebacks::total 196 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 49660 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 49660 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 924309 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 924309 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 924309 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 924309 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 924309 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 924309 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11020233999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11020233999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11020233999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1340651 # number of replacements -system.cpu0.dcache.tagsinuse 504.872538 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11358067 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341162 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.468826 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19222000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 504.872538 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986079 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986079 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6993872 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6993872 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3966970 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3966970 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 182544 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 182544 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208490 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208490 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10960842 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10960842 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10960842 # number of overall hits -system.cpu0.dcache.overall_hits::total 10960842 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1697480 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1697480 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1808304 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1808304 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21693 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21693 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 688 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3505784 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3505784 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3505784 # number of overall misses -system.cpu0.dcache.overall_misses::total 3505784 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 37053025000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 37053025000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55161743853 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 55161743853 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326351000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 326351000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6342500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 6342500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 92214768853 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 92214768853 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 92214768853 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 92214768853 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8691352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8691352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5775274 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5775274 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 204237 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204237 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209178 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209178 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14466626 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14466626 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14466626 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14466626 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195307 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.313111 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106215 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003289 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.242336 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.242336 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21828.254236 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30504.684972 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15044.069516 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9218.750000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 888039305 # number of cycles access was blocked +system.cpu0.dcache.replacements 1225027 # number of replacements +system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10607012 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1225539 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.654977 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 19420000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 491.225534 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.959425 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.959425 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6460129 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6460129 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3759204 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3759204 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177511 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 177511 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 200041 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 200041 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10219333 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10219333 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10219333 # number of overall hits +system.cpu0.dcache.overall_hits::total 10219333 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1549115 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1549115 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1704606 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1704606 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20750 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20750 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2030 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2030 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3253721 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3253721 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3253721 # number of overall misses +system.cpu0.dcache.overall_misses::total 3253721 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34776889000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34776889000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52688012248 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 52688012248 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301583000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 301583000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 24841500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 24841500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 87464901248 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 87464901248 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 87464901248 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 87464901248 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8009244 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8009244 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5463810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5463810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 198261 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 198261 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 202071 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 202071 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13473054 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13473054 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 98700 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8997.358713 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8893.625908 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 791009 # number of writebacks -system.cpu0.dcache.writebacks::total 791009 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 651385 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 651385 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523767 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1523767 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4864 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4864 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2175152 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2175152 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2175152 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2175152 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1046095 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1046095 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 284537 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 284537 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 688 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 688 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330632 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1330632 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330632 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1330632 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24225951000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24225951000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8293520304 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8293520304 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195490000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195490000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4269500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4269500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32519471304 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 32519471304 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32519471304 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 32519471304 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 916801000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 916801000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1252089998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1252089998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2168890998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2168890998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120360 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049268 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.082399 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003289 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23158.461708 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29147.423021 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11616.257650 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6205.668605 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 689568 # number of writebacks +system.cpu0.dcache.writebacks::total 689568 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 597617 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 597617 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436241 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1436241 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4277 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4277 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2033858 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2033858 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2033858 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2033858 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 951498 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 951498 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 268365 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 268365 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16473 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16473 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2030 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2030 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1219863 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1219863 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1219863 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1219863 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22991247500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22991247500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7905411394 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7905411394 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183295500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183295500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18744000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18744000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30896658894 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30896658894 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30896658894 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30896658894 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 635008500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 635008500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1065246998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency @@ -930,22 +930,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1327892 # DTB read hits -system.cpu1.dtb.read_misses 10318 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 331425 # DTB read accesses -system.cpu1.dtb.write_hits 775217 # DTB write hits -system.cpu1.dtb.write_misses 3380 # DTB write misses -system.cpu1.dtb.write_acv 51 # DTB write access violations -system.cpu1.dtb.write_accesses 128049 # DTB write accesses -system.cpu1.dtb.data_hits 2103109 # DTB hits -system.cpu1.dtb.data_misses 13698 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 459474 # DTB accesses -system.cpu1.itb.fetch_hits 367800 # ITB hits -system.cpu1.itb.fetch_misses 7781 # ITB misses -system.cpu1.itb.fetch_acv 134 # ITB acv -system.cpu1.itb.fetch_accesses 375581 # ITB accesses +system.cpu1.dtb.read_hits 1967803 # DTB read hits +system.cpu1.dtb.read_misses 13979 # DTB read misses +system.cpu1.dtb.read_acv 50 # DTB read access violations +system.cpu1.dtb.read_accesses 344857 # DTB read accesses +system.cpu1.dtb.write_hits 1156959 # DTB write hits +system.cpu1.dtb.write_misses 3426 # DTB write misses +system.cpu1.dtb.write_acv 86 # DTB write access violations +system.cpu1.dtb.write_accesses 133134 # DTB write accesses +system.cpu1.dtb.data_hits 3124762 # DTB hits +system.cpu1.dtb.data_misses 17405 # DTB misses +system.cpu1.dtb.data_acv 136 # DTB access violations +system.cpu1.dtb.data_accesses 477991 # DTB accesses +system.cpu1.itb.fetch_hits 421916 # ITB hits +system.cpu1.itb.fetch_misses 9109 # ITB misses +system.cpu1.itb.fetch_acv 356 # ITB acv +system.cpu1.itb.fetch_accesses 431025 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -958,643 +958,647 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 9964881 # number of cpu cycles simulated +system.cpu1.numCycles 16642884 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1747552 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1443569 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 66414 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1567726 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 697812 # Number of BTB hits +system.cpu1.BPredUnit.lookups 2705570 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2183133 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 103658 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1600081 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 956693 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 120159 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5219 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3352807 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8393265 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1747552 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 817971 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1599998 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 341231 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3951622 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24365 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48200 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1053319 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 37675 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9267506 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.905666 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.249416 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 205000 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 11458 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 5302876 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13307049 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2705570 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1161693 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2441613 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 501707 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6356468 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 74919 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 150190 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1679881 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 61959 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14687135 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.906034 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.268778 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7667508 82.74% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 116348 1.26% 83.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 230890 2.49% 86.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 132710 1.43% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 250243 2.70% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 85158 0.92% 91.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 106718 1.15% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 73511 0.79% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 604420 6.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12245522 83.38% 83.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 134693 0.92% 84.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 301692 2.05% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 210681 1.43% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 386391 2.63% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 150965 1.03% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 158556 1.08% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 103876 0.71% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 994759 6.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9267506 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.175371 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.842285 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3427974 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4057837 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1486886 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 74257 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 220551 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 74813 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4599 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8126768 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13850 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 220551 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3564378 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 427759 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3208421 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1411256 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 435139 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7552023 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45897 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 92610 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5051424 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9247695 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9194844 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52851 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4016877 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1034547 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 305973 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22549 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1293822 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1418447 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 841500 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 143535 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 89440 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6603642 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 325438 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6286957 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22758 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1275148 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 714507 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 249945 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9267506 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.678387 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.328894 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14687135 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.162566 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.799564 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5465828 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6500437 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2284956 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 109363 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 326550 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 135471 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8440 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12979059 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22096 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 326550 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5675549 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 1529515 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4345584 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2134958 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 674977 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12129764 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 166 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 128005 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 129891 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 8170378 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 14771785 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 14690250 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 81535 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6624020 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1546358 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 396407 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 33332 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2062542 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2114945 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1244442 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 252990 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 158890 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 10689942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 428775 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10217833 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 32007 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1868726 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1009548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 314972 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14687135 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.695700 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.377163 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 6496050 70.09% 70.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1227596 13.25% 83.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 583666 6.30% 89.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 391304 4.22% 93.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 294316 3.18% 97.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 159029 1.72% 98.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 73572 0.79% 99.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 31508 0.34% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10465 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10355359 70.51% 70.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1845686 12.57% 83.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 877719 5.98% 89.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 637269 4.34% 93.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 497555 3.39% 96.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 237687 1.62% 98.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 141618 0.96% 99.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 77397 0.53% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 16845 0.11% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9267506 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14687135 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2850 1.96% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 81883 56.36% 58.33% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60541 41.67% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 13419 6.74% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 108426 54.48% 61.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 77176 38.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3977 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3891249 61.89% 61.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10225 0.16% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1383111 22.00% 84.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 794977 12.64% 96.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 191359 3.04% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3982 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6701010 65.58% 65.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17534 0.17% 65.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10648 0.10% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2057377 20.14% 86.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1183005 11.58% 97.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 242286 2.37% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6286957 # Type of FU issued -system.cpu1.iq.rate 0.630911 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 145274 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023107 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 21930562 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8166757 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6084651 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 78890 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 39096 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37806 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6387378 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40876 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 61877 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10217833 # Type of FU issued +system.cpu1.iq.rate 0.613946 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 199021 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019478 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 35235052 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 12931686 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9924010 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 118777 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 58514 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 57042 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10351384 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 61488 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 101325 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 265041 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6645 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1728 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 113419 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 375645 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 853 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2882 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 159755 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 368 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 22536 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4092 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 23338 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 220551 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 309881 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12131 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7193888 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 99371 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1418447 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 841500 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 303567 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4003 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 5102 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1728 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 48086 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 60250 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 108336 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6208556 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1341795 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 78401 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 326550 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1215619 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 41484 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 11650788 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 153391 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2114945 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1244442 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 389086 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9620 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6598 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2882 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57079 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 98765 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 155844 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10093188 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1987752 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 124645 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 264808 # number of nop insts executed -system.cpu1.iew.exec_refs 2123746 # number of memory reference insts executed -system.cpu1.iew.exec_branches 906293 # Number of branches executed -system.cpu1.iew.exec_stores 781951 # Number of stores executed -system.cpu1.iew.exec_rate 0.623044 # Inst execution rate -system.cpu1.iew.wb_sent 6150217 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6122457 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2959215 # num instructions producing a value -system.cpu1.iew.wb_consumers 4044738 # num instructions consuming a value +system.cpu1.iew.exec_nop 532071 # number of nop insts executed +system.cpu1.iew.exec_refs 3152815 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1559516 # Number of branches executed +system.cpu1.iew.exec_stores 1165063 # Number of stores executed +system.cpu1.iew.exec_rate 0.606457 # Inst execution rate +system.cpu1.iew.wb_sent 10020459 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9981052 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4916782 # num instructions producing a value +system.cpu1.iew.wb_consumers 6843934 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614403 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.731621 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.599719 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.718415 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5811574 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 5811574 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1309607 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 75493 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 100450 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9046955 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642379 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.547455 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 9615778 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 9615778 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1958417 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 113803 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 145209 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14360585 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.669595 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.592350 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6775881 74.90% 74.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1100597 12.17% 87.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 394396 4.36% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 244103 2.70% 94.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 155347 1.72% 95.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 74536 0.82% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76677 0.85% 97.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 67598 0.75% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 157820 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10743360 74.81% 74.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1616043 11.25% 86.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 700215 4.88% 90.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 397241 2.77% 93.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 279128 1.94% 95.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 129549 0.90% 96.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 113540 0.79% 97.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 89987 0.63% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 291522 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9046955 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5811574 # Number of instructions committed -system.cpu1.commit.committedOps 5811574 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14360585 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9615778 # Number of instructions committed +system.cpu1.commit.committedOps 9615778 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1881487 # Number of memory references committed -system.cpu1.commit.loads 1153406 # Number of loads committed -system.cpu1.commit.membars 20496 # Number of memory barriers committed -system.cpu1.commit.branches 821024 # Number of branches committed -system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5437311 # Number of committed integer instructions. -system.cpu1.commit.function_calls 89377 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 157820 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2823987 # Number of memory references committed +system.cpu1.commit.loads 1739300 # Number of loads committed +system.cpu1.commit.membars 35653 # Number of memory barriers committed +system.cpu1.commit.branches 1422938 # Number of branches committed +system.cpu1.commit.fp_insts 55483 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8948473 # Number of committed integer instructions. +system.cpu1.commit.function_calls 153476 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 291522 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 15919643 # The number of ROB reads -system.cpu1.rob.rob_writes 14461697 # The number of ROB writes -system.cpu1.timesIdled 81901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 697375 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3784961926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5588082 # Number of Instructions Simulated -system.cpu1.committedOps 5588082 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5588082 # Number of Instructions Simulated -system.cpu1.cpi 1.783238 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.783238 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.560778 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.560778 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8095217 # number of integer regfile reads -system.cpu1.int_regfile_writes 4412873 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24584 # number of floating regfile reads -system.cpu1.fp_regfile_writes 23091 # number of floating regfile writes -system.cpu1.misc_regfile_reads 284668 # number of misc regfile reads -system.cpu1.misc_regfile_writes 134791 # number of misc regfile writes -system.cpu1.icache.replacements 110606 # number of replacements -system.cpu1.icache.tagsinuse 453.435417 # Cycle average of tags in use -system.cpu1.icache.total_refs 936898 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 111117 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.431635 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874818624000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 453.435417 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.885616 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.885616 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 936898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 936898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 936898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 936898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 936898 # number of overall hits -system.cpu1.icache.overall_hits::total 936898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 116421 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 116421 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 116421 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 116421 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 116421 # number of overall misses -system.cpu1.icache.overall_misses::total 116421 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1750783999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1750783999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1750783999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1750783999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1750783999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1750783999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1053319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1053319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1053319 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1053319 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1053319 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1053319 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110528 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110528 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110528 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15038.386537 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 96999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 25542136 # The number of ROB reads +system.cpu1.rob.rob_writes 23473924 # The number of ROB writes +system.cpu1.timesIdled 165614 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1955749 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3781507254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9164096 # Number of Instructions Simulated +system.cpu1.committedOps 9164096 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 9164096 # Number of Instructions Simulated +system.cpu1.cpi 1.816097 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.816097 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550631 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550631 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13179031 # number of integer regfile reads +system.cpu1.int_regfile_writes 7231354 # number of integer regfile writes +system.cpu1.fp_regfile_reads 33888 # number of floating regfile reads +system.cpu1.fp_regfile_writes 32897 # number of floating regfile writes +system.cpu1.misc_regfile_reads 392068 # number of misc regfile reads +system.cpu1.misc_regfile_writes 179438 # number of misc regfile writes +system.cpu1.icache.replacements 177236 # number of replacements +system.cpu1.icache.tagsinuse 505.128292 # Cycle average of tags in use +system.cpu1.icache.total_refs 1491482 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 177747 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.391039 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 108399350000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.128292 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.986579 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.986579 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1491482 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1491482 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1491482 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1491482 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1491482 # number of overall hits +system.cpu1.icache.overall_hits::total 1491482 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 188398 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 188398 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 188398 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 188398 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 188398 # number of overall misses +system.cpu1.icache.overall_misses::total 188398 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2886679000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2886679000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2886679000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2886679000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2886679000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2886679000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1679880 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1679880 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1679880 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1679880 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6928.500000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 37 # number of writebacks -system.cpu1.icache.writebacks::total 37 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5236 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 5236 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 5236 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 5236 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 5236 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 5236 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 111185 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 111185 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 111185 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 111185 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 111185 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 111185 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1333353499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1333353499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1333353499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1333353499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1333353499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1333353499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 52 # number of writebacks +system.cpu1.icache.writebacks::total 52 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 10580 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 10580 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 177818 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 177818 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 177818 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 177818 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 177818 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 177818 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2188079500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2188079500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2188079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62388 # number of replacements -system.cpu1.dcache.tagsinuse 392.324021 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1699992 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62715 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 27.106625 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874614053500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 392.324021 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.766258 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.766258 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1127254 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1127254 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 549515 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 549515 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16791 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16791 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14923 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1676769 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1676769 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1676769 # number of overall hits -system.cpu1.dcache.overall_hits::total 1676769 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 106582 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 106582 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 157839 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 157839 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1481 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1481 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 695 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 695 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 264421 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 264421 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 264421 # number of overall misses -system.cpu1.dcache.overall_misses::total 264421 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1787903500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1787903500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5181152780 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5181152780 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19396000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 19396000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8380000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8380000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6969056280 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6969056280 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6969056280 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6969056280 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1233836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1233836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 707354 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 707354 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18272 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18272 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15618 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15618 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1941190 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1941190 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1941190 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1941190 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.086383 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223140 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081053 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044500 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136216 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136216 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16774.910398 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32825.555028 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.556381 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12057.553957 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 86281997 # number of cycles access was blocked +system.cpu1.dcache.replacements 156190 # number of replacements +system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2451996 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 156506 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 15.667105 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 42868987000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 478.738504 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.935036 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.935036 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1592507 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1592507 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 821344 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 821344 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 23925 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 23925 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 22430 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 22430 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2413851 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2413851 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2413851 # number of overall hits +system.cpu1.dcache.overall_hits::total 2413851 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 229184 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 229184 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 231703 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 231703 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 3831 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 3831 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 1979 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 1979 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 460887 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 460887 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 460887 # number of overall misses +system.cpu1.dcache.overall_misses::total 460887 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3617978500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3617978500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7562454737 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7562454737 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50003000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 50003000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 26428500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 26428500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11180433237 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11180433237 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11180433237 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11180433237 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1821691 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1821691 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1053047 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1053047 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 27756 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 27756 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 24409 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 24409 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2874738 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2874738 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6886 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35937 # number of writebacks -system.cpu1.dcache.writebacks::total 35937 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62835 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 62835 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 134042 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 134042 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 196877 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 196877 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 196877 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 196877 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43747 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 43747 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23797 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1186 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1186 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 695 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 695 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 67544 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 67544 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 67544 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 67544 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 555340000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 555340000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 753314485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 753314485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 11632000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 11632000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1308654485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1308654485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1308654485 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1308654485 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19116500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19116500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320800500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 320800500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 339917000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 339917000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035456 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033642 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064908 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044500 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12694.356184 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31655.859352 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9807.757167 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9046.043165 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks +system.cpu1.dcache.writebacks::total 116478 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 879 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 879 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 296787 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 296787 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 296787 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 296787 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 127049 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 127049 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37051 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 37051 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 2952 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 2952 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 1975 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 1975 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 164100 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 164100 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 164100 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 164100 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1572060500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1572060500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1129988939 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1129988939 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25904500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 25904500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 20495000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 20495000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2702049439 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2702049439 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2702049439 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2702049439 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 300850500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 300850500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 561357500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199147 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71494 40.63% 40.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 238 0.14% 40.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1915 1.09% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102317 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175972 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70129 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 238 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1915 1.34% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70122 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142412 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1858860218500 97.97% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90821000 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 390050500 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4014000 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38119760000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897464864000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980907 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 189249 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 67157 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.14% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1923 1.15% 41.55% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 121 0.07% 41.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 97397 58.38% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 166835 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 65800 49.19% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.18% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1923 1.44% 50.81% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 121 0.09% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 65679 49.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 133760 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863324430000 98.10% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91299000 0.00% 98.11% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 390735500 0.02% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 47295500 0.00% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 35546879500 1.87% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1899400639500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.979794 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685341 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.88% 28.37% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 28.84% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.72% 32.56% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.65% 37.21% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.79% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 40.47% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.40% 41.86% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.79% 44.65% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.93% 45.58% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.35% 60.93% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.40% 62.33% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.65% 66.98% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.65% 71.63% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 72.09% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.79% 74.88% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.70% 85.58% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.40% 86.98% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.79% 89.77% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 90.23% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.40% 91.63% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.19% 95.81% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.14% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 215 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed +system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed +system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed +system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed +system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed +system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 105 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169050 91.54% 93.71% # number of callpals executed -system.cpu0.kern.callpal::rdps 6330 3.43% 97.14% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rti 4761 2.58% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184665 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7257 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1249 # number of protection mode switches +system.cpu0.kern.callpal::wripir 205 0.12% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3713 2.12% 2.24% # number of callpals executed +system.cpu0.kern.callpal::tbi 45 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 159757 91.11% 93.38% # number of callpals executed +system.cpu0.kern.callpal::rdps 6320 3.60% 96.98% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rti 4796 2.74% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 348 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 134 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 175342 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1248 -system.cpu0.kern.mode_good::user 1249 +system.cpu0.kern.mode_good::kernel 1161 +system.cpu0.kern.mode_good::user 1162 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.171972 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895601847000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1863009000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3841 # number of times the context was actually changed +system.cpu0.kern.swap_context 3714 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38551 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10250 33.36% 33.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18453 60.05% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30728 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10238 45.71% 45.71% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 8.57% 54.29% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.47% 54.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10133 45.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22396 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871094081500 98.61% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343283500 0.02% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 42013500 0.00% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25985147000 1.37% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897464525500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998829 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1921 4.71% 41.54% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 205 0.50% 42.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 23643 57.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 40791 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 15002 46.99% 46.99% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1921 6.02% 53.01% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 205 0.64% 53.65% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 14797 46.35% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 31925 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870054566000 98.47% 98.47% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 345480500 0.02% 98.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 82493000 0.00% 98.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28594480500 1.51% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1899077020000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998669 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.549125 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.90% 21.62% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.31% 27.93% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.70% 30.63% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.70% 33.33% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.50% 37.84% # number of syscalls executed -system.cpu1.kern.syscall::45 21 18.92% 56.76% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.70% 59.46% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.90% 60.36% # number of syscalls executed -system.cpu1.kern.syscall::71 31 27.93% 88.29% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.01% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.70% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 111 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed +system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed +system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed +system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed +system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed +system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed +system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26174 82.49% 83.79% # number of callpals executed -system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.40% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2528 7.97% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 121 0.29% 0.29% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed +system.cpu1.kern.callpal::swpctx 734 1.74% 2.03% # number of callpals executed +system.cpu1.kern.callpal::tbi 9 0.02% 2.05% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 2.07% # number of callpals executed +system.cpu1.kern.callpal::swpipl 35949 85.20% 87.27% # number of callpals executed +system.cpu1.kern.callpal::rdps 2433 5.77% 93.03% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.03% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.05% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.05% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.06% # number of callpals executed +system.cpu1.kern.callpal::rti 2715 6.43% 99.49% # number of callpals executed +system.cpu1.kern.callpal::callsys 167 0.40% 99.89% # number of callpals executed +system.cpu1.kern.callpal::imb 47 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31730 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches -system.cpu1.kern.mode_switch::user 491 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 521 -system.cpu1.kern.mode_good::user 491 -system.cpu1.kern.mode_good::idle 30 -system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 42196 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1189 # number of protection mode switches +system.cpu1.kern.mode_switch::user 578 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2262 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 747 +system.cpu1.kern.mode_good::user 578 +system.cpu1.kern.mode_good::idle 169 +system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.614145 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2062444500 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 847773000 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893876331500 99.85% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 394 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.702972 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 735 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |