diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual')
4 files changed, 23 insertions, 28 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index f8b77d3d8..9efbaffcd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,8 +26,8 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/dist/binaries/ts_osfpal +readfile=/work/gem5.latest/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -1099,7 +1099,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -1122,7 +1122,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -1287,6 +1287,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -1337,7 +1338,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index c0d08bdf9..518507880 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -1,5 +1,5 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -warn: Obsolete M5 ivlb instruction encountered. diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index d865b26f6..c80d76784 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 10:36:29 -gem5 started Jun 21 2014 13:05:58 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Oct 29 2014 09:12:51 +gem5 started Oct 29 2014 09:21:02 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 121062000 -Exiting @ tick 1906207240000 because m5_exit instruction encountered +info: Launching CPU 1 @ 119596000 +Exiting @ tick 1905067807000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 6b49ba8d7..7598617b8 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.905068 # Nu sim_ticks 1905067807000 # Number of ticks simulated final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133407 # Simulator instruction rate (inst/s) -host_op_rate 133407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4441980470 # Simulator tick rate (ticks/s) -host_mem_usage 322876 # Number of bytes of host memory used -host_seconds 428.88 # Real time elapsed on the host +host_inst_rate 163944 # Simulator instruction rate (inst/s) +host_op_rate 163944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5458738398 # Simulator tick rate (ticks/s) +host_mem_usage 318552 # Number of bytes of host memory used +host_seconds 348.99 # Real time elapsed on the host sim_insts 57215334 # Number of instructions simulated sim_ops 57215334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -739,8 +739,6 @@ system.iocache.fast_writes 41552 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses @@ -755,16 +753,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency |