diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual')
4 files changed, 2007 insertions, 2011 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index ac0bee128..7fa651550 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -194,7 +194,7 @@ useIndirect=true [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -733,7 +733,7 @@ useIndirect=true [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1091,7 +1091,7 @@ pipelined=false [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1239,7 +1239,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -1285,7 +1285,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1383,27 +1383,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1423,6 +1423,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1432,7 +1433,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1454,9 +1455,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index b3e079503..1abbf975c 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:23 -gem5 executing on e108600-lin, pid 39569 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28085 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 127844500 -Exiting @ tick 1907672102500 because m5_exit instruction encountered +info: Launching CPU 1 @ 133768500 +Exiting @ tick 1907549438500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index dfe837c06..2752814bd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906534 # Number of seconds simulated -sim_ticks 1906533530000 # Number of ticks simulated -final_tick 1906533530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.907549 # Number of seconds simulated +sim_ticks 1907549438500 # Number of ticks simulated +final_tick 1907549438500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134861 # Simulator instruction rate (inst/s) -host_op_rate 134861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4533949866 # Simulator tick rate (ticks/s) -host_mem_usage 343876 # Number of bytes of host memory used -host_seconds 420.50 # Real time elapsed on the host -sim_insts 56709432 # Number of instructions simulated -sim_ops 56709432 # Number of ops (including micro ops) simulated +host_inst_rate 120882 # Simulator instruction rate (inst/s) +host_op_rate 120882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4068519298 # Simulator tick rate (ticks/s) +host_mem_usage 339992 # Number of bytes of host memory used +host_seconds 468.86 # Real time elapsed on the host +sim_insts 56676315 # Number of instructions simulated +sim_ops 56676315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 896192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24492096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 81664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 812544 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 857728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24440448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26283456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 896192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 81664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7904832 # Number of bytes written to this memory -system.physmem.bytes_written::total 7904832 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14003 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 382689 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12696 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26308480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 857728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7911424 # Number of bytes written to this memory +system.physmem.bytes_written::total 7911424 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410679 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123513 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123513 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 470064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12846402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 426189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13785992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 470064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512897 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4146180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4146180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4146180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 470064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12846402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 426189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17932172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410679 # Number of read requests accepted -system.physmem.writeReqs 123513 # Number of write requests accepted -system.physmem.readBursts 410679 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123513 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26276352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7903488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26283456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7904832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 411070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123616 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123616 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12812485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 465653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13791768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63478 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4147428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4147428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4147428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12812485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 465653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17939196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411070 # Number of read requests accepted +system.physmem.writeReqs 123616 # Number of write requests accepted +system.physmem.readBursts 411070 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123616 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26300288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7909696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26308480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7911424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26110 # Per bank write bursts -system.physmem.perBankRdBursts::1 26073 # Per bank write bursts -system.physmem.perBankRdBursts::2 25765 # Per bank write bursts -system.physmem.perBankRdBursts::3 25777 # Per bank write bursts -system.physmem.perBankRdBursts::4 25805 # Per bank write bursts -system.physmem.perBankRdBursts::5 25558 # Per bank write bursts -system.physmem.perBankRdBursts::6 25453 # Per bank write bursts -system.physmem.perBankRdBursts::7 25268 # Per bank write bursts -system.physmem.perBankRdBursts::8 25514 # Per bank write bursts -system.physmem.perBankRdBursts::9 25670 # Per bank write bursts -system.physmem.perBankRdBursts::10 25901 # Per bank write bursts -system.physmem.perBankRdBursts::11 25385 # Per bank write bursts -system.physmem.perBankRdBursts::12 25810 # Per bank write bursts -system.physmem.perBankRdBursts::13 25833 # Per bank write bursts -system.physmem.perBankRdBursts::14 25046 # Per bank write bursts -system.physmem.perBankRdBursts::15 25600 # Per bank write bursts -system.physmem.perBankWrBursts::0 8438 # Per bank write bursts -system.physmem.perBankWrBursts::1 8395 # Per bank write bursts -system.physmem.perBankWrBursts::2 7934 # Per bank write bursts -system.physmem.perBankWrBursts::3 7573 # Per bank write bursts -system.physmem.perBankWrBursts::4 7567 # Per bank write bursts -system.physmem.perBankWrBursts::5 7501 # Per bank write bursts -system.physmem.perBankWrBursts::6 7444 # Per bank write bursts -system.physmem.perBankWrBursts::7 7061 # Per bank write bursts -system.physmem.perBankWrBursts::8 7349 # Per bank write bursts -system.physmem.perBankWrBursts::9 7703 # Per bank write bursts -system.physmem.perBankWrBursts::10 7693 # Per bank write bursts -system.physmem.perBankWrBursts::11 7415 # Per bank write bursts -system.physmem.perBankWrBursts::12 7960 # Per bank write bursts -system.physmem.perBankWrBursts::13 8226 # Per bank write bursts -system.physmem.perBankWrBursts::14 7426 # Per bank write bursts -system.physmem.perBankWrBursts::15 7807 # Per bank write bursts +system.physmem.perBankRdBursts::0 26240 # Per bank write bursts +system.physmem.perBankRdBursts::1 25986 # Per bank write bursts +system.physmem.perBankRdBursts::2 25958 # Per bank write bursts +system.physmem.perBankRdBursts::3 25690 # Per bank write bursts +system.physmem.perBankRdBursts::4 25582 # Per bank write bursts +system.physmem.perBankRdBursts::5 25570 # Per bank write bursts +system.physmem.perBankRdBursts::6 25628 # Per bank write bursts +system.physmem.perBankRdBursts::7 25343 # Per bank write bursts +system.physmem.perBankRdBursts::8 25590 # Per bank write bursts +system.physmem.perBankRdBursts::9 25698 # Per bank write bursts +system.physmem.perBankRdBursts::10 25929 # Per bank write bursts +system.physmem.perBankRdBursts::11 25525 # Per bank write bursts +system.physmem.perBankRdBursts::12 26076 # Per bank write bursts +system.physmem.perBankRdBursts::13 25420 # Per bank write bursts +system.physmem.perBankRdBursts::14 25099 # Per bank write bursts +system.physmem.perBankRdBursts::15 25608 # Per bank write bursts +system.physmem.perBankWrBursts::0 8587 # Per bank write bursts +system.physmem.perBankWrBursts::1 8090 # Per bank write bursts +system.physmem.perBankWrBursts::2 7940 # Per bank write bursts +system.physmem.perBankWrBursts::3 7436 # Per bank write bursts +system.physmem.perBankWrBursts::4 7275 # Per bank write bursts +system.physmem.perBankWrBursts::5 7415 # Per bank write bursts +system.physmem.perBankWrBursts::6 7544 # Per bank write bursts +system.physmem.perBankWrBursts::7 7156 # Per bank write bursts +system.physmem.perBankWrBursts::8 7532 # Per bank write bursts +system.physmem.perBankWrBursts::9 7639 # Per bank write bursts +system.physmem.perBankWrBursts::10 7820 # Per bank write bursts +system.physmem.perBankWrBursts::11 7739 # Per bank write bursts +system.physmem.perBankWrBursts::12 8260 # Per bank write bursts +system.physmem.perBankWrBursts::13 7848 # Per bank write bursts +system.physmem.perBankWrBursts::14 7518 # Per bank write bursts +system.physmem.perBankWrBursts::15 7790 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 24 # Number of times write queue was full causing retry -system.physmem.totGap 1906529083500 # Total gap between requests +system.physmem.numWrRetry 73 # Number of times write queue was full causing retry +system.physmem.totGap 1907545081500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410679 # Read request sizes (log2) +system.physmem.readPktSize::6 411070 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123513 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123616 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see @@ -159,130 +159,117 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 188 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64501 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 529.911784 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 323.379229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.310744 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14472 22.44% 22.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11319 17.55% 39.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5673 8.80% 48.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2735 4.24% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2521 3.91% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1561 2.42% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1592 2.47% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1422 2.20% 64.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23206 35.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64501 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5582 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.544966 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2807.309852 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5579 99.95% 99.95% # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.308940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 323.701196 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.289256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14473 22.48% 22.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11513 17.88% 40.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5038 7.82% 48.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2819 4.38% 52.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2271 3.53% 56.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1853 2.88% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1969 3.06% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1608 2.50% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22844 35.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64388 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5502 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.686478 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2827.616380 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5499 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5582 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5582 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.123253 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.862531 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.587113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4829 86.51% 86.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 142 2.54% 89.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.27% 89.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 29 0.52% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 220 3.94% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.38% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.23% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 3 0.05% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.14% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.14% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.13% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 7 0.13% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 95.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 21 0.38% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.04% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 16 0.29% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 179 3.21% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.04% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.04% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.09% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 6 0.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 13 0.23% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5582 # Writes before turning the bus around for reads -system.physmem.totQLat 4047296750 # Total ticks spent queuing -system.physmem.totMemAccLat 11745446750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9857.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5502 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5502 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.462559 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.761271 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.372868 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4982 90.55% 90.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 39 0.71% 91.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 171 3.11% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.11% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 13 0.24% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 3 0.05% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 6 0.11% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 29 0.53% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.11% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 149 2.71% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.15% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 12 0.22% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 11 0.20% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 6 0.11% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 14 0.25% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5502 # Writes before turning the bus around for reads +system.physmem.totQLat 8174654750 # Total ticks spent queuing +system.physmem.totMemAccLat 15879817250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2054710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19892.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28607.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 38642.48 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.79 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s @@ -290,78 +277,88 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.95 # Average write queue length when enqueuing -system.physmem.readRowHits 369870 # Number of row buffer hits during reads -system.physmem.writeRowHits 99689 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.71 # Row buffer hit rate for writes -system.physmem.avgGap 3568995.95 # Average gap between requests -system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245828520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134132625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1605310200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 401196240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 58054066515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1092995561250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1277961588390 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.306343 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1818124535500 # Time in different power states -system.physmem_0.memoryStateTime::REF 63663080000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24745773250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 241799040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 131934000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597120200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 399031920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57215830500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1093730864250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1277842072950 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.243651 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1819353589250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63663080000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23516733250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 16961800 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14485891 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 473040 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10754552 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4802971 # Number of BTB hits +system.physmem.avgRdQLen 2.34 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.44 # Average write queue length when enqueuing +system.physmem.readRowHits 370634 # Number of row buffer hits during reads +system.physmem.writeRowHits 99508 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes +system.physmem.avgGap 3567598.71 # Average gap between requests +system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229108320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121773960 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320732460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3850104960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4304249550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 244489440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8392475940 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4645539360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 448697608680 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 472278008880 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.583627 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1897458465500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 385946750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1635552000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1866968885000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 12097849250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8056520750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18404684750 # Time in different power states +system.physmem_1.actEnergy 230629140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122578500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463307300 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 324402120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3763440720.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4252821870 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240122400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8356841250 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4387202880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 448891199505 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 472033988085 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.455703 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1897589722250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 380622500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1598754000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1867843123750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11424948500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7975953750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 18326036000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16746871 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14324468 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 462281 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10727156 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4756454 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.659889 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 946597 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 35405 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5065158 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 501808 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4563350 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 210940 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.340308 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 926491 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 34071 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5119287 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 497756 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4621531 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 206577 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9542415 # DTB read hits -system.cpu0.dtb.read_misses 34570 # DTB read misses -system.cpu0.dtb.read_acv 614 # DTB read access violations -system.cpu0.dtb.read_accesses 570502 # DTB read accesses -system.cpu0.dtb.write_hits 5776455 # DTB write hits -system.cpu0.dtb.write_misses 8473 # DTB write misses -system.cpu0.dtb.write_acv 390 # DTB write access violations -system.cpu0.dtb.write_accesses 186760 # DTB write accesses -system.cpu0.dtb.data_hits 15318870 # DTB hits -system.cpu0.dtb.data_misses 43043 # DTB misses -system.cpu0.dtb.data_acv 1004 # DTB access violations -system.cpu0.dtb.data_accesses 757262 # DTB accesses -system.cpu0.itb.fetch_hits 1323023 # ITB hits -system.cpu0.itb.fetch_misses 7096 # ITB misses -system.cpu0.itb.fetch_acv 610 # ITB acv -system.cpu0.itb.fetch_accesses 1330119 # ITB accesses +system.cpu0.dtb.read_hits 9412979 # DTB read hits +system.cpu0.dtb.read_misses 34328 # DTB read misses +system.cpu0.dtb.read_acv 621 # DTB read access violations +system.cpu0.dtb.read_accesses 567042 # DTB read accesses +system.cpu0.dtb.write_hits 5709982 # DTB write hits +system.cpu0.dtb.write_misses 8326 # DTB write misses +system.cpu0.dtb.write_acv 453 # DTB write access violations +system.cpu0.dtb.write_accesses 184750 # DTB write accesses +system.cpu0.dtb.data_hits 15122961 # DTB hits +system.cpu0.dtb.data_misses 42654 # DTB misses +system.cpu0.dtb.data_acv 1074 # DTB access violations +system.cpu0.dtb.data_accesses 751792 # DTB accesses +system.cpu0.itb.fetch_hits 1307701 # ITB hits +system.cpu0.itb.fetch_misses 6903 # ITB misses +system.cpu0.itb.fetch_acv 605 # ITB acv +system.cpu0.itb.fetch_accesses 1314604 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -374,606 +371,604 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13007 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6504 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 284289977.091175 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 440390387.503353 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6503 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 12949 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6475 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 285376318.378378 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440714536.369915 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6475 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 79500 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6504 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 57511518999 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849022011001 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 115029541 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6475 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 59737777000 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847811661500 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 119482029 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26105514 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 74391279 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16961800 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6251376 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 82220028 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1360432 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28534 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 140847 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 424678 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8564382 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 320281 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 109600123 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.678752 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.000671 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25760123 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 73391497 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16746871 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6180701 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 86881424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1333696 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 31404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 137910 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 424032 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 391 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8451225 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 316387 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 113902133 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.644338 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.954525 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 95795479 87.40% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 897061 0.82% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1880834 1.72% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 785387 0.72% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2637004 2.41% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 588358 0.54% 93.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 697546 0.64% 94.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 846325 0.77% 95.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5472129 4.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 100270966 88.03% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 886228 0.78% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1867927 1.64% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 772028 0.68% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2612142 2.29% 93.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 579506 0.51% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 682297 0.60% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 834861 0.73% 95.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5396178 4.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 109600123 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.147456 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.646715 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20981522 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 77286866 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8861450 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1818601 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 651683 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 621495 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 29133 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 64563390 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 88112 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 651683 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21851256 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 51776932 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17156942 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9742291 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8421017 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62086646 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 197170 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2004328 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 218757 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4545100 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 41879351 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 74952395 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 74819888 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 123702 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34134806 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7744545 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1440211 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 234687 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12404512 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9945616 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6151141 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1474462 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 959878 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 54892526 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1879962 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 53219239 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 73531 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9606336 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4159079 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1308684 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 109600123 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.485576 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.229164 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 113902133 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.140162 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614247 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20705856 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 82013409 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8738075 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1805880 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 638912 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 611998 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 28528 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 63750944 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 85334 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 638912 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21566893 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55682864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17571842 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9616135 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8825485 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 61313705 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 198555 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2000786 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 244905 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4945993 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41348673 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 74029068 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 73897769 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 122571 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33810397 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7538276 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1420468 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 230583 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12282803 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9801073 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6065767 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1438850 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 936003 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54214575 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1853218 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52616152 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 74253 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9353064 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4027640 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1289091 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 113902133 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.461942 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.202978 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 87964311 80.26% 80.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9240201 8.43% 88.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3866881 3.53% 92.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2775272 2.53% 94.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2892547 2.64% 97.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1421694 1.30% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 953270 0.87% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 366394 0.33% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 119553 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 92500805 81.21% 81.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9147500 8.03% 89.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3821730 3.36% 92.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2743420 2.41% 95.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2859412 2.51% 97.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1408857 1.24% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 945269 0.83% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 359735 0.32% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 115405 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 109600123 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 113902133 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 170160 16.71% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 520319 51.11% 67.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 327644 32.18% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 168885 16.84% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 512937 51.15% 67.99% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 321005 32.01% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36500931 68.59% 68.59% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56437 0.11% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25510 0.05% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9976302 18.75% 87.49% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5867670 11.03% 98.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 788585 1.48% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36110587 68.63% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 55774 0.11% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25398 0.05% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9844131 18.71% 87.50% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5797742 11.02% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 778716 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 53219239 # Type of FU issued -system.cpu0.iq.rate 0.462657 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1018124 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019131 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 216556534 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 66119650 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51474452 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 573722 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 277081 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260310 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53925009 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 309817 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 608784 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52616152 # Type of FU issued +system.cpu0.iq.rate 0.440369 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1002827 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019059 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 219643662 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65164078 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50897823 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 567855 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 274599 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 257683 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53309936 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 306506 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 606515 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1996070 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4265 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18313 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 688901 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1936563 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4258 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18275 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 663361 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18448 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 363376 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18355 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 359900 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 651683 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 48679015 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 759858 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 60350483 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 162315 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9945616 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6151141 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1664805 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40490 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 518912 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18313 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186521 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 513145 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 699666 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52530190 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9602772 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 689049 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 638912 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 52175649 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1047801 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 59607584 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 159494 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9801073 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6065767 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1641866 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39898 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 807337 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18275 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 179860 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 504304 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 684164 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51934418 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9472740 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 681734 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3577995 # number of nop insts executed -system.cpu0.iew.exec_refs 15404618 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8349417 # Number of branches executed -system.cpu0.iew.exec_stores 5801846 # Number of stores executed -system.cpu0.iew.exec_rate 0.456667 # Inst execution rate -system.cpu0.iew.wb_sent 51922146 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51734762 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26504573 # num instructions producing a value -system.cpu0.iew.wb_consumers 36648490 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.449752 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723211 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10116425 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 571278 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 623596 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 107842796 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.464314 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.394503 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3539791 # number of nop insts executed +system.cpu0.iew.exec_refs 15207952 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8258466 # Number of branches executed +system.cpu0.iew.exec_stores 5735212 # Number of stores executed +system.cpu0.iew.exec_rate 0.434663 # Inst execution rate +system.cpu0.iew.wb_sent 51337506 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51155506 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26224773 # num instructions producing a value +system.cpu0.iew.wb_consumers 36250862 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.428144 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723425 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9849450 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 564127 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 611071 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112190301 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.442089 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.364280 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 90117032 83.56% 83.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7061240 6.55% 90.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3809100 3.53% 93.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2021336 1.87% 95.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1578999 1.46% 96.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575276 0.53% 97.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 421394 0.39% 97.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 458654 0.43% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1799765 1.67% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 94635636 84.35% 84.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6985533 6.23% 90.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3776917 3.37% 93.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2005568 1.79% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1565673 1.40% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 565948 0.50% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418764 0.37% 98.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 453132 0.40% 98.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1783130 1.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 107842796 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50072886 # Number of instructions committed -system.cpu0.commit.committedOps 50072886 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112190301 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49598051 # Number of instructions committed +system.cpu0.commit.committedOps 49598051 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13411786 # Number of memory references committed -system.cpu0.commit.loads 7949546 # Number of loads committed -system.cpu0.commit.membars 194670 # Number of memory barriers committed -system.cpu0.commit.branches 7579863 # Number of branches committed -system.cpu0.commit.fp_insts 251347 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46348996 # Number of committed integer instructions. -system.cpu0.commit.function_calls 640938 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2909270 5.81% 5.81% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32681197 65.27% 71.08% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55117 0.11% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 25038 0.05% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8144216 16.26% 87.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5468196 10.92% 98.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 788585 1.57% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13266916 # Number of memory references committed +system.cpu0.commit.loads 7864510 # Number of loads committed +system.cpu0.commit.membars 192309 # Number of memory barriers committed +system.cpu0.commit.branches 7509354 # Number of branches committed +system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45907115 # Number of committed integer instructions. +system.cpu0.commit.function_calls 632192 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2885858 5.82% 5.82% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32387672 65.30% 71.12% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54445 0.11% 71.23% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8056819 16.24% 87.53% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5408346 10.90% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 778715 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 50072886 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1799765 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166055766 # The number of ROB reads -system.cpu0.rob.rob_writes 122136916 # The number of ROB writes -system.cpu0.timesIdled 488999 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5429418 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3697477415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47166151 # Number of Instructions Simulated -system.cpu0.committedOps 47166151 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.438816 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.438816 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.410035 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.410035 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68768616 # number of integer regfile reads -system.cpu0.int_regfile_writes 37693548 # number of integer regfile writes -system.cpu0.fp_regfile_reads 122704 # number of floating regfile reads -system.cpu0.fp_regfile_writes 131478 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1676808 # number of misc regfile reads -system.cpu0.misc_regfile_writes 792469 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1260860 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.428743 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10814422 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1261290 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.574096 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.428743 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989119 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989119 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 57625075 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 57625075 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6881291 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6881291 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3568585 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3568585 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177059 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177059 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 182551 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 182551 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10449876 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10449876 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10449876 # number of overall hits -system.cpu0.dcache.overall_hits::total 10449876 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1562512 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1562512 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1693924 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1693924 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20209 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20209 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2828 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2828 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3256436 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3256436 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3256436 # number of overall misses -system.cpu0.dcache.overall_misses::total 3256436 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38980676000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 38980676000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74553561151 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 74553561151 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 291267500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 291267500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 15945500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 15945500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 113534237151 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 113534237151 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 113534237151 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 113534237151 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8443803 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8443803 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5262509 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5262509 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 197268 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 197268 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 185379 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 185379 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13706312 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13706312 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13706312 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13706312 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.185048 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.185048 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.321885 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.321885 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102444 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102444 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015255 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015255 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.237587 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.237587 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.237587 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.237587 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24947.441044 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24947.441044 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44012.341257 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44012.341257 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14412.761641 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14412.761641 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5638.437058 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5638.437058 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34864.568857 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34864.568857 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4192146 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2471 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 109181 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.396296 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 29.771084 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 743371 # number of writebacks -system.cpu0.dcache.writebacks::total 743371 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 555767 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 555767 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1440437 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1440437 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1996204 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1996204 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1996204 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1996204 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1006745 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1006745 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253487 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 253487 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14749 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14749 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2828 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2828 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1260232 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1260232 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1260232 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1260232 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7013 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7013 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10003 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10003 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17016 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17016 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29619600000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29619600000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11703772725 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11703772725 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170858500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170858500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 13117500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 13117500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41323372725 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 41323372725 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41323372725 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 41323372725 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563340000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563340000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1563340000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1563340000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119229 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119229 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048168 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048168 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074766 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074766 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015255 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015255 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.091945 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.091945 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29421.154314 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29421.154314 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46171.096447 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46171.096447 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11584.412503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11584.412503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4638.437058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4638.437058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222920.290888 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222920.290888 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91874.706159 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91874.706159 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 908505 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.512047 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7601055 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 909016 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.361850 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28452405500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.512047 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995141 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995141 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 49598051 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1783130 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 169680194 # The number of ROB reads +system.cpu0.rob.rob_writes 120607262 # The number of ROB writes +system.cpu0.timesIdled 481372 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5579896 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3694980588 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46714728 # Number of Instructions Simulated +system.cpu0.committedOps 46714728 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.557695 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.557695 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.390977 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390977 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68002622 # number of integer regfile reads +system.cpu0.int_regfile_writes 37262146 # number of integer regfile writes +system.cpu0.fp_regfile_reads 121389 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130195 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1657828 # number of misc regfile reads +system.cpu0.misc_regfile_writes 782201 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1253317 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.016530 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10648438 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1253753 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.493250 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.016530 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988314 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988314 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 436 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 414 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.851562 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 56881554 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56881554 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6768789 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6768789 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3521179 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3521179 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174329 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174329 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179913 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 179913 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10289968 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10289968 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10289968 # number of overall hits +system.cpu0.dcache.overall_hits::total 10289968 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1553170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1553170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1684058 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1684058 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20354 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20354 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3039 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3039 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3237228 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3237228 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3237228 # number of overall misses +system.cpu0.dcache.overall_misses::total 3237228 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41477053500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41477053500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85173031211 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 85173031211 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394024000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 394024000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17098500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 17098500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 126650084711 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 126650084711 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 126650084711 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 126650084711 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8321959 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8321959 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205237 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5205237 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194683 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194683 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182952 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182952 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13527196 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13527196 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13527196 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13527196 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186635 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186635 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323531 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323531 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104549 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104549 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016611 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016611 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239313 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239313 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239313 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239313 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26704.773785 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26704.773785 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50576.067577 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50576.067577 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19358.553601 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19358.553601 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.357354 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.357354 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39123.004222 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39123.004222 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4484825 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 6096 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 108156 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 130 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.466262 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 46.892308 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 737739 # number of writebacks +system.cpu0.dcache.writebacks::total 737739 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 551343 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 551343 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432280 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1432280 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5686 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5686 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983623 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1983623 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983623 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1983623 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001827 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1001827 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251778 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251778 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14668 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14668 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3039 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3039 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1253605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1253605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1253605 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1253605 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9906 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16883 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31605979000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31605979000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13230681248 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13230681248 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170838000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170838000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14059500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14059500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44836660248 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 44836660248 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44836660248 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 44836660248 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1556905500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1556905500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1556905500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1556905500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075343 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075343 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016611 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016611 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092673 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092673 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31548.340182 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31548.340182 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52548.996529 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52548.996529 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11646.986638 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11646.986638 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.357354 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.357354 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223148.272897 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223148.272897 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92217.348812 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92217.348812 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 894430 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.352767 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7502081 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 894941 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.382766 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30333693500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352767 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994830 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994830 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9473645 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9473645 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7601055 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7601055 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7601055 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7601055 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7601055 # number of overall hits -system.cpu0.icache.overall_hits::total 7601055 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 963326 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 963326 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 963326 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 963326 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 963326 # number of overall misses -system.cpu0.icache.overall_misses::total 963326 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13819823495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13819823495 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13819823495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13819823495 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13819823495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13819823495 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8564381 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8564381 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8564381 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8564381 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8564381 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8564381 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112481 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.112481 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112481 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.112481 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112481 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.112481 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14345.946746 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14345.946746 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14345.946746 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14345.946746 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6257 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9346457 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9346457 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7502081 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7502081 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7502081 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7502081 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7502081 # number of overall hits +system.cpu0.icache.overall_hits::total 7502081 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 949140 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 949140 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 949140 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 949140 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 949140 # number of overall misses +system.cpu0.icache.overall_misses::total 949140 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13882658989 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13882658989 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13882658989 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13882658989 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13882658989 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13882658989 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8451221 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8451221 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8451221 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8451221 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8451221 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8451221 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112308 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.112308 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112308 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.112308 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112308 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.112308 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14626.566143 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14626.566143 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14626.566143 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14626.566143 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6715 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 267 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.822660 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.149813 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 908505 # number of writebacks -system.cpu0.icache.writebacks::total 908505 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54062 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54062 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54062 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54062 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54062 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54062 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909264 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 909264 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 909264 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 909264 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 909264 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 909264 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12278033496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12278033496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12278033496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12278033496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12278033496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12278033496 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.106168 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.106168 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.106168 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13503.265824 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4250134 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3659200 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 108723 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2354380 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 849662 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 894430 # number of writebacks +system.cpu0.icache.writebacks::total 894430 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53904 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53904 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 53904 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53904 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 53904 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53904 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895236 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 895236 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 895236 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 895236 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 895236 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 895236 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12277660991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12277660991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12277660991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12277660991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12277660991 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12277660991 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105930 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105930 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105930 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13714.440651 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4438770 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3818546 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 113828 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2325021 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 880835 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.088567 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 217108 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8204 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1308734 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 157441 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1151293 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 37897 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 37.885034 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 228893 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8586 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1265295 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 163281 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1102014 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 40695 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2331871 # DTB read hits -system.cpu1.dtb.read_misses 15400 # DTB read misses -system.cpu1.dtb.read_acv 73 # DTB read access violations -system.cpu1.dtb.read_accesses 429786 # DTB read accesses -system.cpu1.dtb.write_hits 1381774 # DTB write hits -system.cpu1.dtb.write_misses 3743 # DTB write misses -system.cpu1.dtb.write_acv 71 # DTB write access violations -system.cpu1.dtb.write_accesses 161427 # DTB write accesses -system.cpu1.dtb.data_hits 3713645 # DTB hits -system.cpu1.dtb.data_misses 19143 # DTB misses -system.cpu1.dtb.data_acv 144 # DTB access violations -system.cpu1.dtb.data_accesses 591213 # DTB accesses -system.cpu1.itb.fetch_hits 662529 # ITB hits -system.cpu1.itb.fetch_misses 3380 # ITB misses -system.cpu1.itb.fetch_acv 133 # ITB acv -system.cpu1.itb.fetch_accesses 665909 # ITB accesses +system.cpu1.dtb.read_hits 2431495 # DTB read hits +system.cpu1.dtb.read_misses 15697 # DTB read misses +system.cpu1.dtb.read_acv 126 # DTB read access violations +system.cpu1.dtb.read_accesses 432376 # DTB read accesses +system.cpu1.dtb.write_hits 1439190 # DTB write hits +system.cpu1.dtb.write_misses 3913 # DTB write misses +system.cpu1.dtb.write_acv 68 # DTB write access violations +system.cpu1.dtb.write_accesses 163232 # DTB write accesses +system.cpu1.dtb.data_hits 3870685 # DTB hits +system.cpu1.dtb.data_misses 19610 # DTB misses +system.cpu1.dtb.data_acv 194 # DTB access violations +system.cpu1.dtb.data_accesses 595608 # DTB accesses +system.cpu1.itb.fetch_hits 677547 # ITB hits +system.cpu1.itb.fetch_misses 3477 # ITB misses +system.cpu1.itb.fetch_acv 144 # ITB acv +system.cpu1.itb.fetch_accesses 681024 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -986,572 +981,572 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 4980 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2490 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 762354971.285141 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 386526411.344669 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2490 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 5082 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2541 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 747256549.980323 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 396382548.008070 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2541 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975501000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2490 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 8269651500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898263878500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 16541794 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2541 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8770545000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898778893500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 17543632 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6749073 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16895090 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4250134 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1224211 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 8698208 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 363130 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26231 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65753 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47571 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1900929 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 80768 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15768440 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.071450 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.476995 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7091057 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17620667 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4438770 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1273009 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9220507 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 378986 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 68380 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 52547 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1980567 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84330 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16648116 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.058418 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.465473 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12797159 81.16% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 186632 1.18% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 321640 2.04% 84.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 225512 1.43% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 384419 2.44% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 144313 0.92% 89.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 169042 1.07% 90.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 202635 1.29% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1337088 8.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 13552832 81.41% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 195919 1.18% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 328483 1.97% 84.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 235159 1.41% 85.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 403136 2.42% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 149696 0.90% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 175199 1.05% 90.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 211449 1.27% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1396243 8.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15768440 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.256933 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.021358 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5523877 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7693314 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2103455 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 273251 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 174542 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 146034 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7171 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 13792543 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22640 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 174542 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5705734 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 782365 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5725411 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2195690 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1184696 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13060888 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4153 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 107025 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 30497 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 586772 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 8670673 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 15585724 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 15521516 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 57730 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6788049 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1882616 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 491915 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 50500 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2201368 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2434805 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1482534 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 303562 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 164759 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11452007 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 560044 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10991859 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27120 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2468765 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1174488 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 414117 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15768440 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.697080 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.421678 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16648116 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253013 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.004391 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5799032 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8189176 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2194913 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 283013 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 181981 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 153262 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7666 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14395116 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 24052 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 181981 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5988192 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 920488 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6008083 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2289928 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1259442 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13629732 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4042 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 109065 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 36629 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 635484 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9050413 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16252880 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16186853 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59441 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7085651 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1964754 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 511413 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 53676 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2285701 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2541438 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1543271 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 322798 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 171550 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11950332 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 586300 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11472464 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27528 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2575040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1218372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 432674 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16648116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.689115 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.415855 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11265469 71.44% 71.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1937394 12.29% 83.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 827410 5.25% 88.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 596936 3.79% 92.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 547934 3.47% 96.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 289502 1.84% 98.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 188780 1.20% 99.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 83209 0.53% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 31806 0.20% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11949949 71.78% 71.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2021085 12.14% 83.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 863131 5.18% 89.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 621327 3.73% 92.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 572760 3.44% 96.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 302852 1.82% 98.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 196760 1.18% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 86740 0.52% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 33512 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15768440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16648116 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32091 10.27% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 173932 55.66% 65.93% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 106485 34.07% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33628 10.30% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 182347 55.85% 66.15% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 110540 33.85% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6803980 61.90% 61.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16523 0.15% 62.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 13867 0.13% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2450394 22.29% 84.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1410696 12.83% 97.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 289273 2.63% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7109835 61.97% 62.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17232 0.15% 62.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2555661 22.28% 84.58% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1468866 12.80% 97.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 299742 2.61% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10991859 # Type of FU issued -system.cpu1.iq.rate 0.664490 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 312508 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028431 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 37874505 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 14381418 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10489971 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 217280 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 104295 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 101356 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11183979 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 115637 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 113432 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11472464 # Type of FU issued +system.cpu1.iq.rate 0.653939 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 326515 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028461 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 39721820 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15008897 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10951678 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 225266 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 107813 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 104885 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11674098 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120130 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 118360 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 527848 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1066 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 5067 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 174171 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 553503 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1124 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5247 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 178223 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 475 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 99025 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 530 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 100466 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 174542 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 497039 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 226226 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 12632900 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 57966 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2434805 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1482534 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 508876 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6584 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 218362 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 5067 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 44763 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 141821 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 186584 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10809707 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2356029 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 182151 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 181981 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 560519 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 287887 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13187033 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 58459 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2541438 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1543271 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 532420 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6842 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 279702 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5247 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 45694 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 148663 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 194357 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11283035 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2456415 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 189428 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 620849 # number of nop insts executed -system.cpu1.iew.exec_refs 3747857 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1612675 # Number of branches executed -system.cpu1.iew.exec_stores 1391828 # Number of stores executed -system.cpu1.iew.exec_rate 0.653479 # Inst execution rate -system.cpu1.iew.wb_sent 10644010 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 10591327 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5073681 # num instructions producing a value -system.cpu1.iew.wb_consumers 7144079 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.640277 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710194 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2479122 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 145927 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 162123 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 15327061 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.652859 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.628724 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 650401 # number of nop insts executed +system.cpu1.iew.exec_refs 3906085 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1687752 # Number of branches executed +system.cpu1.iew.exec_stores 1449670 # Number of stores executed +system.cpu1.iew.exec_rate 0.643141 # Inst execution rate +system.cpu1.iew.wb_sent 11111703 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11056563 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5287384 # num instructions producing a value +system.cpu1.iew.wb_consumers 7447136 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.630232 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709989 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2591726 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 153626 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 169211 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16186649 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.645421 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.620431 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11704556 76.37% 76.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1675096 10.93% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 596024 3.89% 91.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 370132 2.41% 93.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 281840 1.84% 95.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 119415 0.78% 96.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 109784 0.72% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 115974 0.76% 97.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 354240 2.31% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12404611 76.63% 76.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1746252 10.79% 87.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 623750 3.85% 91.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 386653 2.39% 93.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 297145 1.84% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 125489 0.78% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 112472 0.69% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119580 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 370697 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 15327061 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10006417 # Number of instructions committed -system.cpu1.commit.committedOps 10006417 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16186649 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10447204 # Number of instructions committed +system.cpu1.commit.committedOps 10447204 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3215320 # Number of memory references committed -system.cpu1.commit.loads 1906957 # Number of loads committed -system.cpu1.commit.membars 46297 # Number of memory barriers committed -system.cpu1.commit.branches 1432968 # Number of branches committed -system.cpu1.commit.fp_insts 99355 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9296453 # Number of committed integer instructions. -system.cpu1.commit.function_calls 155642 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 467886 4.68% 4.68% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5954632 59.51% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16225 0.16% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13860 0.14% 64.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1953254 19.52% 84.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1308912 13.08% 97.11% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 289273 2.89% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3352983 # Number of memory references committed +system.cpu1.commit.loads 1987935 # Number of loads committed +system.cpu1.commit.membars 48912 # Number of memory barriers committed +system.cpu1.commit.branches 1499265 # Number of branches committed +system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9704534 # Number of committed integer instructions. +system.cpu1.commit.function_calls 163857 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 490367 4.69% 4.69% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6221313 59.55% 64.24% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16935 0.16% 64.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2036847 19.50% 84.06% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1365632 13.07% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 299742 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 10006417 # Class of committed instruction -system.cpu1.commit.bw_lim_events 354240 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 27350454 # The number of ROB reads -system.cpu1.rob.rob_writes 25410376 # The number of ROB writes -system.cpu1.timesIdled 127916 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 773354 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3796525267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9543281 # Number of Instructions Simulated -system.cpu1.committedOps 9543281 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.733345 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.733345 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.576919 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.576919 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13915898 # number of integer regfile reads -system.cpu1.int_regfile_writes 7574327 # number of integer regfile writes -system.cpu1.fp_regfile_reads 57027 # number of floating regfile reads -system.cpu1.fp_regfile_writes 56084 # number of floating regfile writes -system.cpu1.misc_regfile_reads 548336 # number of misc regfile reads -system.cpu1.misc_regfile_writes 233992 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 125899 # number of replacements -system.cpu1.dcache.tags.tagsinuse 488.643443 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2930828 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 126411 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.184913 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 47496090500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.643443 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954382 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.954382 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10447204 # Class of committed instruction +system.cpu1.commit.bw_lim_events 370697 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 28744557 # The number of ROB reads +system.cpu1.rob.rob_writes 26537349 # The number of ROB writes +system.cpu1.timesIdled 134728 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 895516 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3797555246 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9961587 # Number of Instructions Simulated +system.cpu1.committedOps 9961587 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.761128 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.761128 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.567818 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.567818 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 14521823 # number of integer regfile reads +system.cpu1.int_regfile_writes 7909607 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58779 # number of floating regfile reads +system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes +system.cpu1.misc_regfile_reads 571518 # number of misc regfile reads +system.cpu1.misc_regfile_writes 244969 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 130966 # number of replacements +system.cpu1.dcache.tags.tagsinuse 487.964655 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3061418 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 131478 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.284641 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 49531315500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.964655 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.953056 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.953056 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13906652 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13906652 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1865609 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1865609 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 981966 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 981966 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 38120 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 38120 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 34857 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 34857 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2847575 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2847575 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2847575 # number of overall hits -system.cpu1.dcache.overall_hits::total 2847575 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 231819 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 231819 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 282423 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 282423 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5078 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5078 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2912 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2912 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 514242 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 514242 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 514242 # number of overall misses -system.cpu1.dcache.overall_misses::total 514242 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3027811000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3027811000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10676531998 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10676531998 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51207500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 51207500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 16199500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 16199500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13704342998 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13704342998 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13704342998 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13704342998 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2097428 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2097428 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1264389 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1264389 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 43198 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 43198 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 37769 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 37769 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3361817 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3361817 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3361817 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3361817 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110525 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.110525 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223367 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.223367 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117552 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117552 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.077100 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.077100 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152965 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.152965 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152965 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.152965 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13061.099392 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13061.099392 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37803.337540 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37803.337540 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10084.186688 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10084.186688 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5563.015110 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5563.015110 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26649.598823 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26649.598823 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 625764 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 300 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24254 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.800445 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 15.789474 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 81179 # number of writebacks -system.cpu1.dcache.writebacks::total 81179 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 142547 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 142547 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 235954 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 235954 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 779 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 779 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 378501 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 378501 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 378501 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 378501 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 89272 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 89272 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 46469 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 46469 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4299 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4299 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2912 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2912 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 135741 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 135741 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 135741 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 135741 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 182 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 182 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3016 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3016 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3198 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3198 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1142608000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1142608000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1700967690 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1700967690 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38610000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38610000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 13287500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 13287500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2843575690 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2843575690 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2843575690 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2843575690 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 35749500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 35749500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 35749500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 35749500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042563 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042563 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036752 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036752 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.099518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.077100 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.077100 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040377 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040377 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12799.175553 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12799.175553 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36604.353225 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36604.353225 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8981.158409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8981.158409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4563.015110 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4563.015110 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196425.824176 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196425.824176 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11178.705441 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11178.705441 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 243897 # number of replacements -system.cpu1.icache.tags.tagsinuse 471.203096 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1645008 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 244406 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.730637 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1879506005500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.203096 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920319 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.920319 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2145410 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2145410 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1645008 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1645008 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1645008 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1645008 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1645008 # number of overall hits -system.cpu1.icache.overall_hits::total 1645008 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 255921 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 255921 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 255921 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 255921 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 255921 # number of overall misses -system.cpu1.icache.overall_misses::total 255921 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3476894499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3476894499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3476894499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3476894499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3476894499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3476894499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1900929 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1900929 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1900929 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1900929 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1900929 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1900929 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.134629 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.134629 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.134629 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.134629 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.134629 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.134629 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13585.811633 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13585.811633 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13585.811633 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13585.811633 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 470 # number of cycles access was blocked +system.cpu1.dcache.tags.tag_accesses 14512669 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14512669 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1946433 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1946433 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1026063 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1026063 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40785 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40785 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37242 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 37242 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2972496 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2972496 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2972496 # number of overall hits +system.cpu1.dcache.overall_hits::total 2972496 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 241711 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 241711 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 292248 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 292248 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5308 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5308 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3094 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3094 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 533959 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 533959 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 533959 # number of overall misses +system.cpu1.dcache.overall_misses::total 533959 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3394927000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3394927000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12114051455 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12114051455 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54394000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 54394000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17165000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 17165000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15508978455 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15508978455 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15508978455 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15508978455 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2188144 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2188144 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318311 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1318311 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46093 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46093 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40336 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 40336 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3506455 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3506455 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3506455 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3506455 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110464 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110464 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221684 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.221684 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115158 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115158 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076706 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076706 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152279 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152279 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152279 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152279 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14045.397189 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14045.397189 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41451.272395 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41451.272395 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10247.550867 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10247.550867 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5547.834518 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5547.834518 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29045.260881 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29045.260881 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 715753 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 884 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24925 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.716269 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 84601 # number of writebacks +system.cpu1.dcache.writebacks::total 84601 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148639 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 148639 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243827 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 243827 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 846 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 846 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 392466 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 392466 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 392466 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 392466 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93072 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 93072 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48421 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 48421 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4462 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4462 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3093 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3093 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 141493 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 141493 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 141493 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 141493 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3153 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3371 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262526500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262526500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1947214752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1947214752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40086500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40086500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14072000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14072000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3209741252 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3209741252 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3209741252 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3209741252 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41866500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41866500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41866500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41866500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042535 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042535 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096804 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096804 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076681 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076681 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040352 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040352 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13565.051788 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13565.051788 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40214.261416 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40214.261416 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8983.975796 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8983.975796 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.628193 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.628193 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192048.165138 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192048.165138 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12419.608425 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12419.608425 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 256896 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.782709 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1710963 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 257408 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.646891 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1882016787500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.782709 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919497 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919497 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 2238053 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2238053 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1710963 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1710963 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1710963 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1710963 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1710963 # number of overall hits +system.cpu1.icache.overall_hits::total 1710963 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 269604 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 269604 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 269604 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 269604 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 269604 # number of overall misses +system.cpu1.icache.overall_misses::total 269604 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3754413998 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3754413998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3754413998 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3754413998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3754413998 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3754413998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1980567 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1980567 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1980567 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1980567 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1980567 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1980567 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136125 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.136125 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136125 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.136125 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136125 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.136125 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13925.661333 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13925.661333 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13925.661333 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13925.661333 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 473 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.368421 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.261905 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 243897 # number of writebacks -system.cpu1.icache.writebacks::total 243897 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11440 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 11440 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 11440 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 11440 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 11440 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 11440 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244481 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 244481 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 244481 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 244481 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 244481 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 244481 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3131245499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3131245499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3131245499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3131245499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3131245499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3131245499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.128611 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.128611 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.128611 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12807.725341 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 256896 # number of writebacks +system.cpu1.icache.writebacks::total 256896 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12118 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12118 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12118 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12118 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12118 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12118 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257486 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 257486 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 257486 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 257486 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 257486 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 257486 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3368066498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3368066498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3368066498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3368066498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3368066498 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3368066498 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.130006 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.130006 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.130006 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13080.581072 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1564,12 +1559,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7374 # Transaction distribution system.iobus.trans_dist::ReadResp 7374 # Transaction distribution -system.iobus.trans_dist::WriteReq 54571 # Transaction distribution -system.iobus.trans_dist::WriteResp 54571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11828 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54611 # Transaction distribution +system.iobus.trans_dist::WriteResp 54611 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11908 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1578,11 +1573,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40508 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123890 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1591,50 +1586,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73858 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735194 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12271500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735514 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12353502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 824500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14105000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13988000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6057000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6060500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216200796 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216282007 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27409000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.499134 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.490946 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712299837000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.499134 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031196 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031196 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714262123000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.490946 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030684 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030684 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1643,14 +1638,14 @@ system.iocache.demand_misses::tsunami.ide 41731 # n system.iocache.demand_misses::total 41731 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22562883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22562883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858746913 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858746913 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4881309796 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4881309796 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4881309796 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4881309796 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22774383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22774383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4918988624 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4918988624 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4941763007 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4941763007 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4941763007 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4941763007 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1667,19 +1662,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126049.625698 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126049.625698 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116931.722011 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116931.722011 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116970.832139 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116970.832139 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127231.189944 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 127231.189944 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118381.512899 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118381.512899 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118419.472502 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118419.472502 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1165 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 145.625000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks @@ -1691,14 +1686,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41731 system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13612883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13612883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778734565 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778734565 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2792347448 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2792347448 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2792347448 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2792347448 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13824383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13824383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2838948426 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2838948426 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2852772809 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2852772809 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2852772809 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2852772809 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1707,200 +1702,200 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76049.625698 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76049.625698 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66873.665889 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66873.665889 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66913.025041 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66913.025041 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66913.025041 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66913.025041 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 345621 # number of replacements -system.l2c.tags.tagsinuse 65429.949099 # Cycle average of tags in use -system.l2c.tags.total_refs 4347999 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411104 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.576397 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 5987439000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 292.894251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5335.962916 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58874.943819 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 203.860157 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 722.287955 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004469 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081420 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.898360 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011021 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998382 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65483 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1723 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1817 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5637 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56151 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999191 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38487323 # Number of tag accesses -system.l2c.tags.data_accesses 38487323 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 824550 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 824550 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 880861 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 880861 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 2842 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1401 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4243 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 470 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 444 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 914 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 147625 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 30184 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 177809 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 895088 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 243149 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1138237 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 727494 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 80955 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 808449 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 895088 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 875119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 243149 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 111139 # number of demand (read+write) hits -system.l2c.demand_hits::total 2124495 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 895088 # number of overall hits -system.l2c.overall_hits::cpu0.data 875119 # number of overall hits -system.l2c.overall_hits::cpu1.inst 243149 # number of overall hits -system.l2c.overall_hits::cpu1.data 111139 # number of overall hits -system.l2c.overall_hits::total 2124495 # number of overall hits +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77231.189944 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 77231.189944 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68322.786533 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68322.786533 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 345941 # number of replacements +system.l2c.tags.tagsinuse 65423.095027 # Cycle average of tags in use +system.l2c.tags.total_refs 4335515 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411463 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.536828 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6416575000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 293.307825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5315.079150 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58827.069962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 210.319847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 777.318243 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004476 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081102 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.897630 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003209 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011861 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998277 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1694 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1843 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5673 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56180 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 38390429 # Number of tag accesses +system.l2c.tags.data_accesses 38390429 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 822340 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 822340 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 875169 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 875169 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1494 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 4357 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 467 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 968 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 145988 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 30963 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 176951 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 881644 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 255533 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1137177 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 722233 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 84048 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 806281 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 881644 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 868221 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 255533 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 115011 # number of demand (read+write) hits +system.l2c.demand_hits::total 2120409 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 881644 # number of overall hits +system.l2c.overall_hits::cpu0.data 868221 # number of overall hits +system.l2c.overall_hits::cpu1.inst 255533 # number of overall hits +system.l2c.overall_hits::cpu1.data 115011 # number of overall hits +system.l2c.overall_hits::total 2120409 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 6 # 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average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210417.938115 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183925.824176 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209747.810980 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86721.967560 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10467.323327 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74657.935094 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 850516 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 398567 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 435 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93561.900643 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 115771.239121 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95764.396687 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90231.858002 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71490.593495 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107172.606925 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71745.854000 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210644.188046 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179548.165138 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209702.015288 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87049.961500 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11611.242955 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74494.223363 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 852108 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 399805 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 437 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 297176 # Transaction distribution -system.membus.trans_dist::WriteReq 13019 # Transaction distribution -system.membus.trans_dist::WriteResp 13019 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123513 # Transaction distribution -system.membus.trans_dist::CleanEvict 262911 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6111 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4826 # Transaction distribution +system.membus.trans_dist::ReadResp 297167 # Transaction distribution +system.membus.trans_dist::WriteReq 13059 # Transaction distribution +system.membus.trans_dist::WriteResp 13059 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123616 # Transaction distribution +system.membus.trans_dist::CleanEvict 263125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6609 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5164 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121549 # Transaction distribution -system.membus.trans_dist::ReadExResp 121146 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290030 # Transaction distribution -system.membus.trans_dist::BadAddressError 49 # Transaction distribution +system.membus.trans_dist::ReadExReq 121953 # Transaction distribution +system.membus.trans_dist::ReadExResp 121548 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 290016 # Transaction distribution +system.membus.trans_dist::BadAddressError 44 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40428 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1177677 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 98 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1218203 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40508 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 88 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1220212 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1301648 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73538 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31530048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31603586 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1303657 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73858 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31561664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31635522 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34261826 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 11676 # Total snoops (count) -system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 484282 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001355 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036780 # Request fanout histogram +system.membus.pkt_size::total 34293762 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12507 # Total snoops (count) +system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 485548 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001427 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037752 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 483626 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 656 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484855 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 693 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 484282 # Request fanout histogram -system.membus.reqLayer0.occupancy 36370000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 485548 # Request fanout histogram +system.membus.reqLayer0.occupancy 36350498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1352579532 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1353965073 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 62000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2178718000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2179761000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 960113 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 960863 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5113699 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2556514 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 337557 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1071 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5108724 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2554049 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 343728 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2265500 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13019 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13019 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 906543 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1152402 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825837 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10249 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5740 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15989 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 300358 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 300358 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1153745 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1104612 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 49 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 203 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2726862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3834313 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 401077 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7695072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116326272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128153608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31253696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13151546 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288885122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 379909 # Total snoops (count) -system.toL2Bus.snoopTraffic 6725760 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2940742 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.121053 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.326514 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2263429 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13059 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13059 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 904436 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1151326 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 825788 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10854 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6132 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16986 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 300014 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 300014 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1152722 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1103559 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 44 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 238 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2684715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3812301 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771824 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417816 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7686656 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114526656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127297140 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32917632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13697806 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288439234 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382362 # Total snoops (count) +system.toL2Bus.snoopTraffic 6813696 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2939714 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.123574 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.329478 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2585068 87.91% 87.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 355364 12.08% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 309 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2576793 87.65% 87.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 362587 12.33% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 316 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 18 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2940742 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4550461413 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2939714 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4544765338 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1365446887 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1344393906 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1921756875 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1911305093 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 368286347 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 387758410 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 208891088 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 217734513 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2184,194 +2179,194 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6504 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 179089 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 63660 40.34% 40.34% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.42% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.22% 41.64% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 175 0.11% 41.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 91921 58.25% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 157813 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 62631 49.19% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.51% 50.81% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 175 0.14% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 62456 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 127319 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863112245000 97.74% 97.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 65536000 0.00% 97.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 577434000 0.03% 97.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 84972500 0.00% 97.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42413276000 2.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906253463500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983836 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6475 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 176726 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 62785 40.28% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.23% 41.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 90860 58.29% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 155882 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 61770 49.18% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.53% 50.82% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61589 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862335551000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64321000 0.00% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 576343500 0.03% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 87551500 0.00% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 44167527000 2.32% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907231294000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983834 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679453 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.806771 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed -system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed -system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed -system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed -system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed -system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed -system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed -system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed -system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed -system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed -system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed -system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 178 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.677845 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.805712 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 4.14% 4.14% # number of syscalls executed +system.cpu0.kern.syscall::3 14 8.28% 12.43% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.37% 14.79% # number of syscalls executed +system.cpu0.kern.syscall::6 26 15.38% 30.18% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.59% 30.77% # number of syscalls executed +system.cpu0.kern.syscall::17 5 2.96% 33.73% # number of syscalls executed +system.cpu0.kern.syscall::19 7 4.14% 37.87% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.37% 40.24% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.59% 40.83% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.78% 42.60% # number of syscalls executed +system.cpu0.kern.syscall::33 5 2.96% 45.56% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.18% 46.75% # number of syscalls executed +system.cpu0.kern.syscall::45 26 15.38% 62.13% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.78% 63.91% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.73% 68.64% # number of syscalls executed +system.cpu0.kern.syscall::54 8 4.73% 73.37% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.55% 76.92% # number of syscalls executed +system.cpu0.kern.syscall::71 15 8.88% 85.80% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.78% 87.57% # number of syscalls executed +system.cpu0.kern.syscall::74 3 1.78% 89.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.59% 89.94% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.18% 91.12% # number of syscalls executed +system.cpu0.kern.syscall::92 7 4.14% 95.27% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.18% 96.45% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.18% 97.63% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.59% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.59% 98.82% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.18% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 169 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 278 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3399 2.05% 2.22% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.25% # number of callpals executed +system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151231 91.28% 93.54% # number of callpals executed -system.cpu0.kern.callpal::rdps 5900 3.56% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::swpipl 149333 91.35% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 5683 3.48% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed -system.cpu0.kern.callpal::rti 4349 2.63% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rti 4311 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 165676 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6738 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches +system.cpu0.kern.callpal::total 163475 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6664 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1097 -system.cpu0.kern.mode_good::user 1097 +system.cpu0.kern.mode_good::kernel 1070 +system.cpu0.kern.mode_good::user 1070 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162808 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.160564 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280026 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904214078500 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1672761500 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.276700 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1905216688000 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1682440000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3400 # number of times the context was actually changed +system.cpu0.kern.swap_context 3350 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2490 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 60423 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18641 37.27% 37.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 3.85% 41.12% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 278 0.56% 41.67% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 29176 58.33% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 50020 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 18293 47.50% 47.50% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.00% 52.50% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 278 0.72% 53.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18016 46.78% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 38512 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1873859043000 98.29% 98.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 564907000 0.03% 98.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 133677500 0.01% 98.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31975089500 1.68% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1906532717000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981331 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2541 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 62895 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 19560 37.60% 37.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.70% 41.30% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 30244 58.14% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 52021 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 19198 47.61% 47.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 4.77% 52.38% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18906 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 40321 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872948111000 98.19% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 564456500 0.03% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141435000 0.01% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33894599000 1.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907548601500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981493 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.617494 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769932 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed -system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed -system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed -system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed -system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed -system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed -system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed -system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed -system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 148 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.625116 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.775091 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.64% 0.64% # number of syscalls executed +system.cpu1.kern.syscall::3 16 10.19% 10.83% # number of syscalls executed +system.cpu1.kern.syscall::6 16 10.19% 21.02% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.64% 21.66% # number of syscalls executed +system.cpu1.kern.syscall::17 10 6.37% 28.03% # number of syscalls executed +system.cpu1.kern.syscall::19 3 1.91% 29.94% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.27% 31.21% # number of syscalls executed +system.cpu1.kern.syscall::23 3 1.91% 33.12% # number of syscalls executed +system.cpu1.kern.syscall::24 3 1.91% 35.03% # number of syscalls executed +system.cpu1.kern.syscall::33 6 3.82% 38.85% # number of syscalls executed +system.cpu1.kern.syscall::45 28 17.83% 56.69% # number of syscalls executed +system.cpu1.kern.syscall::47 3 1.91% 58.60% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.27% 59.87% # number of syscalls executed +system.cpu1.kern.syscall::54 2 1.27% 61.15% # number of syscalls executed +system.cpu1.kern.syscall::58 1 0.64% 61.78% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.64% 62.42% # number of syscalls executed +system.cpu1.kern.syscall::71 39 24.84% 87.26% # number of syscalls executed +system.cpu1.kern.syscall::74 13 8.28% 95.54% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.64% 96.18% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.27% 97.45% # number of syscalls executed +system.cpu1.kern.syscall::132 3 1.91% 99.36% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.64% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 157 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 175 0.33% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1166 2.23% 2.57% # number of callpals executed -system.cpu1.kern.callpal::tbi 5 0.01% 2.58% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.59% # number of callpals executed -system.cpu1.kern.callpal::swpipl 44628 85.35% 87.94% # number of callpals executed -system.cpu1.kern.callpal::rdps 2858 5.47% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.42% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed -system.cpu1.kern.callpal::rti 3189 6.10% 99.52% # number of callpals executed -system.cpu1.kern.callpal::callsys 200 0.38% 99.91% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed +system.cpu1.kern.callpal::swpipl 46558 85.31% 87.92% # number of callpals executed +system.cpu1.kern.callpal::rdps 3077 5.64% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed +system.cpu1.kern.callpal::wrusp 6 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::rti 3246 5.95% 99.52% # number of callpals executed +system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 52290 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1624 # number of protection mode switches -system.cpu1.kern.mode_switch::user 640 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2399 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 844 -system.cpu1.kern.mode_good::user 640 -system.cpu1.kern.mode_good::idle 204 -system.cpu1.kern.mode_switch_good::kernel 0.519704 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 54577 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1699 # number of protection mode switches +system.cpu1.kern.mode_switch::user 669 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2429 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 888 +system.cpu1.kern.mode_good::user 669 +system.cpu1.kern.mode_good::idle 219 +system.cpu1.kern.mode_switch_good::kernel 0.522660 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.085035 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.361999 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4862135000 0.26% 0.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1013458000 0.05% 0.31% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1900657116000 99.69% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1167 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090161 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370231 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5315508000 0.28% 0.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1058693000 0.06% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1901174392500 99.67% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1229 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index 7e0283697..a10880583 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 |