diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 2056 |
1 files changed, 1035 insertions, 1021 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index eda12d3cf..f07e7eac0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860188 # Number of seconds simulated -sim_ticks 1860187818000 # Number of ticks simulated -final_tick 1860187818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860172 # Number of seconds simulated +sim_ticks 1860172195000 # Number of ticks simulated +final_tick 1860172195000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129673 # Simulator instruction rate (inst/s) -host_op_rate 129673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4553007725 # Simulator tick rate (ticks/s) -host_mem_usage 348812 # Number of bytes of host memory used -host_seconds 408.56 # Real time elapsed on the host -sim_insts 52979638 # Number of instructions simulated -sim_ops 52979638 # Number of ops (including micro ops) simulated +host_inst_rate 152063 # Simulator instruction rate (inst/s) +host_op_rate 152063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5340733222 # Simulator tick rate (ticks/s) +host_mem_usage 304984 # Number of bytes of host memory used +host_seconds 348.30 # Real time elapsed on the host +sim_insts 52963419 # Number of instructions simulated +sim_ops 52963419 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 963200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 965120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516608 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388771 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 965120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445263 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117447 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117447 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13375716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15319331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517797 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517797 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13375716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19360110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445263 # Number of read requests accepted -system.physmem.writeReqs 117447 # Number of write requests accepted -system.physmem.readBursts 445263 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117447 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28490624 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 7515520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28496832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7516608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 445258 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117433 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117433 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15319287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445258 # Number of read requests accepted +system.physmem.writeReqs 117433 # Number of write requests accepted +system.physmem.readBursts 445258 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117433 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28490432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue +system.physmem.bytesWritten 7513664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28496512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7515712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 171 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28211 # Per bank write bursts -system.physmem.perBankRdBursts::1 27992 # Per bank write bursts -system.physmem.perBankRdBursts::2 28433 # Per bank write bursts -system.physmem.perBankRdBursts::3 27987 # Per bank write bursts -system.physmem.perBankRdBursts::4 27796 # Per bank write bursts -system.physmem.perBankRdBursts::5 27217 # Per bank write bursts -system.physmem.perBankRdBursts::6 27269 # Per bank write bursts -system.physmem.perBankRdBursts::7 27319 # Per bank write bursts -system.physmem.perBankRdBursts::8 27690 # Per bank write bursts -system.physmem.perBankRdBursts::9 27272 # Per bank write bursts -system.physmem.perBankRdBursts::10 28021 # Per bank write bursts -system.physmem.perBankRdBursts::11 27509 # Per bank write bursts -system.physmem.perBankRdBursts::12 27548 # Per bank write bursts -system.physmem.perBankRdBursts::13 28237 # Per bank write bursts -system.physmem.perBankRdBursts::14 28335 # Per bank write bursts -system.physmem.perBankRdBursts::15 28330 # Per bank write bursts -system.physmem.perBankWrBursts::0 7921 # Per bank write bursts -system.physmem.perBankWrBursts::1 7511 # Per bank write bursts -system.physmem.perBankWrBursts::2 7946 # Per bank write bursts -system.physmem.perBankWrBursts::3 7492 # Per bank write bursts -system.physmem.perBankWrBursts::4 7346 # Per bank write bursts -system.physmem.perBankWrBursts::5 6678 # Per bank write bursts -system.physmem.perBankWrBursts::6 6778 # Per bank write bursts -system.physmem.perBankWrBursts::7 6711 # Per bank write bursts -system.physmem.perBankWrBursts::8 7130 # Per bank write bursts -system.physmem.perBankWrBursts::9 6681 # Per bank write bursts -system.physmem.perBankWrBursts::10 7414 # Per bank write bursts -system.physmem.perBankWrBursts::11 6966 # Per bank write bursts -system.physmem.perBankWrBursts::12 7109 # Per bank write bursts -system.physmem.perBankWrBursts::13 7879 # Per bank write bursts -system.physmem.perBankWrBursts::14 8056 # Per bank write bursts -system.physmem.perBankWrBursts::15 7812 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 176 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28223 # Per bank write bursts +system.physmem.perBankRdBursts::1 27968 # Per bank write bursts +system.physmem.perBankRdBursts::2 28292 # Per bank write bursts +system.physmem.perBankRdBursts::3 27927 # Per bank write bursts +system.physmem.perBankRdBursts::4 27805 # Per bank write bursts +system.physmem.perBankRdBursts::5 27242 # Per bank write bursts +system.physmem.perBankRdBursts::6 27352 # Per bank write bursts +system.physmem.perBankRdBursts::7 27274 # Per bank write bursts +system.physmem.perBankRdBursts::8 27691 # Per bank write bursts +system.physmem.perBankRdBursts::9 27508 # Per bank write bursts +system.physmem.perBankRdBursts::10 27933 # Per bank write bursts +system.physmem.perBankRdBursts::11 27527 # Per bank write bursts +system.physmem.perBankRdBursts::12 27552 # Per bank write bursts +system.physmem.perBankRdBursts::13 28225 # Per bank write bursts +system.physmem.perBankRdBursts::14 28330 # Per bank write bursts +system.physmem.perBankRdBursts::15 28314 # Per bank write bursts +system.physmem.perBankWrBursts::0 7932 # Per bank write bursts +system.physmem.perBankWrBursts::1 7496 # Per bank write bursts +system.physmem.perBankWrBursts::2 7821 # Per bank write bursts +system.physmem.perBankWrBursts::3 7427 # Per bank write bursts +system.physmem.perBankWrBursts::4 7353 # Per bank write bursts +system.physmem.perBankWrBursts::5 6703 # Per bank write bursts +system.physmem.perBankWrBursts::6 6854 # Per bank write bursts +system.physmem.perBankWrBursts::7 6665 # Per bank write bursts +system.physmem.perBankWrBursts::8 7118 # Per bank write bursts +system.physmem.perBankWrBursts::9 6889 # Per bank write bursts +system.physmem.perBankWrBursts::10 7323 # Per bank write bursts +system.physmem.perBankWrBursts::11 6981 # Per bank write bursts +system.physmem.perBankWrBursts::12 7116 # Per bank write bursts +system.physmem.perBankWrBursts::13 7874 # Per bank write bursts +system.physmem.perBankWrBursts::14 8055 # Per bank write bursts +system.physmem.perBankWrBursts::15 7794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1860182401000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1860166839000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445263 # Read request sizes (log2) +system.physmem.readPktSize::6 445258 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117447 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2192 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117433 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2195 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,128 +148,128 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 564.805095 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 351.189585 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.649920 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13350 20.94% 20.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10335 16.21% 37.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4789 7.51% 44.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2797 4.39% 49.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2437 3.82% 52.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.47% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1469 2.30% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1613 2.53% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25383 39.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63749 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6887 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.637723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.523346 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2544.314640 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6884 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 565.384925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 351.672479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.574374 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13299 20.88% 20.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10397 16.33% 37.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4628 7.27% 44.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2746 4.31% 48.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2553 4.01% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1655 2.60% 55.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1376 2.16% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1696 2.66% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25330 39.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 64.625581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 16.554610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2544.325145 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6885 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6887 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6887 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.050966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.814496 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.834643 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5493 79.76% 79.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 28 0.41% 80.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 690 10.02% 90.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 216 3.14% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 116 1.68% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 20 0.29% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 25 0.36% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 93 1.35% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 19 0.28% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 44 0.64% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.16% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 7 0.10% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 8 0.12% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 16 0.23% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.03% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 14 0.20% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 9 0.13% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 3 0.04% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.03% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.03% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 7 0.10% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 4 0.06% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 3 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 1 0.01% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 3 0.04% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 3 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 7 0.10% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 17 0.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6887 # Writes before turning the bus around for reads -system.physmem.totQLat 8647566500 # Total ticks spent queuing -system.physmem.totMemAccLat 16994429000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225830000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19425.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6888 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6888 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044280 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.812634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.762583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5511 80.01% 80.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 31 0.45% 80.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 662 9.61% 90.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 220 3.19% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 110 1.60% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 25 0.36% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 25 0.36% 95.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 91 1.32% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 31 0.45% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 12 0.17% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 22 0.32% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.09% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.20% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.04% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 16 0.23% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 12 0.17% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 7 0.10% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 4 0.06% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.06% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 6 0.09% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 3 0.04% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 3 0.04% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 8 0.12% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 12 0.17% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6888 # Writes before turning the bus around for reads +system.physmem.totQLat 8740437500 # Total ticks spent queuing +system.physmem.totMemAccLat 17087243750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19634.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38175.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38384.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s @@ -278,64 +278,65 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.02 # Average write queue length when enqueuing -system.physmem.readRowHits 403062 # Number of row buffer hits during reads -system.physmem.writeRowHits 95784 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.56 # Row buffer hit rate for writes -system.physmem.avgGap 3305756.79 # Average gap between requests -system.physmem.pageHitRate 88.67 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1761433244000 # Time in different power states -system.physmem.memoryStateTime::REF 62115560000 # Time in different power states +system.physmem.avgRdQLen 1.65 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.75 # Average write queue length when enqueuing +system.physmem.readRowHits 403028 # Number of row buffer hits during reads +system.physmem.writeRowHits 95855 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.63 # Row buffer hit rate for writes +system.physmem.avgGap 3305840.75 # Average gap between requests +system.physmem.pageHitRate 88.68 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761575145500 # Time in different power states +system.physmem.memoryStateTime::REF 62115040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 36633312250 # Time in different power states +system.physmem.memoryStateTime::ACT 36476358250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19402968 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295944 # Transaction distribution -system.membus.trans_dist::ReadResp 295866 # Transaction distribution +system.membus.throughput 19402477 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295985 # Transaction distribution +system.membus.trans_dist::ReadResp 295900 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117447 # Transaction distribution -system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 156883 # Transaction distribution -system.membus.trans_dist::ReadExResp 156883 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.trans_dist::Writeback 117433 # Transaction distribution +system.membus.trans_dist::UpgradeReq 178 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 179 # Transaction distribution +system.membus.trans_dist::ReadExReq 156844 # Transaction distribution +system.membus.trans_dist::ReadExResp 156844 # Transaction distribution +system.membus.trans_dist::BadAddressError 85 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704384 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748524 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30703168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30747308 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36057580 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36057580 # Total data (bytes) +system.membus.tot_pkt_size::total 36056364 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36056364 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29864500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29838500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1548275500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1526200750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 98000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 104500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3770327047 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3755175800 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376611244 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376659242 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261115 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.260971 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710335896000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261115 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710335831000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260971 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078811 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078811 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -349,14 +350,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21272883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21272883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12456693929 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12456693929 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12477966812 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12477966812 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12477966812 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12477966812 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12441682213 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12441682213 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12462816596 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12462816596 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12462816596 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12462816596 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -373,19 +374,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122964.641618 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299785.664445 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 299052.529946 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 299052.529946 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 365915 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299424.389031 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299424.389031 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 298689.433098 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 298689.433098 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 366119 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28370 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28395 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.897956 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.893784 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -399,14 +400,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12274883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12274883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10293819441 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10293819441 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10306094324 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10306094324 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10306094324 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10306094324 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10278710729 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10278710729 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10290848112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10290848112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10290848112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10290848112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -415,14 +416,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247369.819239 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247369.819239 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -436,36 +437,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13846630 # Number of BP lookups -system.cpu.branchPred.condPredicted 11622667 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 398238 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9513264 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5817388 # Number of BTB hits +system.cpu.branchPred.lookups 13973676 # Number of BP lookups +system.cpu.branchPred.condPredicted 11739131 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 397652 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9590938 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5932533 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.150284 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 900921 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39034 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.855608 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 905503 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38808 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9912884 # DTB read hits -system.cpu.dtb.read_misses 41215 # DTB read misses -system.cpu.dtb.read_acv 553 # DTB read access violations -system.cpu.dtb.read_accesses 941108 # DTB read accesses -system.cpu.dtb.write_hits 6599017 # DTB write hits -system.cpu.dtb.write_misses 10339 # DTB write misses -system.cpu.dtb.write_acv 401 # DTB write access violations -system.cpu.dtb.write_accesses 338138 # DTB write accesses -system.cpu.dtb.data_hits 16511901 # DTB hits -system.cpu.dtb.data_misses 51554 # DTB misses -system.cpu.dtb.data_acv 954 # DTB access violations -system.cpu.dtb.data_accesses 1279246 # DTB accesses -system.cpu.itb.fetch_hits 1308304 # ITB hits -system.cpu.itb.fetch_misses 36786 # ITB misses -system.cpu.itb.fetch_acv 1079 # ITB acv -system.cpu.itb.fetch_accesses 1345090 # ITB accesses +system.cpu.dtb.read_hits 10112222 # DTB read hits +system.cpu.dtb.read_misses 41745 # DTB read misses +system.cpu.dtb.read_acv 542 # DTB read access violations +system.cpu.dtb.read_accesses 945441 # DTB read accesses +system.cpu.dtb.write_hits 6611008 # DTB write hits +system.cpu.dtb.write_misses 10791 # DTB write misses +system.cpu.dtb.write_acv 413 # DTB write access violations +system.cpu.dtb.write_accesses 339727 # DTB write accesses +system.cpu.dtb.data_hits 16723230 # DTB hits +system.cpu.dtb.data_misses 52536 # DTB misses +system.cpu.dtb.data_acv 955 # DTB access violations +system.cpu.dtb.data_accesses 1285168 # DTB accesses +system.cpu.itb.fetch_hits 1309723 # ITB hits +system.cpu.itb.fetch_misses 39683 # ITB misses +system.cpu.itb.fetch_acv 1073 # ITB acv +system.cpu.itb.fetch_accesses 1349406 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -478,303 +479,304 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121969353 # number of cpu cycles simulated +system.cpu.numCycles 121578156 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28022459 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70674133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13846630 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6718309 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13243332 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1983249 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37995640 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254581 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364654 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8542175 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264688 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81194854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870426 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.213908 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28154197 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 72069959 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13973676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6838036 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13462286 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2111809 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36504135 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 258219 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 367287 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8654218 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283642 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80169891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.898965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.245398 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67951522 83.69% 83.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854853 1.05% 84.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1698258 2.09% 86.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 823227 1.01% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2753963 3.39% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 558188 0.69% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 642929 0.79% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1006595 1.24% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4905319 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66707605 83.21% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 850391 1.06% 84.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1701562 2.12% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 829510 1.03% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2814732 3.51% 90.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 566680 0.71% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 649069 0.81% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1061564 1.32% 93.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4988778 6.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81194854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113525 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.579442 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29206421 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37679452 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12104138 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 965352 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1239490 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585042 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69357398 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129450 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1239490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30354385 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13996332 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19984766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11324382 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4295497 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65588313 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7118 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505148 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1530678 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43795306 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79617271 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79438234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5615089 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682372 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239607 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12205686 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10422971 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6895231 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1319326 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 854507 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58152614 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2049745 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56795087 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 97937 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6861282 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503589 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1388801 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81194854 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.699491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361721 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80169891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114936 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.592787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 28969141 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36597720 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12749238 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 505228 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1348563 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 587502 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42619 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70583559 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129875 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1348563 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 29902418 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12633582 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20046715 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11807818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4430793 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66640171 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8986 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 787429 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 47943 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1601274 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 44565634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80920867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80741427 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166989 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38166970 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6398656 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1681821 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 238696 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9832739 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10696003 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7004082 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1336985 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 877203 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58981840 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2047452 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57223975 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117650 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7712570 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4365148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1386476 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80169891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.713784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.404933 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56519522 69.61% 69.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10856431 13.37% 82.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5145956 6.34% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3402319 4.19% 93.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2626681 3.24% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1459376 1.80% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753323 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 333723 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 97523 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56166624 70.06% 70.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10391261 12.96% 83.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4679899 5.84% 88.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3142763 3.92% 92.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2796032 3.49% 96.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1647190 2.05% 98.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 895238 1.12% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 353951 0.44% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96933 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81194854 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80169891 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 92642 11.69% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372744 47.05% 58.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326922 41.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 98738 11.92% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 400158 48.30% 60.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 329520 39.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38726894 68.19% 68.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61723 0.11% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10344006 18.21% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6676923 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38901419 67.98% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61759 0.11% 68.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10584317 18.50% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6690891 11.69% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949060 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56795087 # Type of FU issued -system.cpu.iq.rate 0.465650 # Inst issue rate -system.cpu.iq.fu_busy_cnt 792308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013950 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194982001 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66741051 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55566428 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693271 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336387 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57217918 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362191 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598643 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57223975 # Type of FU issued +system.cpu.iq.rate 0.470676 # Inst issue rate +system.cpu.iq.fu_busy_cnt 828416 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194870458 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68419457 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55733530 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693448 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 335810 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328249 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57682446 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362659 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 614531 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1330641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3245 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 517313 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1606237 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3745 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13777 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 627539 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17932 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 166827 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18239 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 375591 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1239490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10213175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 697716 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63724678 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 681593 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10422971 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6895231 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805950 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512370 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16905 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202448 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409860 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612308 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56329043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9982328 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466043 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1348563 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9312966 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 978337 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64604997 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 590069 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10696003 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7004082 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1802911 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 468863 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 377382 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13777 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 204854 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411482 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 616336 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56685901 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10182131 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 538073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3522319 # number of nop insts executed -system.cpu.iew.exec_refs 16606918 # number of memory reference insts executed -system.cpu.iew.exec_branches 8922931 # Number of branches executed -system.cpu.iew.exec_stores 6624590 # Number of stores executed -system.cpu.iew.exec_rate 0.461829 # Inst execution rate -system.cpu.iew.wb_sent 56008659 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55894317 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27713107 # num instructions producing a value -system.cpu.iew.wb_consumers 37520284 # num instructions consuming a value +system.cpu.iew.exec_nop 3575705 # number of nop insts executed +system.cpu.iew.exec_refs 16819167 # number of memory reference insts executed +system.cpu.iew.exec_branches 8947461 # Number of branches executed +system.cpu.iew.exec_stores 6637036 # Number of stores executed +system.cpu.iew.exec_rate 0.466251 # Inst execution rate +system.cpu.iew.wb_sent 56177988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56061779 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28606216 # num instructions producing a value +system.cpu.iew.wb_consumers 39617780 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458265 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738617 # average fanout of values written-back +system.cpu.iew.wb_rate 0.461117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.722055 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7436889 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660944 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566942 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79955364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702522 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.631936 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8325898 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566478 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 78821328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.712415 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.665597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59166975 74.00% 74.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8627079 10.79% 84.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4603678 5.76% 90.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2536989 3.17% 93.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1507337 1.89% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611638 0.76% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 523619 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 528614 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1849435 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58682621 74.45% 74.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8193641 10.40% 84.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4257107 5.40% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2319840 2.94% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1767395 2.24% 95.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615421 0.78% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 496583 0.63% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 549859 0.70% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1938861 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79955364 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170432 # Number of instructions committed -system.cpu.commit.committedOps 56170432 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 78821328 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56153459 # Number of instructions committed +system.cpu.commit.committedOps 56153459 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470248 # Number of memory references committed -system.cpu.commit.loads 9092330 # Number of loads committed -system.cpu.commit.membars 226348 # Number of memory barriers committed -system.cpu.commit.branches 8439871 # Number of branches committed +system.cpu.commit.refs 15466309 # Number of memory references committed +system.cpu.commit.loads 9089766 # Number of loads committed +system.cpu.commit.membars 226357 # Number of memory barriers committed +system.cpu.commit.branches 8438044 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52020070 # Number of committed integer instructions. -system.cpu.commit.function_calls 740568 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198067 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36230888 64.50% 70.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.30% # Class of committed instruction +system.cpu.commit.int_insts 52003822 # Number of committed integer instructions. +system.cpu.commit.function_calls 740374 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197313 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36218566 64.50% 70.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60658 0.11% 70.30% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9318678 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383871 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949012 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9316123 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6382496 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949060 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56170432 # Class of committed instruction -system.cpu.commit.bw_lim_events 1849435 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56153459 # Class of committed instruction +system.cpu.commit.bw_lim_events 1938861 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141463709 # The number of ROB reads -system.cpu.rob.rob_writes 128455843 # The number of ROB writes -system.cpu.timesIdled 1197783 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40774499 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598399845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979638 # Number of Instructions Simulated -system.cpu.committedOps 52979638 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.302193 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302193 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73867254 # number of integer regfile reads -system.cpu.int_regfile_writes 40307997 # number of integer regfile writes -system.cpu.fp_regfile_reads 166020 # number of floating regfile reads -system.cpu.fp_regfile_writes 167441 # number of floating regfile writes -system.cpu.misc_regfile_reads 2027897 # number of misc regfile reads -system.cpu.misc_regfile_writes 938938 # number of misc regfile writes +system.cpu.rob.rob_reads 141112277 # The number of ROB reads +system.cpu.rob.rob_writes 130308588 # The number of ROB writes +system.cpu.timesIdled 1194216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41408265 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598759795 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52963419 # Number of Instructions Simulated +system.cpu.committedOps 52963419 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.295512 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.295512 # CPI: Total CPI of All Threads +system.cpu.ipc 0.435633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.435633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74250743 # number of integer regfile reads +system.cpu.int_regfile_writes 40442410 # number of integer regfile writes +system.cpu.fp_regfile_reads 166399 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 2028427 # number of misc regfile reads +system.cpu.misc_regfile_writes 938976 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -806,7 +808,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454556 # Throughput (bytes/s) +system.iobus.throughput 1454569 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51149 # Transaction distribution @@ -866,241 +868,245 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380172568 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380163354 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43172756 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43205758 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111944057 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2118154 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2118059 # Transaction distribution +system.cpu.toL2Bus.throughput 111909594 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2117185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2117083 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840753 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342489 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020220 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677927 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5698147 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64643392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586284 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208229676 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208219628 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17344 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480508998 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2018148 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5696298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64577024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208163692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208153644 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17472 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2479804999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1518532368 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1516964420 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189805164 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2185370157 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009436 # number of replacements -system.cpu.icache.tags.tagsinuse 509.668112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7476172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1009944 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.402561 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26651967250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.668112 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995446 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995446 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1008400 # number of replacements +system.cpu.icache.tags.tagsinuse 509.648597 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7589401 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1008908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.522392 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26586363250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.648597 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995407 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9552342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9552342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7476173 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7476173 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7476173 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7476173 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7476173 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14786308436 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8542175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8542175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8542175 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8542175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8542175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8542175 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124793 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124793 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124793 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124793 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7589402 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7589402 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7589402 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7589402 # number of overall hits +system.cpu.icache.overall_hits::total 7589402 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064815 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064815 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064815 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064815 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064815 # number of overall misses +system.cpu.icache.overall_misses::total 1064815 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14788071318 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14788071318 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14788071318 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14788071318 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14788071318 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14788071318 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8654217 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8654217 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8654217 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8654217 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8654217 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8654217 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123040 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123040 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123040 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123040 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123040 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123040 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13887.925431 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13887.925431 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13887.925431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13887.925431 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4640 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 182 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.065574 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.494505 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55835 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55835 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55835 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55835 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55835 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55835 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010167 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1010167 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1010167 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1010167 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1010167 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1010167 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12133097628 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12133097628 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12133097628 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12133097628 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12133097628 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12133097628 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118256 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118256 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118256 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12010.981974 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12010.981974 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55683 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 55683 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 55683 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 55683 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 55683 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 55683 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009132 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1009132 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1009132 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1009132 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1009132 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1009132 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12130132326 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12130132326 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12130132326 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12130132326 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12130132326 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12130132326 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116606 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116606 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116606 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12020.362377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12020.362377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338321 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65341.789916 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2546336 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403490 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.310778 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5544203750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53907.448463 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5292.784095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6141.557358 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.822562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080761 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.093713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3494 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3325 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55443 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26727783 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26727783 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 995001 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827094 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1822095 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840946 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840946 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 27 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 27 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1100884 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2110937 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 840946 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 840946 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.tags.replacements 338319 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65340.875442 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2545143 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.307884 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5540956750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53842.334774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5321.183862 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6177.356806 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.821569 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081195 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.094259 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997023 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3496 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3313 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333995500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882363500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882363500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216359000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216359000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136913 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167693 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167693 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64075.443074 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52944.197665 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53525.301064 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71168.420741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71168.420741 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64075.443074 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58348.822962 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58562.427136 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64075.443074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58348.822962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58562.427136 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1182,168 +1196,168 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401941 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.431628 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25377000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994598 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 417 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # 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number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4197394 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4197394 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 185535 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 185535 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215521 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215521 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11419345 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11419345 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11419345 # number of overall hits +system.cpu.dcache.overall_hits::total 11419345 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1789877 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1789877 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1948925 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1948925 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23421 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23421 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3752813 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3752813 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3752813 # number of overall misses -system.cpu.dcache.overall_misses::total 3752813 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40323855155 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40323855155 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76523868035 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77928512640 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358310999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 358310999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 38001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118091882773 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118091882773 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118091882773 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118091882773 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9011828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9011828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146319 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146319 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208956 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208956 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215523 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215523 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15158147 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15158147 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15158147 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15158147 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198614 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198614 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.317088 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.317088 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.112086 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.112086 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247643 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247643 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247643 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31136.036672 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31136.036672 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3013190 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 80012 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.659226 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 118.428571 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.246653 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246653 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246653 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246653 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22439.178856 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22439.178856 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39985.383039 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39985.383039 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15298.706247 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15298.706247 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31585.487216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31585.487216 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3437281 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 992 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 114395 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.047476 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 124 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840946 # number of writebacks -system.cpu.dcache.writebacks::total 840946 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 724204 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 724204 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5146 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5146 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2368528 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2368528 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2368528 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2368528 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083943 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083943 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300342 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300342 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17597 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17597 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840753 # number of writebacks +system.cpu.dcache.writebacks::total 840753 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705849 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 705849 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1648446 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1648446 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5839 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5839 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2354295 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2354295 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2354295 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2354295 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084028 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084028 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300479 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300479 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17582 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17582 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384285 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384285 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384285 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384285 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275514507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275514507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11674414609 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11674414609 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201282500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201282500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38949929116 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38949929116 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38949929116 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38949929116 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424067500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424067500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997567998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997567998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421635498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421635498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120352 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120352 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084296 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084296 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384507 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384507 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275332511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275332511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11834545572 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11834545572 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200445001 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200445001 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39109878083 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39109878083 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39109878083 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39109878083 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424085500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424085500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997539998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997539998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048888 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048888 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084142 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084142 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091347 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091347 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25161.095941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25161.095941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39385.599566 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39385.599566 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11400.580196 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11400.580196 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16999.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1352,28 +1366,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211015 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74666 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105570 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182246 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73299 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817873983000 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64184500 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 553817500 0.03% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41694992500 2.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860186977500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73299 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817910535000 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64222000 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554846000 0.03% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41641763000 2.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860171366000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815425 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1412,7 +1426,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175119 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.23% 93.44% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1421,20 +1435,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191963 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.callpal::total 191975 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29561208000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2704677000 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827921084500 98.27% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29515260500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2703792500 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827952305000 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |