diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 62 |
1 files changed, 57 insertions, 5 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 9b89e5da4..cd56250dd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.876794 # Nu sim_ticks 1876794488000 # Number of ticks simulated final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156335 # Simulator instruction rate (inst/s) -host_op_rate 156335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5537786455 # Simulator tick rate (ticks/s) -host_mem_usage 329540 # Number of bytes of host memory used -host_seconds 338.91 # Real time elapsed on the host +host_inst_rate 191271 # Simulator instruction rate (inst/s) +host_op_rate 191271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6775305946 # Simulator tick rate (ticks/s) +host_mem_usage 377772 # Number of bytes of host memory used +host_seconds 277.01 # Real time elapsed on the host sim_insts 52982943 # Number of instructions simulated sim_ops 52982943 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory @@ -298,6 +299,8 @@ system.physmem_1.memoryStateTime::REF 62670140000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 19569408 # Number of BP lookups system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect @@ -344,6 +347,16 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.numPwrStateTransitions 12876 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 155167561 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -640,6 +653,7 @@ system.cpu.fp_regfile_reads 166613 # nu system.cpu.fp_regfile_writes 175794 # number of floating regfile writes system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads system.cpu.misc_regfile_writes 939529 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1405900 # number of replacements system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. @@ -656,6 +670,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits @@ -808,6 +823,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1074186 # number of replacements system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. @@ -824,6 +840,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 366 system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits @@ -898,6 +915,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 338591 # number of replacements system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. @@ -920,6 +938,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits @@ -1116,6 +1135,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution @@ -1170,6 +1190,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51151 # Transaction distribution @@ -1224,6 +1245,7 @@ system.iobus.respLayer0.occupancy 23459000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1238,6 +1260,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1318,6 +1341,7 @@ system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 296606 # Transaction distribution system.membus.trans_dist::WriteReq 9599 # Transaction distribution @@ -1367,6 +1391,11 @@ system.membus.respLayer1.occupancy 2138626000 # La system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1398,6 +1427,29 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed |