diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 2159 |
1 files changed, 1084 insertions, 1075 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 038a204b1..156f5647f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.861006 # Number of seconds simulated -sim_ticks 1861005569500 # Number of ticks simulated -final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.861005 # Number of seconds simulated +sim_ticks 1861005347500 # Number of ticks simulated +final_tick 1861005347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152837 # Simulator instruction rate (inst/s) -host_op_rate 152837 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5373256396 # Simulator tick rate (ticks/s) -host_mem_usage 376300 # Number of bytes of host memory used -host_seconds 346.35 # Real time elapsed on the host -sim_insts 52934565 # Number of instructions simulated -sim_ops 52934565 # Number of ops (including micro ops) simulated +host_inst_rate 149955 # Simulator instruction rate (inst/s) +host_op_rate 149955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5267476367 # Simulator tick rate (ticks/s) +host_mem_usage 376564 # Number of bytes of host memory used +host_seconds 353.30 # Real time elapsed on the host +sim_insts 52979113 # Number of instructions simulated +sim_ops 52979113 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 965824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory -system.physmem.bytes_written::total 7517248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388701 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25846272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 965824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7524416 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15091 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403841 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117457 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13367431 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403848 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117569 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117569 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13368843 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13888096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4039347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4039347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4039347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13367431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13888338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13368843 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17927443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403841 # Number of read requests accepted -system.physmem.writeReqs 159009 # Number of write requests accepted -system.physmem.readBursts 403841 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bw_total::total 17931538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403848 # Number of read requests accepted +system.physmem.writeReqs 117569 # Number of write requests accepted +system.physmem.readBursts 403848 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117569 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue -system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25748 # Per bank write bursts -system.physmem.perBankRdBursts::1 25559 # Per bank write bursts -system.physmem.perBankRdBursts::2 25508 # Per bank write bursts -system.physmem.perBankRdBursts::3 25346 # Per bank write bursts -system.physmem.perBankRdBursts::4 25393 # Per bank write bursts -system.physmem.perBankRdBursts::5 24806 # Per bank write bursts -system.physmem.perBankRdBursts::6 25027 # Per bank write bursts -system.physmem.perBankRdBursts::7 25127 # Per bank write bursts -system.physmem.perBankRdBursts::8 24925 # Per bank write bursts -system.physmem.perBankRdBursts::9 25034 # Per bank write bursts -system.physmem.perBankRdBursts::10 25436 # Per bank write bursts -system.physmem.perBankRdBursts::11 24774 # Per bank write bursts -system.physmem.perBankRdBursts::12 24551 # Per bank write bursts -system.physmem.perBankRdBursts::13 25233 # Per bank write bursts -system.physmem.perBankRdBursts::14 25663 # Per bank write bursts -system.physmem.perBankRdBursts::15 25612 # Per bank write bursts -system.physmem.perBankWrBursts::0 9148 # Per bank write bursts -system.physmem.perBankWrBursts::1 8514 # Per bank write bursts -system.physmem.perBankWrBursts::2 8998 # Per bank write bursts -system.physmem.perBankWrBursts::3 8298 # Per bank write bursts -system.physmem.perBankWrBursts::4 8214 # Per bank write bursts -system.physmem.perBankWrBursts::5 7705 # Per bank write bursts -system.physmem.perBankWrBursts::6 7696 # Per bank write bursts -system.physmem.perBankWrBursts::7 7707 # Per bank write bursts -system.physmem.perBankWrBursts::8 8055 # Per bank write bursts -system.physmem.perBankWrBursts::9 7602 # Per bank write bursts -system.physmem.perBankWrBursts::10 8149 # Per bank write bursts -system.physmem.perBankWrBursts::11 7799 # Per bank write bursts -system.physmem.perBankWrBursts::12 8377 # Per bank write bursts -system.physmem.perBankWrBursts::13 9062 # Per bank write bursts -system.physmem.perBankWrBursts::14 8903 # Per bank write bursts -system.physmem.perBankWrBursts::15 8889 # Per bank write bursts +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25846272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7524416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 41759 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25651 # Per bank write bursts +system.physmem.perBankRdBursts::1 25422 # Per bank write bursts +system.physmem.perBankRdBursts::2 25567 # Per bank write bursts +system.physmem.perBankRdBursts::3 25497 # Per bank write bursts +system.physmem.perBankRdBursts::4 25384 # Per bank write bursts +system.physmem.perBankRdBursts::5 24734 # Per bank write bursts +system.physmem.perBankRdBursts::6 24943 # Per bank write bursts +system.physmem.perBankRdBursts::7 25079 # Per bank write bursts +system.physmem.perBankRdBursts::8 24928 # Per bank write bursts +system.physmem.perBankRdBursts::9 25027 # Per bank write bursts +system.physmem.perBankRdBursts::10 25572 # Per bank write bursts +system.physmem.perBankRdBursts::11 24872 # Per bank write bursts +system.physmem.perBankRdBursts::12 24489 # Per bank write bursts +system.physmem.perBankRdBursts::13 25240 # Per bank write bursts +system.physmem.perBankRdBursts::14 25741 # Per bank write bursts +system.physmem.perBankRdBursts::15 25596 # Per bank write bursts +system.physmem.perBankWrBursts::0 7944 # Per bank write bursts +system.physmem.perBankWrBursts::1 7514 # Per bank write bursts +system.physmem.perBankWrBursts::2 7965 # Per bank write bursts +system.physmem.perBankWrBursts::3 7518 # Per bank write bursts +system.physmem.perBankWrBursts::4 7330 # Per bank write bursts +system.physmem.perBankWrBursts::5 6666 # Per bank write bursts +system.physmem.perBankWrBursts::6 6776 # Per bank write bursts +system.physmem.perBankWrBursts::7 6716 # Per bank write bursts +system.physmem.perBankWrBursts::8 7141 # Per bank write bursts +system.physmem.perBankWrBursts::9 6711 # Per bank write bursts +system.physmem.perBankWrBursts::10 7422 # Per bank write bursts +system.physmem.perBankWrBursts::11 6968 # Per bank write bursts +system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::13 7857 # Per bank write bursts +system.physmem.perBankWrBursts::14 8054 # Per bank write bursts +system.physmem.perBankWrBursts::15 7825 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 85 # Number of times write queue was full causing retry -system.physmem.totGap 1861000236500 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 1860999975500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403841 # Read request sizes (log2) +system.physmem.readPktSize::6 403848 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159009 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117569 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -148,199 +148,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 323 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 548.114030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 339.010384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.134053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13424 21.42% 21.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10425 16.63% 38.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5386 8.59% 46.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2710 4.32% 50.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2462 3.93% 54.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1644 2.62% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1512 2.41% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1300 2.07% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23822 38.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62685 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4847 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 83.295234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3032.862596 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4844 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61779 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 540.028683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.823835 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.833229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13638 22.08% 22.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10412 16.85% 38.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4989 8.08% 47.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3229 5.23% 52.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2263 3.66% 55.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1516 2.45% 58.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1526 2.47% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1289 2.09% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22917 37.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61779 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.447919 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2924.392219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5210 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4847 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4847 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.463586 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.516932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.014286 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4601 94.92% 94.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 56 1.16% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 4 0.08% 96.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 1 0.02% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 13 0.27% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 3 0.06% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 3 0.06% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 6 0.12% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 21 0.43% 97.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 18 0.37% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 8 0.17% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 12 0.25% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 2 0.04% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.08% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.04% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 17 0.35% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 13 0.27% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 3 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 11 0.23% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.08% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 2 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 4 0.08% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 4 0.08% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 8 0.17% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads -system.physmem.totQLat 3741904500 # Total ticks spent queuing -system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 5213 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.549779 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.928650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.456391 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4618 88.59% 88.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 208 3.99% 92.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 74 1.42% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 17 0.33% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 8 0.15% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 5 0.10% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 10 0.19% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 7 0.13% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 32 0.61% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 168 3.22% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 10 0.19% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.10% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.08% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 12 0.23% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5213 # Writes before turning the bus around for reads +system.physmem.totQLat 3805918000 # Total ticks spent queuing +system.physmem.totMemAccLat 11376080500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9426.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28176.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing -system.physmem.readRowHits 364326 # Number of row buffer hits during reads -system.physmem.writeRowHits 109846 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.50 # Row buffer hit rate for writes -system.physmem.avgGap 3306387.56 # Average gap between requests -system.physmem.pageHitRate 88.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235516680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128506125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579609200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 429494400 # Energy for write commands per rank (pJ) +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.30 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 364169 # Number of row buffer hits during reads +system.physmem.writeRowHits 95345 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes +system.physmem.avgGap 3569120.25 # Average gap between requests +system.physmem.pageHitRate 88.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232515360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126868500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577760600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378619920 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56182721175 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1067316698250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1247423979990 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.297807 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1775410357162 # Time in different power states +system.physmem_0.actBackEnergy 56250477360 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067257263000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1247374938900 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.271455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1775312455750 # Time in different power states system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23446441588 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23544343000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 238381920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 130069500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1569531600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433097280 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 234533880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 127969875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571380200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383117040 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 56034129015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1067447050500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1247403693975 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.286901 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1775626000168 # Time in different power states +system.physmem_1.actBackEnergy 55982569095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067492278500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1247343282750 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.254439 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1775708219250 # Time in different power states system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23231077332 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23148593250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17721924 # Number of BP lookups -system.cpu.branchPred.condPredicted 15403228 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 380344 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11703979 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5913014 # Number of BTB hits +system.cpu.branchPred.lookups 17721018 # Number of BP lookups +system.cpu.branchPred.condPredicted 15408782 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 378784 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12470436 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5897235 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.521400 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 923784 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21447 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 47.289726 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 918220 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21032 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10269214 # DTB read hits -system.cpu.dtb.read_misses 41261 # DTB read misses -system.cpu.dtb.read_acv 507 # DTB read access violations -system.cpu.dtb.read_accesses 967301 # DTB read accesses -system.cpu.dtb.write_hits 6648637 # DTB write hits -system.cpu.dtb.write_misses 9303 # DTB write misses -system.cpu.dtb.write_acv 402 # DTB write access violations -system.cpu.dtb.write_accesses 342644 # DTB write accesses -system.cpu.dtb.data_hits 16917851 # DTB hits -system.cpu.dtb.data_misses 50564 # DTB misses -system.cpu.dtb.data_acv 909 # DTB access violations -system.cpu.dtb.data_accesses 1309945 # DTB accesses -system.cpu.itb.fetch_hits 1769158 # ITB hits -system.cpu.itb.fetch_misses 36068 # ITB misses -system.cpu.itb.fetch_acv 660 # ITB acv -system.cpu.itb.fetch_accesses 1805226 # ITB accesses +system.cpu.dtb.read_hits 10294388 # DTB read hits +system.cpu.dtb.read_misses 42024 # DTB read misses +system.cpu.dtb.read_acv 506 # DTB read access violations +system.cpu.dtb.read_accesses 968687 # DTB read accesses +system.cpu.dtb.write_hits 6648521 # DTB write hits +system.cpu.dtb.write_misses 9456 # DTB write misses +system.cpu.dtb.write_acv 408 # DTB write access violations +system.cpu.dtb.write_accesses 343243 # DTB write accesses +system.cpu.dtb.data_hits 16942909 # DTB hits +system.cpu.dtb.data_misses 51480 # DTB misses +system.cpu.dtb.data_acv 914 # DTB access violations +system.cpu.dtb.data_accesses 1311930 # DTB accesses +system.cpu.itb.fetch_hits 1769476 # ITB hits +system.cpu.itb.fetch_misses 36155 # ITB misses +system.cpu.itb.fetch_acv 662 # ITB acv +system.cpu.itb.fetch_accesses 1805631 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -353,258 +344,258 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122572361 # number of cpu cycles simulated +system.cpu.numCycles 122272854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29541441 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78093998 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17721924 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6836798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 84630340 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1254210 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1349 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1745325 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 441267 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9051182 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273719 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117014009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.667390 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.979034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29542399 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 77951342 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17721018 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6815455 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 84318662 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1251172 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1032 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27002 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1751503 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 450615 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9037094 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 274713 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116717019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.667866 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.979948 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102427448 87.53% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 934169 0.80% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1984138 1.70% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 910061 0.78% 90.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2793690 2.39% 93.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 647956 0.55% 93.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 739168 0.63% 94.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007210 0.86% 95.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5570169 4.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102159840 87.53% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 935001 0.80% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1975635 1.69% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 907890 0.78% 90.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2798283 2.40% 93.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 634657 0.54% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 731012 0.63% 94.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1008696 0.86% 95.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5566005 4.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117014009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144583 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.637126 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24038562 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80987042 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9497307 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7824422 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 116717019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144930 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.637520 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24051579 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80690981 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9487535 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1903773 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 583150 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586842 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42848 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68182155 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 134674 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 583150 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24974215 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50913599 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20868972 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10381558 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8995523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65764072 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 201455 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2078667 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 157006 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4811107 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43858088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79749030 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79568293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168286 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179356 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5678724 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1691117 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241700 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13523739 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10414999 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6951257 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1489090 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1076371 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58557437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2137330 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57550552 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 58383 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7715649 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3482179 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476201 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116717019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.493078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.231262 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1001151 0.86% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93076852 79.75% 79.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10193735 8.73% 88.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4312708 3.70% 92.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3021195 2.59% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3081764 2.64% 97.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1495449 1.28% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1007889 0.86% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 403235 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124192 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116717019 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 208462 18.43% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547266 48.38% 66.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375475 33.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39056911 67.87% 67.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61891 0.11% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38552 0.07% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10704988 18.60% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6728388 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948900 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued -system.cpu.iq.rate 0.469435 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57550552 # Type of FU issued +system.cpu.iq.rate 0.470673 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1131203 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019656 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 232294841 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68093775 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55871823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712867 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336544 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329026 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58291729 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382740 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 634925 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1322411 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20331 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 573217 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18302 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 483316 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 583150 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 47678109 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 871068 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64398227 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 142430 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10414999 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6951257 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1888726 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 44438 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 623782 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20331 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 186400 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411798 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 598198 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56961347 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10364061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 589204 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3706829 # number of nop insts executed -system.cpu.iew.exec_refs 17011176 # number of memory reference insts executed -system.cpu.iew.exec_branches 8976912 # Number of branches executed -system.cpu.iew.exec_stores 6673045 # Number of stores executed -system.cpu.iew.exec_rate 0.464599 # Inst execution rate -system.cpu.iew.wb_sent 56353404 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56212492 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28792537 # num instructions producing a value -system.cpu.iew.wb_consumers 40027235 # num instructions consuming a value +system.cpu.iew.exec_nop 3703460 # number of nop insts executed +system.cpu.iew.exec_refs 17037134 # number of memory reference insts executed +system.cpu.iew.exec_branches 8968929 # Number of branches executed +system.cpu.iew.exec_stores 6673073 # Number of stores executed +system.cpu.iew.exec_rate 0.465854 # Inst execution rate +system.cpu.iew.wb_sent 56337909 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56200849 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28756133 # num instructions producing a value +system.cpu.iew.wb_consumers 39912635 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458607 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719324 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459635 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.720477 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8228560 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8112704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661129 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 547326 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 115294268 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487187 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.430320 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4272055 3.70% 93.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1764306 1.53% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 473669 0.41% 97.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2085446 1.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95501177 82.83% 82.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7867272 6.82% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4280982 3.71% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2233083 1.94% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1745854 1.51% 96.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611445 0.53% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 482985 0.42% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 468960 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2102510 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56123349 # Number of instructions committed -system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 115294268 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56169836 # Number of instructions committed +system.cpu.commit.committedOps 56169836 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15459994 # Number of memory references committed -system.cpu.commit.loads 9085408 # Number of loads committed -system.cpu.commit.membars 226308 # Number of memory barriers committed -system.cpu.commit.branches 8435685 # Number of branches committed -system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51974864 # Number of committed integer instructions. -system.cpu.commit.function_calls 740049 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3196057 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36183700 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction +system.cpu.commit.refs 15470628 # Number of memory references committed +system.cpu.commit.loads 9092588 # Number of loads committed +system.cpu.commit.membars 226333 # Number of memory barriers committed +system.cpu.commit.branches 8440353 # Number of branches committed +system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52019375 # Number of committed integer instructions. +system.cpu.commit.function_calls 740552 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197996 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36217639 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60667 0.11% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction @@ -627,411 +618,417 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318921 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383992 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948900 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction -system.cpu.commit.bw_lim_events 2085446 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 177593268 # The number of ROB reads -system.cpu.rob.rob_writes 130137832 # The number of ROB writes -system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52934565 # Number of Instructions Simulated -system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads -system.cpu.ipc 0.431864 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.431864 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74599299 # number of integer regfile reads -system.cpu.int_regfile_writes 40560409 # number of integer regfile writes -system.cpu.fp_regfile_reads 167171 # number of floating regfile reads -system.cpu.fp_regfile_writes 167579 # number of floating regfile writes -system.cpu.misc_regfile_reads 2029670 # number of misc regfile reads -system.cpu.misc_regfile_writes 939349 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1403663 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994456 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11858482 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1404175 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.445160 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994456 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56169836 # Class of committed instruction +system.cpu.commit.bw_lim_events 2102510 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 177224791 # The number of ROB reads +system.cpu.rob.rob_writes 129983616 # The number of ROB writes +system.cpu.timesIdled 573073 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5555835 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599737842 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979113 # Number of Instructions Simulated +system.cpu.committedOps 52979113 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.307945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.307945 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433286 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433286 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74622251 # number of integer regfile reads +system.cpu.int_regfile_writes 40551917 # number of integer regfile writes +system.cpu.fp_regfile_reads 167069 # number of floating regfile reads +system.cpu.fp_regfile_writes 167545 # number of floating regfile writes +system.cpu.misc_regfile_reads 2028916 # number of misc regfile reads +system.cpu.misc_regfile_writes 939321 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1404299 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994455 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11844191 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404811 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.431163 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994455 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63936372 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63936372 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7267066 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7267066 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4189300 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4189300 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186111 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186111 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215710 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215710 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11456366 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11456366 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11456366 # number of overall hits -system.cpu.dcache.overall_hits::total 11456366 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1796718 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1796718 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1954848 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1954848 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23269 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23269 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses -system.cpu.dcache.overall_misses::total 3751566 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890725520 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80890725520 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 122732079835 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 122732079835 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 122732079835 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 122732079835 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15207932 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15207932 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15207932 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15207932 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198230 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198230 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318164 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111133 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111133 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32714.892883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32714.892883 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4477894 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.235072 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 63926076 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63926076 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7252822 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7252822 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4188714 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4188714 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186644 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186644 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215706 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215706 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11441536 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11441536 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11441536 # number of overall hits +system.cpu.dcache.overall_hits::total 11441536 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1804157 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1804157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1958890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1958890 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23354 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23354 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3763047 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3763047 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3763047 # number of overall misses +system.cpu.dcache.overall_misses::total 3763047 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41750233000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41750233000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80527676066 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80527676066 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 377889000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 377889000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 498500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 498500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 122277909066 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 122277909066 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 122277909066 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 122277909066 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9056979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9056979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147604 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147604 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215735 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215735 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15204583 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15204583 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15204583 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15204583 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199201 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199201 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318643 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318643 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111211 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111211 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247494 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247494 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247494 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247494 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23141.130733 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23141.130733 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41108.830034 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41108.830034 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16180.911193 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16180.911193 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17189.655172 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17189.655172 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32494.387943 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32494.387943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32494.387943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32494.387943 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4529793 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2677 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 135335 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.470965 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 107.080000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842087 # number of writebacks -system.cpu.dcache.writebacks::total 842087 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 701160 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 701160 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664055 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664055 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5272 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5272 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2365215 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2365215 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2365215 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2365215 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095558 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1095558 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290793 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290793 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17997 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17997 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 27 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 842762 # number of writebacks +system.cpu.dcache.writebacks::total 842762 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708195 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 708195 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1668077 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1668077 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5151 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5151 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2376272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2376272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2376272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2376272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095962 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1095962 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290813 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290813 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18203 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18203 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386775 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386775 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386775 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386775 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482529124 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482529124 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479462147 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42479462147 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479462147 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42479462147 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011966000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3445672500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3445672500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120872 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047328 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047328 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000125 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000125 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091160 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30575992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30575992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12635842717 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12635842717 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226273500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226273500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 469500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 469500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43211834717 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43211834717 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43211834717 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43211834717 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1451037500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1451037500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035928998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035928998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486966498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486966498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047305 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047305 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086682 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086682 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091208 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091208 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27898.770213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27898.770213 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43450.061438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43450.061438 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12430.560897 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12430.560897 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16189.655172 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16189.655172 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209384.920635 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209384.920635 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.231739 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.231739 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210986.053004 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210986.053004 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1032757 # number of replacements -system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7965141 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1033265 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.708711 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 28360334250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.197301 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994526 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1035158 # number of replacements +system.cpu.icache.tags.tagsinuse 509.238634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7947846 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1035666 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.674140 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28148361500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.238634 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994607 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994607 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10084699 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10084699 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7965142 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7965142 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7965142 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7965142 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7965142 # number of overall hits -system.cpu.icache.overall_hits::total 7965142 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1086038 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1086038 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1086038 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1086038 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1086038 # number of overall misses -system.cpu.icache.overall_misses::total 1086038 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15222356868 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15222356868 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15222356868 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15222356868 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15222356868 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15222356868 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9051180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9051180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9051180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9051180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9051180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9051180 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119989 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119989 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119989 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119989 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119989 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119989 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.412748 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14016.412748 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14016.412748 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14016.412748 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5848 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10073023 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10073023 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7947847 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7947847 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7947847 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7947847 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7947847 # number of overall hits +system.cpu.icache.overall_hits::total 7947847 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1089244 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1089244 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1089244 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1089244 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1089244 # number of overall misses +system.cpu.icache.overall_misses::total 1089244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15223822993 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15223822993 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15223822993 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15223822993 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15223822993 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15223822993 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9037091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9037091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9037091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9037091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9037091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9037091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120530 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120530 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120530 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120530 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120530 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120530 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.503881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13976.503881 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.503881 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13976.503881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.503881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13976.503881 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5247 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 208 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.115385 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.328125 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52519 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52519 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52519 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52519 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52519 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52519 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1033519 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1033519 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1033519 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1033519 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1033519 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1033519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13013904297 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13013904297 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13013904297 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13013904297 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13013904297 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13013904297 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114186 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114186 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114186 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12591.838464 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12591.838464 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53312 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53312 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53312 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53312 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53312 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53312 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035932 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1035932 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1035932 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1035932 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1035932 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1035932 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13551519997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13551519997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13551519997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13551519997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13551519997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13551519997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114631 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114631 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114631 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13081.476387 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13081.476387 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13081.476387 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13081.476387 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13081.476387 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13081.476387 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338332 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65331.413764 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2572439 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403497 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.375361 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5986676750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53648.492013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5347.510273 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6335.411477 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081597 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.096671 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996878 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 338333 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65329.899668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4170748 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403498 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.336478 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5937880000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53646.073919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5370.196877 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6313.628872 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.818574 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081943 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.096338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996855 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 491 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 490 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3506 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2403 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55444 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55438 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26943938 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26943938 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1018225 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 828726 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1846951 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 842087 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 842087 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186337 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186337 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1015063 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2033288 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1015063 # number of overall hits -system.cpu.l2cache.overall_hits::total 2033288 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115276 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115276 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389207 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404334 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389207 # number of overall misses -system.cpu.l2cache.overall_misses::total 404334 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271399612 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10271399612 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30291411612 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31556248611 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30291411612 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31556248611 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 842087 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 842087 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 27 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 27 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301613 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301613 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1033352 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1404270 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2437622 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1033352 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1404270 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2437622 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014639 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248428 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.135326 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382198 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382198 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277160 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165872 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277160 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89102.671953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89102.671953 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78045.003910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78045.003910 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 39732941 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39732941 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 842762 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 842762 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 23 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186220 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186220 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1020652 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1020652 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 829426 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 829426 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1020652 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1015646 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2036298 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1020652 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1015646 # number of overall hits +system.cpu.l2cache.overall_hits::total 2036298 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 53 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 53 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115405 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115405 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15093 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 15093 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273846 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 273846 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15093 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389251 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404344 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15093 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389251 # number of overall misses +system.cpu.l2cache.overall_misses::total 404344 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 425000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 425000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 61000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 61000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10303208000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10303208000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1257093500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1257093500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19996128500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19996128500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1257093500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30299336500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31556430000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1257093500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30299336500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31556430000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 842762 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 842762 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 82 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 29 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301625 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301625 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1035745 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1035745 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1103272 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1103272 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1035745 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1404897 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2440642 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1035745 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1404897 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2440642 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.646341 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.646341 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.206897 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.206897 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014572 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014572 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248213 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248213 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277067 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.165671 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277067 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.165671 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8018.867925 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8018.867925 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 10166.666667 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 10166.666667 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89278.696764 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89278.696764 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83289.836348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83289.836348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73019.611387 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73019.611387 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83289.836348 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77840.099319 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78043.522347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83289.836348 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77840.099319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78043.522347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1040,130 +1037,141 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75945 # number of writebacks -system.cpu.l2cache.writebacks::total 75945 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 76057 # number of writebacks +system.cpu.l2cache.writebacks::total 76057 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15126 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273931 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289057 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115276 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115276 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389207 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404333 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389207 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404333 # number of overall MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 307 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 307 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 53 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 53 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115405 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115405 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15092 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15092 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273846 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273846 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15092 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15092 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389251 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404343 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861643888 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861643888 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469539888 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26545366637 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469539888 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26545366637 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165872 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76873.277074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76873.277074 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192884.054834 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192884.054834 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196642.961342 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196642.961342 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195066.799782 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195066.799782 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1250500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1250500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 124500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 124500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9149158000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9149158000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1106078000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1106078000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17268105500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17268105500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1106078000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26417263500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27523341500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1106078000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26417263500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27523341500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364412500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364412500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925547500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925547500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289960000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289960000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.646341 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.646341 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.206897 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.206897 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248213 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248213 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165671 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165671 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23594.339623 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23594.339623 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20750 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79278.696764 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79278.696764 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73289.027299 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73289.027299 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63057.724049 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63057.724049 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196884.920635 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196884.920635 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200640.564760 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200640.564760 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199065.771162 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199065.771162 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2146205 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 106 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42097 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3338284 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111162 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 960354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1857372 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1103445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106451 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4246137 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7352588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66287680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143898860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210186540 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422109 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5318690 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.079299 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270205 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3296510 98.75% 98.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41774 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4896924 92.07% 92.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 421766 7.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3338284 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 5318690 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3296022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1555343104 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2190379636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2119169250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1180,8 +1188,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51149 # Transaction distribution -system.iobus.trans_dist::WriteResp 9597 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51149 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -1236,21 +1243,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242053963 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216065006 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024003 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.259192 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.259177 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711311066000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.259192 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1711311931000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.259177 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1260,49 +1267,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21719383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21719383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8765491577 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8765491577 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21719383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21719383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21719383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21719383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4909206123 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4909206123 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125545.566474 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125545.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125545.566474 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73146 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118146.084978 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118146.084978 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10015 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.303645 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1310,84 +1317,86 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12567383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12567383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6604781583 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6604781583 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12567383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12567383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12567383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12567383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831606123 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2831606123 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68146.084978 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68146.084978 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296160 # Transaction distribution -system.membus.trans_dist::ReadResp 296066 # Transaction distribution +system.membus.trans_dist::ReadReq 6930 # Transaction distribution +system.membus.trans_dist::ReadResp 295956 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117457 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 187 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 192 # Transaction distribution -system.membus.trans_dist::ReadExReq 115137 # Transaction distribution -system.membus.trans_dist::ReadExResp 115137 # Transaction distribution -system.membus.trans_dist::BadAddressError 94 # Transaction distribution +system.membus.trans_dist::Writeback 117569 # Transaction distribution +system.membus.trans_dist::CleanEvict 261797 # Transaction distribution +system.membus.trans_dist::UpgradeReq 204 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 210 # Transaction distribution +system.membus.trans_dist::ReadExReq 115254 # Transaction distribution +system.membus.trans_dist::ReadExResp 115254 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289111 # Transaction distribution +system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884252 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917494 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042298 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179422 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1304239 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30712960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33414828 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 580180 # Request fanout histogram +system.membus.snoop_fanout::samples 842203 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580180 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580180 # Request fanout histogram -system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842203 # Request fanout histogram +system.membus.reqLayer0.occupancy 29160500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1226050062 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313577675 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 109500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139458813 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139558790 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1421,28 +1430,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210982 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74654 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210978 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74652 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105549 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182213 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73287 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105547 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182209 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73285 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73287 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148584 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817355802000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62075500 0.00% 97.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 532990500 0.03% 97.69% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 43053863500 2.31% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1861004731500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73285 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148580 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817522630000 97.66% 97.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62579500 0.00% 97.67% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 533633500 0.03% 97.70% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42885651500 2.30% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1861004494500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815441 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815437 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1478,11 +1487,11 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175098 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175094 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed @@ -1490,20 +1499,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191942 # number of callpals executed +system.cpu.kern.callpal::total 191938 # number of callpals executed system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326667 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325983 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394509 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29153631500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2692582500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1829158509500 98.29% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393886 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29174464500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2684090500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829145931500 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |