diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt | 3146 |
1 files changed, 1584 insertions, 1562 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 555ee4194..f41b81651 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.843617 # Number of seconds simulated -sim_ticks 1843616607000 # Number of ticks simulated -final_tick 1843616607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841599 # Number of seconds simulated +sim_ticks 1841599161000 # Number of ticks simulated +final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248643 # Simulator instruction rate (inst/s) -host_op_rate 248643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6281412703 # Simulator tick rate (ticks/s) -host_mem_usage 335188 # Number of bytes of host memory used -host_seconds 293.50 # Real time elapsed on the host -sim_insts 72977545 # Number of instructions simulated -sim_ops 72977545 # Number of ops (including micro ops) simulated +host_inst_rate 245408 # Simulator instruction rate (inst/s) +host_op_rate 245408 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6773643024 # Simulator tick rate (ticks/s) +host_mem_usage 331844 # Number of bytes of host memory used +host_seconds 271.88 # Real time elapsed on the host +sim_insts 66720805 # Number of instructions simulated +sim_ops 66720805 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 493824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20821760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1538304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 275200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2511424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 472448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20115392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2145088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 298752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2611904 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25788032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 493824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 275200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 915584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7477248 # Number of bytes written to this memory -system.physmem.bytes_written::total 7477248 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7716 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 325340 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39241 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25791552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 472448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 298752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7488832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7488832 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7382 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33517 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 40811 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402938 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116832 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116832 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 267856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 11293975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 834395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 149272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1362227 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402993 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117013 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 256542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10922785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1164796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 162224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1418280 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13987741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 267856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79496 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 149272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 496624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4055750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4055750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4055750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 267856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 11293975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 834395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 149272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1362227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14004976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 256542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 162224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4066483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4066483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4066483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 256542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10922785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1164796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 162224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1418280 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18043491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 69882 # Number of read requests accepted -system.physmem.writeReqs 42058 # Number of write requests accepted -system.physmem.readBursts 69882 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 42058 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 4471360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue -system.physmem.bytesWritten 2689856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 4472448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2691712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 18071459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81308 # Number of read requests accepted +system.physmem.writeReqs 46917 # Number of write requests accepted +system.physmem.readBursts 81308 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 46917 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5202560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue +system.physmem.bytesWritten 3000896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5203712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3002688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4380 # Per bank write bursts -system.physmem.perBankRdBursts::1 4144 # Per bank write bursts -system.physmem.perBankRdBursts::2 4349 # Per bank write bursts -system.physmem.perBankRdBursts::3 4638 # Per bank write bursts -system.physmem.perBankRdBursts::4 3888 # Per bank write bursts -system.physmem.perBankRdBursts::5 4647 # Per bank write bursts -system.physmem.perBankRdBursts::6 4275 # Per bank write bursts -system.physmem.perBankRdBursts::7 4272 # Per bank write bursts -system.physmem.perBankRdBursts::8 4610 # Per bank write bursts -system.physmem.perBankRdBursts::9 4314 # Per bank write bursts -system.physmem.perBankRdBursts::10 4557 # Per bank write bursts -system.physmem.perBankRdBursts::11 4086 # Per bank write bursts -system.physmem.perBankRdBursts::12 4064 # Per bank write bursts -system.physmem.perBankRdBursts::13 4584 # Per bank write bursts -system.physmem.perBankRdBursts::14 4708 # Per bank write bursts -system.physmem.perBankRdBursts::15 4349 # Per bank write bursts -system.physmem.perBankWrBursts::0 2696 # Per bank write bursts -system.physmem.perBankWrBursts::1 2323 # Per bank write bursts -system.physmem.perBankWrBursts::2 2672 # Per bank write bursts -system.physmem.perBankWrBursts::3 3008 # Per bank write bursts -system.physmem.perBankWrBursts::4 2271 # Per bank write bursts -system.physmem.perBankWrBursts::5 2656 # Per bank write bursts -system.physmem.perBankWrBursts::6 2498 # Per bank write bursts -system.physmem.perBankWrBursts::7 2402 # Per bank write bursts -system.physmem.perBankWrBursts::8 3013 # Per bank write bursts -system.physmem.perBankWrBursts::9 2448 # Per bank write bursts -system.physmem.perBankWrBursts::10 2834 # Per bank write bursts -system.physmem.perBankWrBursts::11 2439 # Per bank write bursts -system.physmem.perBankWrBursts::12 2426 # Per bank write bursts -system.physmem.perBankWrBursts::13 2711 # Per bank write bursts -system.physmem.perBankWrBursts::14 2911 # Per bank write bursts -system.physmem.perBankWrBursts::15 2721 # Per bank write bursts +system.physmem.perBankRdBursts::0 4879 # Per bank write bursts +system.physmem.perBankRdBursts::1 4860 # Per bank write bursts +system.physmem.perBankRdBursts::2 4840 # Per bank write bursts +system.physmem.perBankRdBursts::3 5116 # Per bank write bursts +system.physmem.perBankRdBursts::4 5145 # Per bank write bursts +system.physmem.perBankRdBursts::5 5201 # Per bank write bursts +system.physmem.perBankRdBursts::6 5134 # Per bank write bursts +system.physmem.perBankRdBursts::7 5033 # Per bank write bursts +system.physmem.perBankRdBursts::8 5242 # Per bank write bursts +system.physmem.perBankRdBursts::9 4887 # Per bank write bursts +system.physmem.perBankRdBursts::10 5474 # Per bank write bursts +system.physmem.perBankRdBursts::11 5136 # Per bank write bursts +system.physmem.perBankRdBursts::12 4904 # Per bank write bursts +system.physmem.perBankRdBursts::13 4973 # Per bank write bursts +system.physmem.perBankRdBursts::14 5564 # Per bank write bursts +system.physmem.perBankRdBursts::15 4902 # Per bank write bursts +system.physmem.perBankWrBursts::0 2770 # Per bank write bursts +system.physmem.perBankWrBursts::1 2825 # Per bank write bursts +system.physmem.perBankWrBursts::2 2866 # Per bank write bursts +system.physmem.perBankWrBursts::3 3058 # Per bank write bursts +system.physmem.perBankWrBursts::4 2994 # Per bank write bursts +system.physmem.perBankWrBursts::5 2828 # Per bank write bursts +system.physmem.perBankWrBursts::6 3105 # Per bank write bursts +system.physmem.perBankWrBursts::7 2723 # Per bank write bursts +system.physmem.perBankWrBursts::8 3290 # Per bank write bursts +system.physmem.perBankWrBursts::9 2741 # Per bank write bursts +system.physmem.perBankWrBursts::10 3262 # Per bank write bursts +system.physmem.perBankWrBursts::11 2912 # Per bank write bursts +system.physmem.perBankWrBursts::12 2689 # Per bank write bursts +system.physmem.perBankWrBursts::13 2734 # Per bank write bursts +system.physmem.perBankWrBursts::14 3349 # Per bank write bursts +system.physmem.perBankWrBursts::15 2743 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 1842604622000 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 1840587284000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 69882 # Read request sizes (log2) +system.physmem.readPktSize::6 81308 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 42058 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 46917 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,188 +153,204 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20044 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 357.274795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.112689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 369.610579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7222 36.03% 36.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4570 22.80% 58.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1644 8.20% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 908 4.53% 71.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 718 3.58% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 515 2.57% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 476 2.37% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 378 1.89% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3613 18.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20044 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1835 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.063215 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 849.708875 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 1833 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 379.368110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.960357 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 378.240859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7179 33.20% 33.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4878 22.56% 55.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1948 9.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1045 4.83% 69.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 873 4.04% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 450 2.08% 75.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 417 1.93% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 373 1.72% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4461 20.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21624 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 39.666179 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 981.071588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2047 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1835 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1835 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.904087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.705845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.745243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 40 2.18% 2.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 6 0.33% 2.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 1558 84.90% 87.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 20 1.09% 88.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 5 0.27% 88.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 16 0.87% 89.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 75 4.09% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.33% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 1 0.05% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 15 0.82% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 72 3.92% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.16% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 2 0.11% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 1 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.27% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.11% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.11% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.11% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1835 # Writes before turning the bus around for reads -system.physmem.totQLat 876234250 # Total ticks spent queuing -system.physmem.totMemAccLat 2186203000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 349325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12541.82 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.883846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.590123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.999579 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 33 1.61% 1.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 8 0.39% 2.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 2.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 3 0.15% 2.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1695 82.72% 84.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 48 2.34% 87.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10 0.49% 87.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 15 0.73% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 91 4.44% 92.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 8 0.39% 93.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.05% 93.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.20% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.10% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.15% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.10% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.10% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 2 0.10% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.05% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.10% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.63% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.20% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 77 3.76% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.05% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.10% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.10% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.05% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 2 0.10% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.05% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.20% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2049 # Writes before turning the bus around for reads +system.physmem.totQLat 885699750 # Total ticks spent queuing +system.physmem.totMemAccLat 2409887250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 406450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10895.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31291.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29645.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing -system.physmem.readRowHits 58965 # Number of row buffer hits during reads -system.physmem.writeRowHits 32885 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.19 # Row buffer hit rate for writes -system.physmem.avgGap 16460645.18 # Average gap between requests -system.physmem.pageHitRate 82.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75547080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 41146875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 269825400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 133008480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89192778480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36154606095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 800813931750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 926680844160 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.855224 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1310352812250 # Time in different power states -system.physmem_0.memoryStateTime::REF 45599580000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing +system.physmem.readRowHits 69553 # Number of row buffer hits during reads +system.physmem.writeRowHits 37002 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.87 # Row buffer hit rate for writes +system.physmem.avgGap 14354355.89 # Average gap between requests +system.physmem.pageHitRate 83.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 80733240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 43918875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 313622400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 150135120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35737868835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 798596823000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 923983654350 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.983586 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1308907007000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45531980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9807496500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9262769000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 75985560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41344875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 275121600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 139339440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89192778480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35610008715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799074942000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 924409520670 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.996911 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1311143061750 # Time in different power states -system.physmem_1.memoryStateTime::REF 45599580000 # Time in different power states +system.physmem_1.actEnergy 82744200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 44962500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 320439600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 153705600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35470252125 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 802756182000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 927888838905 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.649647 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309307344000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45531980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9002444500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8896844750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4891655 # DTB read hits -system.cpu0.dtb.read_misses 6160 # DTB read misses -system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428724 # DTB read accesses -system.cpu0.dtb.write_hits 3459344 # DTB write hits +system.cpu0.dtb.read_hits 4808616 # DTB read hits +system.cpu0.dtb.read_misses 6111 # DTB read misses +system.cpu0.dtb.read_acv 122 # DTB read access violations +system.cpu0.dtb.read_accesses 428608 # DTB read accesses +system.cpu0.dtb.write_hits 3411554 # DTB write hits system.cpu0.dtb.write_misses 685 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 165214 # DTB write accesses -system.cpu0.dtb.data_hits 8350999 # DTB hits -system.cpu0.dtb.data_misses 6845 # DTB misses -system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 593938 # DTB accesses -system.cpu0.itb.fetch_hits 2745673 # ITB hits -system.cpu0.itb.fetch_misses 3063 # ITB misses -system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2748736 # ITB accesses +system.cpu0.dtb.write_accesses 164458 # DTB write accesses +system.cpu0.dtb.data_hits 8220170 # DTB hits +system.cpu0.dtb.data_misses 6796 # DTB misses +system.cpu0.dtb.data_acv 206 # DTB access violations +system.cpu0.dtb.data_accesses 593066 # DTB accesses +system.cpu0.itb.fetch_hits 2729287 # ITB hits +system.cpu0.itb.fetch_misses 3056 # ITB misses +system.cpu0.itb.fetch_acv 101 # ITB acv +system.cpu0.itb.fetch_accesses 2732343 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -347,32 +363,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928907955 # number of cpu cycles simulated +system.cpu0.numCycles 928788202 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211433 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211368 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105704 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182590 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1820384307000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39982500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 369735500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22821848000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1843615873000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818752965500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39793500 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 370197000 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22435471000 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841598427000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694732 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815789 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694808 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815838 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -408,499 +424,499 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175329 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192244 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1739 +system.cpu0.kern.callpal::total 192212 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1906 +system.cpu0.kern.mode_good::user 1737 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322243 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 30037472000 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2599704500 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810978694500 98.23% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.committedInsts 33609672 # Number of instructions committed -system.cpu0.committedOps 33609672 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31482741 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165750 # Number of float alu accesses -system.cpu0.num_func_calls 801937 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4632385 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31482741 # number of integer instructions -system.cpu0.num_fp_insts 165750 # number of float instructions -system.cpu0.num_int_register_reads 44252512 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23025410 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85784 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 87202 # number of times the floating registers were written -system.cpu0.num_mem_refs 8380910 # number of memory refs -system.cpu0.num_load_insts 4912915 # Number of load instructions -system.cpu0.num_store_insts 3467995 # Number of store instructions -system.cpu0.num_idle_cycles 904803576.609886 # Number of idle cycles -system.cpu0.num_busy_cycles 24104378.390114 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025949 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974051 # Percentage of idle cycles -system.cpu0.Branches 5693464 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1614345 4.80% 4.80% # Class of executed instruction -system.cpu0.op_class::IntAlu 22916205 68.17% 72.97% # Class of executed instruction -system.cpu0.op_class::IntMult 32373 0.10% 73.07% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 73.07% # Class of executed instruction -system.cpu0.op_class::FloatAdd 13074 0.04% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1630 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::MemRead 5044574 15.01% 88.12% # Class of executed instruction -system.cpu0.op_class::MemWrite 3471125 10.33% 98.44% # Class of executed instruction -system.cpu0.op_class::IprAccess 523401 1.56% 100.00% # Class of executed instruction +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390854 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29766458500 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2570000000 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809261966500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4176 # number of times the context was actually changed +system.cpu0.committedInsts 30028359 # Number of instructions committed +system.cpu0.committedOps 30028359 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 27949209 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163605 # Number of float alu accesses +system.cpu0.num_func_calls 796078 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3573160 # number of instructions that are conditional controls +system.cpu0.num_int_insts 27949209 # number of integer instructions +system.cpu0.num_fp_insts 163605 # number of float instructions +system.cpu0.num_int_register_reads 38472094 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20603467 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84586 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86140 # number of times the floating registers were written +system.cpu0.num_mem_refs 8249833 # number of memory refs +system.cpu0.num_load_insts 4829697 # Number of load instructions +system.cpu0.num_store_insts 3420136 # Number of store instructions +system.cpu0.num_idle_cycles 907169648.432742 # Number of idle cycles +system.cpu0.num_busy_cycles 21618553.567258 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023276 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976724 # Percentage of idle cycles +system.cpu0.Branches 4625246 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1572413 5.24% 5.24% # Class of executed instruction +system.cpu0.op_class::IntAlu 19517057 64.98% 70.22% # Class of executed instruction +system.cpu0.op_class::IntMult 31821 0.11% 70.32% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.32% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12868 0.04% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1602 0.01% 70.37% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::MemRead 4960051 16.51% 86.88% # Class of executed instruction +system.cpu0.op_class::MemWrite 3423231 11.40% 98.28% # Class of executed instruction +system.cpu0.op_class::IprAccess 516318 1.72% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 33616727 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1394181 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13501786 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1394693 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.680830 # Average number of references to valid blocks. +system.cpu0.op_class::total 30035361 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1394566 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13521910 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1395078 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.692583 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.971999 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 119.140649 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.885165 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499945 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.232697 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.267354 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.707457 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 77.564418 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.725941 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503335 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.151493 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345168 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 64418479 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 64418479 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4048167 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1034034 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2748996 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7831197 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3168136 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 783371 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1326904 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5278411 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114770 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19408 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 58589 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 192767 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123716 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21423 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54189 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199328 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7216303 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1817405 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 4075900 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13109608 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7216303 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1817405 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 4075900 # number of overall hits -system.cpu0.dcache.overall_hits::total 13109608 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 729786 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 87342 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 544507 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1361635 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 166271 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 38690 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 668713 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 873674 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9504 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2145 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7260 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18909 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 22 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 25 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 896057 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 126032 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1213220 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2235309 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 896057 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 126032 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1213220 # number of overall misses -system.cpu0.dcache.overall_misses::total 2235309 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2315387000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8759785000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11075172000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2131162500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29470342228 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 31601504728 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28793000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 133300000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 162093000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 511000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 511000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4446549500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 38230127228 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42676676728 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4446549500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 38230127228 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42676676728 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4777953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1121376 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3293503 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9192832 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3334407 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 822061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1995617 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6152085 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124274 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21553 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 65849 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 211676 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123719 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21423 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 54211 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199353 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8112360 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1943437 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5289120 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15344917 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8112360 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1943437 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5289120 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15344917 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.152740 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.077888 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.165328 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.148119 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049865 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047065 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.335091 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.142013 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076476 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099522 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.110252 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089330 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000024 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000406 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110456 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.064850 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229380 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.145671 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110456 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064850 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229380 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.145671 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26509.434178 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16087.552593 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8133.730405 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55083.031791 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 44070.239741 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36170.819697 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13423.310023 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 18360.881543 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8572.267174 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 23227.272727 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20440 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35281.115114 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31511.289979 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19092.070371 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35281.115114 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31511.289979 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19092.070371 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1649152 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2017 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 58664 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.111823 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 183.363636 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 836302 # number of writebacks -system.cpu0.dcache.writebacks::total 836302 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 286455 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 286455 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 571181 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 571181 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1840 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1840 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 857636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 857636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 857636 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 857636 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 87342 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 258052 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 345394 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38690 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 97532 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 136222 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2145 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5420 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7565 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 22 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 22 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 126032 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 355584 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 481616 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 126032 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 355584 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 481616 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1346 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1396 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2742 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1629 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 1971 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3600 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2975 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3367 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6342 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2228045000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4632792500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860837500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092472500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4580895301 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6673367801 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26648000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69159500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95807500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 489000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 489000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4320517500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9213687801 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13534205301 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4320517500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9213687801 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13534205301 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296833500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 314974000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 611807500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 296833500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 314974000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 611807500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.077888 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.078352 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037572 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047065 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048873 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022142 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099522 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.082310 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035739 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000406 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000110 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.064850 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067229 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.064850 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.067229 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031386 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25509.434178 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17952.941655 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19863.800471 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54083.031791 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46968.126369 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48988.913692 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12423.310023 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12760.055351 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12664.573695 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 22227.272727 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22227.272727 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34281.115114 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25911.424026 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28101.652148 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34281.115114 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25911.424026 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28101.652148 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220530.089153 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225626.074499 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223124.544128 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 99775.966387 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 93547.371547 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96469.173762 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 969392 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.185439 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43108744 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 969903 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 44.446449 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10560905500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 255.222519 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 86.294219 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 169.668701 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.498481 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.168543 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.331384 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998409 # Average percentage of cache occupancy +system.cpu0.dcache.tags.tag_accesses 64423039 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 64423039 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3984765 # 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miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050308 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.321337 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.138254 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075910 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101161 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.112247 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090012 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000470 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000135 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109632 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28879.706563 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22966.792888 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14266.212838 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 997927 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2476 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 58775 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 19 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.978766 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 130.315789 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 836681 # number of writebacks +system.cpu0.dcache.writebacks::total 836681 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 375591500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 624285000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 248693500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 375591500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 624285000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081806 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.080779 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039645 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050308 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047420 # 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average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 217860.498840 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218663.747811 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97107.965638 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 99971.120575 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98810.541311 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 969876 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.205246 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39683030 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 970387 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 40.894025 # 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mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010285 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017096 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.107958 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010285 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017096 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.107958 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010285 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13877.737624 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13877.737624 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13877.737624 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 969876 # number of writebacks +system.cpu0.icache.writebacks::total 969876 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22058 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 22058 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22058 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22058 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22058 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22058 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126603 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 334632 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 461235 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 126603 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 334632 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 461235 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 126603 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 334632 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 461235 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1685858000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4399066985 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6084924985 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1685858000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4399066985 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6084924985 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1685858000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4399066985 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6084924985 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011339 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011339 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011339 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13192.678320 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1140904 # DTB read hits -system.cpu1.dtb.read_misses 1286 # DTB read misses -system.cpu1.dtb.read_acv 30 # DTB read access violations -system.cpu1.dtb.read_accesses 118136 # DTB read accesses -system.cpu1.dtb.write_hits 843894 # DTB write hits -system.cpu1.dtb.write_misses 157 # DTB write misses -system.cpu1.dtb.write_acv 18 # DTB write access violations -system.cpu1.dtb.write_accesses 48616 # DTB write accesses -system.cpu1.dtb.data_hits 1984798 # DTB hits -system.cpu1.dtb.data_misses 1443 # DTB misses -system.cpu1.dtb.data_acv 48 # DTB access violations -system.cpu1.dtb.data_accesses 166752 # DTB accesses -system.cpu1.itb.fetch_hits 760414 # ITB hits -system.cpu1.itb.fetch_misses 659 # ITB misses -system.cpu1.itb.fetch_acv 28 # ITB acv -system.cpu1.itb.fetch_accesses 761073 # ITB accesses +system.cpu1.dtb.read_hits 1184324 # DTB read hits +system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_acv 34 # DTB read access violations +system.cpu1.dtb.read_accesses 141546 # DTB read accesses +system.cpu1.dtb.write_hits 885341 # DTB write hits +system.cpu1.dtb.write_misses 169 # DTB write misses +system.cpu1.dtb.write_acv 22 # DTB write access violations +system.cpu1.dtb.write_accesses 57820 # DTB write accesses +system.cpu1.dtb.data_hits 2069665 # DTB hits +system.cpu1.dtb.data_misses 1485 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 199366 # DTB accesses +system.cpu1.itb.fetch_hits 852668 # ITB hits +system.cpu1.itb.fetch_misses 656 # ITB misses +system.cpu1.itb.fetch_acv 33 # ITB acv +system.cpu1.itb.fetch_accesses 853324 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -913,7 +929,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953506414 # number of cpu cycles simulated +system.cpu1.numCycles 953375365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -933,94 +949,94 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7462812 # Number of instructions committed -system.cpu1.committedOps 7462812 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6940057 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 40181 # Number of float alu accesses -system.cpu1.num_func_calls 208293 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 930314 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6940057 # number of integer instructions -system.cpu1.num_fp_insts 40181 # number of float instructions -system.cpu1.num_int_register_reads 9712470 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5067319 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 20912 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21313 # number of times the floating registers were written -system.cpu1.num_mem_refs 1991766 # number of memory refs -system.cpu1.num_load_insts 1145591 # Number of load instructions -system.cpu1.num_store_insts 846175 # Number of store instructions -system.cpu1.num_idle_cycles 924284293.570885 # Number of idle cycles -system.cpu1.num_busy_cycles 29222120.429115 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030647 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969353 # Percentage of idle cycles -system.cpu1.Branches 1204252 # Number of branches fetched -system.cpu1.op_class::No_OpClass 396048 5.31% 5.31% # Class of executed instruction -system.cpu1.op_class::IntAlu 4903561 65.69% 71.00% # Class of executed instruction -system.cpu1.op_class::IntMult 7744 0.10% 71.10% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.10% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3327 0.04% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 440 0.01% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::MemRead 1174639 15.74% 86.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 847384 11.35% 98.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 131160 1.76% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7542911 # Number of instructions committed +system.cpu1.committedOps 7542911 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7009980 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44709 # Number of float alu accesses +system.cpu1.num_func_calls 205791 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 911955 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7009980 # number of integer instructions +system.cpu1.num_fp_insts 44709 # number of float instructions +system.cpu1.num_int_register_reads 9753806 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5113025 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24116 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24503 # number of times the floating registers were written +system.cpu1.num_mem_refs 2076660 # number of memory refs +system.cpu1.num_load_insts 1189039 # Number of load instructions +system.cpu1.num_store_insts 887621 # Number of store instructions +system.cpu1.num_idle_cycles 923368497.825425 # Number of idle cycles +system.cpu1.num_busy_cycles 30006867.174575 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031474 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968526 # Percentage of idle cycles +system.cpu1.Branches 1183564 # Number of branches fetched +system.cpu1.op_class::No_OpClass 404590 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 4887103 64.78% 70.14% # Class of executed instruction +system.cpu1.op_class::IntMult 8470 0.11% 70.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.25% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5131 0.07% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.33% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::MemRead 1217523 16.14% 86.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 888839 11.78% 98.25% # Class of executed instruction +system.cpu1.op_class::IprAccess 131986 1.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7464303 # Class of executed instruction -system.cpu2.branchPred.lookups 11115445 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10184701 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 190030 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8583596 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6500261 # Number of BTB hits +system.cpu1.op_class::total 7544452 # Class of executed instruction +system.cpu2.branchPred.lookups 10195062 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9245801 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 194837 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7645666 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5489178 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 75.728879 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 358939 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 14100 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1769440 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 184650 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 1584790 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 83567 # Number of mispredicted indirect branches. +system.cpu2.branchPred.BTBHitPct 71.794635 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 367323 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 14555 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1840410 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 186758 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 1653652 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 86236 # Number of mispredicted indirect branches. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3745527 # DTB read hits -system.cpu2.dtb.read_misses 14326 # DTB read misses -system.cpu2.dtb.read_acv 141 # DTB read access violations -system.cpu2.dtb.read_accesses 264538 # DTB read accesses -system.cpu2.dtb.write_hits 2181134 # DTB write hits -system.cpu2.dtb.write_misses 3579 # DTB write misses -system.cpu2.dtb.write_acv 134 # DTB write access violations -system.cpu2.dtb.write_accesses 94734 # DTB write accesses -system.cpu2.dtb.data_hits 5926661 # DTB hits -system.cpu2.dtb.data_misses 17905 # DTB misses -system.cpu2.dtb.data_acv 275 # DTB access violations -system.cpu2.dtb.data_accesses 359272 # DTB accesses -system.cpu2.itb.fetch_hits 551804 # ITB hits -system.cpu2.itb.fetch_misses 2698 # ITB misses -system.cpu2.itb.fetch_acv 198 # ITB acv -system.cpu2.itb.fetch_accesses 554502 # ITB accesses +system.cpu2.dtb.read_hits 3794321 # DTB read hits +system.cpu2.dtb.read_misses 14980 # DTB read misses +system.cpu2.dtb.read_acv 154 # DTB read access violations +system.cpu2.dtb.read_accesses 231448 # DTB read accesses +system.cpu2.dtb.write_hits 2188085 # DTB write hits +system.cpu2.dtb.write_misses 3764 # DTB write misses +system.cpu2.dtb.write_acv 156 # DTB write access violations +system.cpu2.dtb.write_accesses 84759 # DTB write accesses +system.cpu2.dtb.data_hits 5982406 # DTB hits +system.cpu2.dtb.data_misses 18744 # DTB misses +system.cpu2.dtb.data_acv 310 # DTB access violations +system.cpu2.dtb.data_accesses 316207 # DTB accesses +system.cpu2.itb.fetch_hits 533759 # ITB hits +system.cpu2.itb.fetch_misses 2736 # ITB misses +system.cpu2.itb.fetch_acv 191 # ITB acv +system.cpu2.itb.fetch_accesses 536495 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1033,303 +1049,303 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 32148288 # number of cpu cycles simulated +system.cpu2.numCycles 30327275 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9118770 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 42633402 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 11115445 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 7043850 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 20872660 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 537018 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10698 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1962 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 54145 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 92611 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 906 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3019400 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 130811 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.icacheStallCycles 9354335 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40099246 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10195062 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6043259 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18967134 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 549482 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 7 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 11119 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1939 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 54610 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 90342 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 596 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3095865 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 133552 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 30420027 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.401491 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.386543 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 28754585 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.394534 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.444600 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20612041 67.76% 67.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 327280 1.08% 68.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509415 1.67% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5051332 16.61% 87.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 910040 2.99% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 211501 0.70% 90.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 256047 0.84% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 439619 1.45% 93.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2102752 6.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 19879004 69.13% 69.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 339943 1.18% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516791 1.80% 72.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4053539 14.10% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 887171 3.09% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 213563 0.74% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 261735 0.91% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 444517 1.55% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2158322 7.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 30420027 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.345755 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.326148 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7385112 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13918236 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8048801 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 564027 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 258008 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 221892 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 11066 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 38888307 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 34887 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 258008 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7685688 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4963925 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6082795 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8292905 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2890873 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 37903882 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 59292 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 377519 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 110958 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1815831 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 25463853 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 47138476 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 47075647 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 58641 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22316309 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 3147544 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 533093 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 73531 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3880120 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3861851 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2321017 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 521824 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 313958 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 35078134 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 686210 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34388477 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 25878 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 3859283 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1728855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 496373 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 30420027 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.130455 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.630155 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 28754585 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.336168 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.322217 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7569976 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 12996616 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7107544 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 570612 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 263955 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 225265 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 11264 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36283979 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 35882 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 263955 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7872857 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4931794 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5918579 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7355041 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2166486 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35279837 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 60983 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 402801 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 76926 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1084115 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23748051 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43586446 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43526101 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56436 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20540056 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 3207995 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 542145 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 75307 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3912291 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3917277 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2333144 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 542030 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 329847 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32377023 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 701408 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 31676973 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 27053 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 3928896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1754776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 507029 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 28754585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.101632 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.635117 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18175934 59.75% 59.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2731876 8.98% 68.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1376382 4.52% 73.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5800287 19.07% 92.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1083705 3.56% 95.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 612376 2.01% 97.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 420135 1.38% 99.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 169190 0.56% 99.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 50142 0.16% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17376990 60.43% 60.43% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2804831 9.75% 70.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1408095 4.90% 75.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4807285 16.72% 91.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1079199 3.75% 95.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 630267 2.19% 97.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 421060 1.46% 99.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 175258 0.61% 99.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 51600 0.18% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 30420027 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 28754585 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 80804 19.32% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 207140 49.52% 68.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 130362 31.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 83759 19.66% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 210235 49.34% 69.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 132097 31.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 3134 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 27917447 81.18% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21186 0.06% 81.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 22118 0.06% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3912960 11.38% 92.70% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2212878 6.43% 99.14% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 297188 0.86% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 25141274 79.37% 79.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20994 0.07% 79.44% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 79.44% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20528 0.06% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3966361 12.52% 92.03% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2221145 7.01% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 302997 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34388477 # Type of FU issued -system.cpu2.iq.rate 1.069683 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 418306 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.012164 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 99374264 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39499421 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 33606798 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 266901 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 130860 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122949 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 34661254 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 142395 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 213891 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 31676973 # Type of FU issued +system.cpu2.iq.rate 1.044504 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 426091 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013451 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92299555 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36885759 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 30885842 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 262120 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 128344 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 120451 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 31960571 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 140043 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 222851 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 829369 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1314 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6796 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 267816 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 843917 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1448 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6897 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 272853 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4168 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 214093 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4760 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 213103 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 258008 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4262177 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 221870 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 37207095 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 66855 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3861851 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2321017 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 613182 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 13352 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 173159 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6796 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 74128 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 200909 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 275037 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 34112414 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3770128 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 276063 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 263955 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4308277 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 202891 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34565468 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 70386 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3917277 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2333144 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 625709 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 13182 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 148814 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6897 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 76158 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 205534 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 281692 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31394525 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3819678 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 282448 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1442751 # number of nop insts executed -system.cpu2.iew.exec_refs 5960966 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7830155 # Number of branches executed -system.cpu2.iew.exec_stores 2190838 # Number of stores executed -system.cpu2.iew.exec_rate 1.061096 # Inst execution rate -system.cpu2.iew.wb_sent 33803794 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 33729747 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 19634882 # num instructions producing a value -system.cpu2.iew.wb_consumers 23447045 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.049193 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.837414 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 4049200 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 189837 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 246514 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 29720868 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.113415 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846179 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 1487037 # number of nop insts executed +system.cpu2.iew.exec_refs 6017890 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6848661 # Number of branches executed +system.cpu2.iew.exec_stores 2198212 # Number of stores executed +system.cpu2.iew.exec_rate 1.035191 # Inst execution rate +system.cpu2.iew.wb_sent 31083503 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31006293 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17785830 # num instructions producing a value +system.cpu2.iew.wb_consumers 21615859 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.022390 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.822814 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 4127890 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194379 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 252373 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28042775 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.083004 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.865926 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18948933 63.76% 63.76% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2226621 7.49% 71.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1117677 3.76% 75.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5469793 18.40% 93.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 585496 1.97% 95.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200130 0.67% 96.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 163612 0.55% 96.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 172854 0.58% 97.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 835752 2.81% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18161783 64.76% 64.76% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2276613 8.12% 72.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1151869 4.11% 76.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4491226 16.02% 93.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 562178 2.00% 95.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 204579 0.73% 95.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 167176 0.60% 96.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 177068 0.63% 96.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 850283 3.03% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 29720868 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 33091654 # Number of instructions committed -system.cpu2.commit.committedOps 33091654 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28042775 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30370432 # Number of instructions committed +system.cpu2.commit.committedOps 30370432 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5085683 # Number of memory references committed -system.cpu2.commit.loads 3032482 # Number of loads committed -system.cpu2.commit.membars 66632 # Number of memory barriers committed -system.cpu2.commit.branches 7528249 # Number of branches committed -system.cpu2.commit.fp_insts 118326 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31611835 # Number of committed integer instructions. -system.cpu2.commit.function_calls 236844 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1189725 3.60% 3.60% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 26406955 79.80% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20610 0.06% 83.46% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.46% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21680 0.07% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3099114 9.37% 92.89% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2054816 6.21% 99.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 297188 0.90% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5133651 # Number of memory references committed +system.cpu2.commit.loads 3073360 # Number of loads committed +system.cpu2.commit.membars 68499 # Number of memory barriers committed +system.cpu2.commit.branches 6541282 # Number of branches committed +system.cpu2.commit.fp_insts 116010 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28852886 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241096 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1223345 4.03% 4.03% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 23598567 77.70% 81.73% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20428 0.07% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20084 0.07% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1224 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3141859 10.35% 92.21% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2061928 6.79% 99.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 302997 1.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 33091654 # Class of committed instruction -system.cpu2.commit.bw_lim_events 835752 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 65950880 # The number of ROB reads -system.cpu2.rob.rob_writes 74981980 # The number of ROB writes -system.cpu2.timesIdled 163418 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1728261 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747565688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31905061 # Number of Instructions Simulated -system.cpu2.committedOps 31905061 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.007623 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.007623 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.992434 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.992434 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 44683951 # number of integer regfile reads -system.cpu2.int_regfile_writes 23750131 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73395 # number of floating regfile reads -system.cpu2.fp_regfile_writes 76222 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5369196 # number of misc regfile reads -system.cpu2.misc_regfile_writes 267799 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 30370432 # Class of committed instruction +system.cpu2.commit.bw_lim_events 850283 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 61616016 # The number of ROB reads +system.cpu2.rob.rob_writes 69709723 # The number of ROB writes +system.cpu2.timesIdled 166720 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1572690 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745481695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29149535 # Number of Instructions Simulated +system.cpu2.committedOps 29149535 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.040403 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.040403 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.961166 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.961166 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 41087551 # number of integer regfile reads +system.cpu2.int_regfile_writes 22005301 # number of integer regfile writes +system.cpu2.fp_regfile_reads 71153 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74234 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4377642 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272877 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1344,9 +1360,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51364 # Transaction distribution -system.iobus.trans_dist::WriteResp 51364 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5196 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51362 # Transaction distribution +system.iobus.trans_dist::WriteResp 51362 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1355,11 +1371,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1825 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1368,35 +1384,35 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45584 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2556000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2373500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 130500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 135500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 65000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 56000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6361000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5872500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2150000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2528000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 80490654 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 89904673 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9084000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9173000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 15688000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261471 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254561 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694927317000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261471 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078842 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078842 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693898501000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254561 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078410 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078410 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1410,14 +1426,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9857962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9857962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 1957317692 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1957317692 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 1967175654 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1967175654 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 1967175654 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1967175654 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9598462 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9598462 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2019796211 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2019796211 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 2029394673 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 2029394673 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 2029394673 # number of overall miss cycles +system.iocache.overall_miss_latency::total 2029394673 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1434,14 +1450,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56982.439306 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 56982.439306 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 47105.258279 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 47105.258279 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 47146.211001 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 47146.211001 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 47146.211001 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 47146.211001 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55482.439306 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 55482.439306 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48608.880704 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48608.880704 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 48637.379820 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 48637.379820 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1450,469 +1466,475 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 68 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 68 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 15504 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 15504 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 15572 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 15572 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 15572 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 15572 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6457962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6457962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1181451904 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1181451904 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 1187909866 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1187909866 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 1187909866 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1187909866 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.393064 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.393064 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.373123 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.373123 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.373206 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.373206 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.373206 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.373206 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 94970.029412 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 94970.029412 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76203.038184 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76203.038184 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76284.990110 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76284.990110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76284.990110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76284.990110 # average overall mshr miss latency -system.l2c.tags.replacements 337717 # number of replacements -system.l2c.tags.tagsinuse 65421.749224 # Cycle average of tags in use -system.l2c.tags.total_refs 4019101 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402879 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.975951 # Average number of references to valid blocks. +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17350 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17350 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6098462 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6098462 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1154802593 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1154802593 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 1160901055 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1160901055 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 1160901055 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1160901055 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.415818 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.415818 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87120.885714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 87120.885714 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66828.853762 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66828.853762 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66910.723631 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66910.723631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency +system.l2c.tags.replacements 337756 # number of replacements +system.l2c.tags.tagsinuse 65421.322565 # Cycle average of tags in use +system.l2c.tags.total_refs 4020988 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402918 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.979668 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55335 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 987 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5975 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2686 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55336 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38519512 # Number of tag accesses -system.l2c.tags.data_accesses 38519512 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 836302 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 836302 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 969066 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 969066 # number of WritebackClean hits +system.l2c.tags.tag_accesses 38533534 # Number of tag accesses +system.l2c.tags.data_accesses 38533534 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 836681 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 836681 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 969577 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 969577 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 19 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 91578 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 24802 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 70520 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 321620 # number of demand (read+write) hits -system.l2c.demand_hits::total 1961310 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 508782 # number of overall hits -system.l2c.overall_hits::cpu0.data 579922 # number of overall hits -system.l2c.overall_hits::cpu1.inst 125321 # number of overall hits -system.l2c.overall_hits::cpu1.data 104096 # number of overall hits -system.l2c.overall_hits::cpu2.inst 321569 # number of overall hits -system.l2c.overall_hits::cpu2.data 321620 # number of overall hits -system.l2c.overall_hits::total 1961310 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 14 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 23 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 90271 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 25531 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70542.653738 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207382.404951 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205358.178654 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206160.070053 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91585.122999 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94234.096353 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 93160.335549 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 823896 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 379632 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 295030 # Transaction distribution -system.membus.trans_dist::WriteReq 9812 # Transaction distribution -system.membus.trans_dist::WriteResp 9812 # Transaction distribution -system.membus.trans_dist::WritebackDirty 116832 # Transaction distribution -system.membus.trans_dist::CleanEvict 261846 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # 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Transaction distribution +system.membus.trans_dist::ReadSharedReq 288010 # Transaction distribution +system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 26048 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143608 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 28 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177548 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1287126 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30619392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30664976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33329424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 142 # Total snoops (count) -system.membus.snoop_fanout::samples 840769 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.trans_dist::InvalidateResp 24272 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143724 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 107800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 107800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1285464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30679232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33343552 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 157 # Total snoops (count) +system.membus.snoop_fanout::samples 742227 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001296 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.035978 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840769 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 741265 99.87% 99.87% # Request fanout histogram +system.membus.snoop_fanout::1 962 0.13% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840769 # Request fanout histogram -system.membus.reqLayer0.occupancy 11262500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 742227 # Request fanout histogram +system.membus.reqLayer0.occupancy 10965500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 344258394 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 390337877 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 375059750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 436169750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 358538 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 370538 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4728439 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2363791 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1687 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1128 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1128 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4730181 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2364664 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1038 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1038 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2069439 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 878363 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 969392 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 601395 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 25 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 60 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302550 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302550 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 970097 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1092227 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 14 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 15504 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2909488 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4217684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7127172 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124121024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142832784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266953808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421384 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4223997 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.001001 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.031618 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2070392 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 866358 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 969876 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 609667 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 58 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302472 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302472 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 970586 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1092680 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2910960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4218835 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7129795 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124183936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142881728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 267065664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 338688 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4114055 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000998 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.031568 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4219770 99.90% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4227 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4109951 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4104 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4223997 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1779844500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4114055 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1826321500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 97962 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 680727278 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 692196311 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 738329921 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 770446828 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |