diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt | 2785 |
1 files changed, 1404 insertions, 1381 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 3aeb0bbf5..b0cdac391 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.842592 # Number of seconds simulated -sim_ticks 1842592129000 # Number of ticks simulated -final_tick 1842592129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1842591955000 # Number of ticks simulated +final_tick 1842591955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226605 # Simulator instruction rate (inst/s) -host_op_rate 226605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6393875150 # Simulator tick rate (ticks/s) -host_mem_usage 320256 # Number of bytes of host memory used -host_seconds 288.18 # Real time elapsed on the host -sim_insts 65303087 # Number of instructions simulated -sim_ops 65303087 # Number of ops (including micro ops) simulated +host_inst_rate 212167 # Simulator instruction rate (inst/s) +host_op_rate 212167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5858461865 # Simulator tick rate (ticks/s) +host_mem_usage 373744 # Number of bytes of host memory used +host_seconds 314.52 # Real time elapsed on the host +sim_insts 66730424 # Number of instructions simulated +sim_ops 66730424 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20073664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2246336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 292800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2554880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 480192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20072256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 146880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2246976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2555648 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25796096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 292800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 920256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481536 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481536 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2294 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35099 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4575 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39920 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25796928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 480192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 146880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 921088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7481920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7481920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313629 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39932 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116899 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116899 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10894253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1219117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 158907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1386568 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403077 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116905 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116905 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 260607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10893489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1219465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1386985 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13999895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 158907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4060332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4060332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4060332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10894253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1219117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 158907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1386568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14000348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4060541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4060541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4060541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10893489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1219465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1386985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18060227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81903 # Number of read requests accepted -system.physmem.writeReqs 62699 # Number of write requests accepted -system.physmem.readBursts 81903 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 62699 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5240384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue -system.physmem.bytesWritten 3952512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5241792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4012736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 916 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5341 # Per bank write bursts -system.physmem.perBankRdBursts::1 4966 # Per bank write bursts -system.physmem.perBankRdBursts::2 4940 # Per bank write bursts -system.physmem.perBankRdBursts::3 5071 # Per bank write bursts -system.physmem.perBankRdBursts::4 5028 # Per bank write bursts -system.physmem.perBankRdBursts::5 5062 # Per bank write bursts -system.physmem.perBankRdBursts::6 5140 # Per bank write bursts -system.physmem.perBankRdBursts::7 5148 # Per bank write bursts -system.physmem.perBankRdBursts::8 5331 # Per bank write bursts +system.physmem.bw_total::total 18060889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81945 # Number of read requests accepted +system.physmem.writeReqs 62218 # Number of write requests accepted +system.physmem.readBursts 81945 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 62218 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5243136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue +system.physmem.bytesWritten 3931008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5244480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3981952 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 773 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 65 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5216 # Per bank write bursts +system.physmem.perBankRdBursts::1 4952 # Per bank write bursts +system.physmem.perBankRdBursts::2 4966 # Per bank write bursts +system.physmem.perBankRdBursts::3 5032 # Per bank write bursts +system.physmem.perBankRdBursts::4 5011 # Per bank write bursts +system.physmem.perBankRdBursts::5 5077 # Per bank write bursts +system.physmem.perBankRdBursts::6 5139 # Per bank write bursts +system.physmem.perBankRdBursts::7 5153 # Per bank write bursts +system.physmem.perBankRdBursts::8 5336 # Per bank write bursts system.physmem.perBankRdBursts::9 5012 # Per bank write bursts -system.physmem.perBankRdBursts::10 5278 # Per bank write bursts -system.physmem.perBankRdBursts::11 5132 # Per bank write bursts -system.physmem.perBankRdBursts::12 4684 # Per bank write bursts -system.physmem.perBankRdBursts::13 5065 # Per bank write bursts -system.physmem.perBankRdBursts::14 5602 # Per bank write bursts -system.physmem.perBankRdBursts::15 5081 # Per bank write bursts -system.physmem.perBankWrBursts::0 3943 # Per bank write bursts -system.physmem.perBankWrBursts::1 3578 # Per bank write bursts -system.physmem.perBankWrBursts::2 3780 # Per bank write bursts -system.physmem.perBankWrBursts::3 4114 # Per bank write bursts -system.physmem.perBankWrBursts::4 3703 # Per bank write bursts -system.physmem.perBankWrBursts::5 3530 # Per bank write bursts -system.physmem.perBankWrBursts::6 4127 # Per bank write bursts -system.physmem.perBankWrBursts::7 3704 # Per bank write bursts -system.physmem.perBankWrBursts::8 4410 # Per bank write bursts -system.physmem.perBankWrBursts::9 3736 # Per bank write bursts -system.physmem.perBankWrBursts::10 4083 # Per bank write bursts -system.physmem.perBankWrBursts::11 3942 # Per bank write bursts -system.physmem.perBankWrBursts::12 3446 # Per bank write bursts -system.physmem.perBankWrBursts::13 3846 # Per bank write bursts -system.physmem.perBankWrBursts::14 4153 # Per bank write bursts -system.physmem.perBankWrBursts::15 3663 # Per bank write bursts +system.physmem.perBankRdBursts::10 5284 # Per bank write bursts +system.physmem.perBankRdBursts::11 5137 # Per bank write bursts +system.physmem.perBankRdBursts::12 4814 # Per bank write bursts +system.physmem.perBankRdBursts::13 5083 # Per bank write bursts +system.physmem.perBankRdBursts::14 5582 # Per bank write bursts +system.physmem.perBankRdBursts::15 5130 # Per bank write bursts +system.physmem.perBankWrBursts::0 3820 # Per bank write bursts +system.physmem.perBankWrBursts::1 3672 # Per bank write bursts +system.physmem.perBankWrBursts::2 3762 # Per bank write bursts +system.physmem.perBankWrBursts::3 4075 # Per bank write bursts +system.physmem.perBankWrBursts::4 3759 # Per bank write bursts +system.physmem.perBankWrBursts::5 3520 # Per bank write bursts +system.physmem.perBankWrBursts::6 4123 # Per bank write bursts +system.physmem.perBankWrBursts::7 3706 # Per bank write bursts +system.physmem.perBankWrBursts::8 4379 # Per bank write bursts +system.physmem.perBankWrBursts::9 3471 # Per bank write bursts +system.physmem.perBankWrBursts::10 3889 # Per bank write bursts +system.physmem.perBankWrBursts::11 3981 # Per bank write bursts +system.physmem.perBankWrBursts::12 3541 # Per bank write bursts +system.physmem.perBankWrBursts::13 3879 # Per bank write bursts +system.physmem.perBankWrBursts::14 4169 # Per bank write bursts +system.physmem.perBankWrBursts::15 3676 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1841579852500 # Total gap between requests +system.physmem.totGap 1841579678500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81903 # Read request sizes (log2) +system.physmem.readPktSize::6 81945 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 62699 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 62218 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,193 +153,216 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 414.094414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 234.871610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 395.166984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6979 31.44% 31.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4758 21.43% 52.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1802 8.12% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1018 4.59% 65.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 909 4.09% 69.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 488 2.20% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 377 1.70% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 379 1.71% 75.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5490 24.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22200 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.346604 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1004.576162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2133 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 22279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 411.784371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 233.119875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 394.569349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7102 31.88% 31.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4721 21.19% 53.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1798 8.07% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1010 4.53% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 955 4.29% 69.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 478 2.15% 72.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 370 1.66% 73.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 364 1.63% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5481 24.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22279 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2129 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 38.475810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1006.180082 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2127 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.926464 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.717874 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 36.556650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 42 1.97% 1.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 3 0.14% 2.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 1647 77.14% 79.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 96 4.50% 83.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 109 5.11% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 21 0.98% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 47 2.20% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.66% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 5 0.23% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.19% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 8 0.37% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 8 0.37% 93.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 2 0.09% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.09% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.05% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 13 0.61% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.70% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 12 0.56% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 7 0.33% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 36 1.69% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 13 0.61% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.33% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 7 0.33% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 5 0.23% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.14% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.14% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::296-303 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2135 # Writes before turning the bus around for reads -system.physmem.totQLat 816878250 # Total ticks spent queuing -system.physmem.totMemAccLat 2352147000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9976.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2129 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2129 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 28.850164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.675931 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 36.499081 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.60% 1.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.33% 1.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 1.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 1 0.05% 2.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1615 75.86% 77.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 35 1.64% 79.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10 0.47% 79.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 84 3.95% 83.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 64 3.01% 86.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 45 2.11% 89.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.42% 89.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.52% 90.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 35 1.64% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.23% 91.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 21 0.99% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.09% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.14% 93.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.09% 93.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.23% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.05% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.19% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.05% 93.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.14% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.19% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.05% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.05% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.28% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.09% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.05% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 15 0.70% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.14% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.09% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.05% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.19% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 43 2.02% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.05% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 11 0.52% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.14% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.14% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.09% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 6 0.28% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.19% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.23% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 3 0.14% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.14% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.14% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2129 # Writes before turning the bus around for reads +system.physmem.totQLat 814366500 # Total ticks spent queuing +system.physmem.totMemAccLat 2350441500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 409620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9940.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28726.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28690.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 70255 # Number of row buffer hits during reads -system.physmem.writeRowHits 51184 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.84 # Row buffer hit rate for writes -system.physmem.avgGap 12735507.48 # Average gap between requests -system.physmem.pageHitRate 84.53 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1767479155500 # Time in different power states -system.physmem.memoryStateTime::REF 61527960000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13578075750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 83696760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 84135240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 45667875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 45907125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 317428800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 321243000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 197503920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 202687920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 120348689760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 120348689760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 46124478945 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 45810126225 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1065091037250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1065366785250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1232208503310 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1232179574520 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.738964 # Core power per rank (mW) -system.physmem.averagePower::1 668.723264 # Core power per rank (mW) +system.physmem.readRowHits 70260 # Number of row buffer hits during reads +system.physmem.writeRowHits 50807 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.69 # Row buffer hit rate for writes +system.physmem.avgGap 12774287.98 # Average gap between requests +system.physmem.pageHitRate 84.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 83779920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45618375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 316258800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 197231760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35724246975 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 802806617250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 928299910200 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.726630 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309959191250 # Time in different power states +system.physmem_0.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9222216250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 84649320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 46030875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 322748400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 200782800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35431940430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799831550250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 925043859195 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.972279 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1310405285500 # Time in different power states +system.physmem_1.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8771812500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4840766 # DTB read hits +system.cpu0.dtb.read_hits 4841130 # DTB read hits system.cpu0.dtb.read_misses 6162 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 429577 # DTB read accesses -system.cpu0.dtb.write_hits 3449248 # DTB write hits +system.cpu0.dtb.write_hits 3448228 # DTB write hits system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 85 # DTB write access violations system.cpu0.dtb.write_accesses 165228 # DTB write accesses -system.cpu0.dtb.data_hits 8290014 # DTB hits +system.cpu0.dtb.data_hits 8289358 # DTB hits system.cpu0.dtb.data_misses 6850 # DTB misses system.cpu0.dtb.data_acv 211 # DTB access violations system.cpu0.dtb.data_accesses 594805 # DTB accesses -system.cpu0.itb.fetch_hits 2745005 # ITB hits +system.cpu0.itb.fetch_hits 2744473 # ITB hits system.cpu0.itb.fetch_misses 3071 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2748076 # ITB accesses +system.cpu0.itb.fetch_accesses 2747544 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -352,87 +375,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 930170502 # number of cpu cycles simulated +system.cpu0.numCycles 929111283 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31084978 # Number of instructions committed -system.cpu0.committedOps 31084978 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28990115 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165280 # Number of float alu accesses -system.cpu0.num_func_calls 801354 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3884267 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28990115 # number of integer instructions -system.cpu0.num_fp_insts 165280 # number of float instructions -system.cpu0.num_int_register_reads 40144651 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21293303 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85481 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86924 # number of times the floating registers were written -system.cpu0.num_mem_refs 8319976 # number of memory refs -system.cpu0.num_load_insts 4862063 # Number of load instructions -system.cpu0.num_store_insts 3457913 # Number of store instructions -system.cpu0.num_idle_cycles 907838728.357051 # Number of idle cycles -system.cpu0.num_busy_cycles 22331773.642949 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024008 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975992 # Percentage of idle cycles -system.cpu0.Branches 4943919 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1583961 5.09% 5.09% # Class of executed instruction -system.cpu0.op_class::IntAlu 20486094 65.89% 70.98% # Class of executed instruction -system.cpu0.op_class::IntMult 31888 0.10% 71.09% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.09% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12950 0.04% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.01% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::MemRead 4993462 16.06% 87.19% # Class of executed instruction -system.cpu0.op_class::MemWrite 3461022 11.13% 98.32% # Class of executed instruction -system.cpu0.op_class::IprAccess 521056 1.68% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30392058 # Number of instructions committed +system.cpu0.committedOps 30392058 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28296981 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 165313 # Number of float alu accesses +system.cpu0.num_func_calls 800920 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3653475 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28296981 # number of integer instructions +system.cpu0.num_fp_insts 165313 # number of float instructions +system.cpu0.num_int_register_reads 38988704 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20831324 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85482 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86956 # number of times the floating registers were written +system.cpu0.num_mem_refs 8319320 # number of memory refs +system.cpu0.num_load_insts 4862427 # Number of load instructions +system.cpu0.num_store_insts 3456893 # Number of store instructions +system.cpu0.num_idle_cycles 905971177.002448 # Number of idle cycles +system.cpu0.num_busy_cycles 23140105.997552 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024906 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975094 # Percentage of idle cycles +system.cpu0.Branches 4712544 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1584509 5.21% 5.21% # Class of executed instruction +system.cpu0.op_class::IntAlu 19793641 65.11% 70.32% # Class of executed instruction +system.cpu0.op_class::IntMult 31883 0.10% 70.43% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.43% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12951 0.04% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1606 0.01% 70.48% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::MemRead 4993701 16.43% 86.90% # Class of executed instruction +system.cpu0.op_class::MemWrite 3459999 11.38% 98.29% # Class of executed instruction +system.cpu0.op_class::IprAccess 520829 1.71% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31092039 # Class of executed instruction +system.cpu0.op_class::total 30399119 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211371 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6424 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211373 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182570 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105693 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819773509500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38545500 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357643000 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22421661500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842591359500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1819763275500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38885000 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357575500 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22431449500 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842591185500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694761 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815808 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815799 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -471,7 +494,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175311 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -480,266 +503,266 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192226 # number of callpals executed +system.cpu0.kern.callpal::total 192228 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1740 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::kernel 1910 +system.cpu0.kern.mode_good::user 1740 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322526 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29639680500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2561811500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810389863000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.391474 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29641344500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2562591500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810387245000 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4177 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393201 # number of replacements +system.cpu0.dcache.tags.replacements 1393017 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13277254 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393713 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.526534 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13281490 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393529 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.530831 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 261.608452 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.750107 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 175.639259 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.510954 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.145996 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.343045 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.752731 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 75.043138 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.201949 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509283 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146569 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.344144 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63354718 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63354718 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4014926 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1052133 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2504051 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7571110 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157714 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 807247 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357321 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5322282 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114982 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18680 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50783 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184445 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123850 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20650 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54829 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199329 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7172640 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1859380 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3861372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12893392 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7172640 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1859380 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3861372 # number of overall hits -system.cpu0.dcache.overall_hits::total 12893392 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 712217 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 95395 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 559235 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1366847 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 166399 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43585 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 617129 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 827113 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9420 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2097 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7598 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19115 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63366474 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63366474 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4014509 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1053432 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2506621 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7574562 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3156846 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 808200 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1357961 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5323007 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114880 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18791 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50813 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16607.100185 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8033.386588 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10400 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27725.678227 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24741.448848 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15022.272281 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27725.678227 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24741.448848 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15022.272281 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 825872 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 866 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 61038 # number of cycles access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10111.111111 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15004.795330 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15004.795330 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 825255 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1343 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 61465 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.530456 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 96.222222 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.426422 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 149.222222 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835902 # number of writebacks -system.cpu0.dcache.writebacks::total 835902 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 293112 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 293112 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 524642 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 524642 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1568 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1568 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 817754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 817754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 817754 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 817754 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 95395 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 266123 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 361518 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43585 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92487 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 136072 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2097 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6030 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8127 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 138980 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 358610 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 497590 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 138980 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 358610 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 497590 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2005063500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4453995148 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6459058648 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1554433740 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2785719201 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4340152941 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23457750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72881252 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96339002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3559497240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7239714349 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10799211589 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3559497240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7239714349 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10799211589 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248461000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342715000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591176000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 319650500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 420043000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 739693500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 568111500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762758000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1330869500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083131 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086875 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040447 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051226 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046842 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022128 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100929 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103287 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.039924 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000146 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069547 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071185 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032981 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069547 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071185 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032981 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21018.538707 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.603555 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17866.492534 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35664.419869 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30120.116351 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31896.003153 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11186.337625 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12086.443118 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.189984 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835667 # number of writebacks +system.cpu0.dcache.writebacks::total 835667 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292188 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 292188 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 524505 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 524505 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 816693 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 816693 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 816693 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 816693 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 94552 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 265940 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 360492 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43595 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92528 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 136123 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2104 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5986 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8090 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 138147 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 358468 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 496615 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 138147 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 358468 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 496615 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1996702750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4449426882 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6446129632 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1557368490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2781486410 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4338854900 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23520500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72740751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96261251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3554071240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7230913292 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10784984532 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3554071240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7230913292 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10784984532 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249355000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342279000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591634000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320316500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419818000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740134500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569671500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762097000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1331768500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082364 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086774 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040322 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051180 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046850 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022134 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100694 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102554 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.039743 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000128 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032909 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032909 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21117.509413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16730.942626 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17881.477625 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35723.557518 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30061.023798 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31874.517165 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.944867 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12151.812730 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.794932 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25611.578932 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20188.266777 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21703.031791 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25611.578932 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20188.266777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21703.031791 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -750,163 +773,163 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 964194 # 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Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998429 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 964323 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.193139 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39678129 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 964834 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 41.124306 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10191163250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.937948 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.959779 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 181.295411 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.515504 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.128828 # 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number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 124188 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 326610 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 450798 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 124188 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 326610 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 450798 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1522394000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982795175 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5505189175 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1522394000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982795175 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5505189175 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1522394000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982795175 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5505189175 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011087 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011087 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011087 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1166206 # DTB read hits +system.cpu1.dtb.read_hits 1166781 # DTB read hits system.cpu1.dtb.read_misses 1314 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations system.cpu1.dtb.read_accesses 141633 # DTB read accesses -system.cpu1.dtb.write_hits 871808 # DTB write hits +system.cpu1.dtb.write_hits 872888 # DTB write hits system.cpu1.dtb.write_misses 168 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations system.cpu1.dtb.write_accesses 57088 # DTB write accesses -system.cpu1.dtb.data_hits 2038014 # DTB hits +system.cpu1.dtb.data_hits 2039669 # DTB hits system.cpu1.dtb.data_misses 1482 # DTB misses system.cpu1.dtb.data_acv 56 # DTB access violations system.cpu1.dtb.data_accesses 198721 # DTB accesses -system.cpu1.itb.fetch_hits 847614 # ITB hits +system.cpu1.itb.fetch_hits 848090 # ITB hits system.cpu1.itb.fetch_misses 662 # ITB misses system.cpu1.itb.fetch_acv 32 # ITB acv -system.cpu1.itb.fetch_accesses 848276 # ITB accesses +system.cpu1.itb.fetch_accesses 848752 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -919,64 +942,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953409628 # number of cpu cycles simulated +system.cpu1.numCycles 953408444 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7451589 # Number of instructions committed -system.cpu1.committedOps 7451589 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6926409 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43920 # Number of float alu accesses -system.cpu1.num_func_calls 202937 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 904115 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6926409 # number of integer instructions -system.cpu1.num_fp_insts 43920 # number of float instructions -system.cpu1.num_int_register_reads 9636713 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5051586 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23745 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24097 # number of times the floating registers were written -system.cpu1.num_mem_refs 2044932 # number of memory refs -system.cpu1.num_load_insts 1170872 # Number of load instructions -system.cpu1.num_store_insts 874060 # Number of store instructions -system.cpu1.num_idle_cycles 925046236.205368 # Number of idle cycles -system.cpu1.num_busy_cycles 28363391.794632 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029749 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970251 # Percentage of idle cycles -system.cpu1.Branches 1171500 # Number of branches fetched -system.cpu1.op_class::No_OpClass 399169 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 4836084 64.89% 70.24% # Class of executed instruction -system.cpu1.op_class::IntMult 8208 0.11% 70.35% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5096 0.07% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::MemRead 1198833 16.08% 86.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 875271 11.74% 98.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 129656 1.74% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7454598 # Number of instructions committed +system.cpu1.committedOps 7454598 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6929268 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 43953 # Number of float alu accesses +system.cpu1.num_func_calls 203515 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 903765 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6929268 # number of integer instructions +system.cpu1.num_fp_insts 43953 # number of float instructions +system.cpu1.num_int_register_reads 9641119 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5054145 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 23746 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written +system.cpu1.num_mem_refs 2046592 # number of memory refs +system.cpu1.num_load_insts 1171450 # Number of load instructions +system.cpu1.num_store_insts 875142 # Number of store instructions +system.cpu1.num_idle_cycles 924951081.946169 # Number of idle cycles +system.cpu1.num_busy_cycles 28457362.053831 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029848 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970152 # Percentage of idle cycles +system.cpu1.Branches 1171881 # Number of branches fetched +system.cpu1.op_class::No_OpClass 398972 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 4837309 64.88% 70.23% # Class of executed instruction +system.cpu1.op_class::IntMult 8193 0.11% 70.34% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5097 0.07% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::MemRead 1199545 16.09% 86.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 876356 11.75% 98.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 129854 1.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7453127 # Class of executed instruction +system.cpu1.op_class::total 7456136 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -994,35 +1017,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8975833 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8240091 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125146 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6986744 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 4884457 # Number of BTB hits +system.cpu2.branchPred.lookups 9673449 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8936896 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 125098 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7569787 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5584968 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 69.910347 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 298693 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7800 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 73.779725 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 299823 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7809 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3460113 # DTB read hits -system.cpu2.dtb.read_misses 12059 # DTB read misses -system.cpu2.dtb.read_acv 120 # DTB read access violations -system.cpu2.dtb.read_accesses 225843 # DTB read accesses -system.cpu2.dtb.write_hits 2120785 # DTB write hits -system.cpu2.dtb.write_misses 2578 # DTB write misses -system.cpu2.dtb.write_acv 111 # DTB write access violations -system.cpu2.dtb.write_accesses 84303 # DTB write accesses -system.cpu2.dtb.data_hits 5580898 # DTB hits -system.cpu2.dtb.data_misses 14637 # DTB misses -system.cpu2.dtb.data_acv 231 # DTB access violations -system.cpu2.dtb.data_accesses 310146 # DTB accesses -system.cpu2.itb.fetch_hits 534656 # ITB hits -system.cpu2.itb.fetch_misses 5715 # ITB misses -system.cpu2.itb.fetch_acv 156 # ITB acv -system.cpu2.itb.fetch_accesses 540371 # ITB accesses +system.cpu2.dtb.read_hits 3461968 # DTB read hits +system.cpu2.dtb.read_misses 12174 # DTB read misses +system.cpu2.dtb.read_acv 114 # DTB read access violations +system.cpu2.dtb.read_accesses 224881 # DTB read accesses +system.cpu2.dtb.write_hits 2122047 # DTB write hits +system.cpu2.dtb.write_misses 2563 # DTB write misses +system.cpu2.dtb.write_acv 106 # DTB write access violations +system.cpu2.dtb.write_accesses 83942 # DTB write accesses +system.cpu2.dtb.data_hits 5584015 # DTB hits +system.cpu2.dtb.data_misses 14737 # DTB misses +system.cpu2.dtb.data_acv 220 # DTB access violations +system.cpu2.dtb.data_accesses 308823 # DTB accesses +system.cpu2.itb.fetch_hits 534012 # ITB hits +system.cpu2.itb.fetch_misses 5788 # ITB misses +system.cpu2.itb.fetch_acv 158 # ITB acv +system.cpu2.itb.fetch_accesses 539800 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1035,305 +1058,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 29309170 # number of cpu cycles simulated +system.cpu2.numCycles 30013580 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9355872 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 35312418 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8975833 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5183150 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 17863271 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 408038 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 9363383 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37425902 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9673449 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5884791 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18558568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 408186 # Number of cycles fetch has spent squashing system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1926 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 226509 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 98836 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2801357 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 93254 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27760138 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.272055 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.388957 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.MiscStallCycles 10133 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 231517 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 99918 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 308 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2804138 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 92736 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 28469903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.314578 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.374234 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20067804 72.29% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312324 1.13% 73.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 471431 1.70% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3277065 11.80% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 832356 3.00% 89.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194310 0.70% 90.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 239050 0.86% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 435621 1.57% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1930177 6.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20072313 70.50% 70.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 312422 1.10% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 471724 1.66% 73.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3982470 13.99% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 833365 2.93% 90.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 193345 0.68% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 238464 0.84% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 434747 1.53% 93.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1931053 6.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27760138 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.306247 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.204825 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7663207 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13056286 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6071971 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 531660 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 191161 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 175121 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13218 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 31964587 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42189 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 191161 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7944282 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4747926 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6306317 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6292094 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2032514 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 31148031 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68690 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 405455 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57635 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 961672 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 20857546 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 38489272 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 38429323 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56078 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 18957389 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1900157 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 527032 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63032 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3906781 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3488819 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2211142 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 463556 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329659 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 28630875 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 676639 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 28279580 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16369 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2426454 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1141058 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 483735 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27760138 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.018712 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.595651 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 28469903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.322302 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.246966 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7673000 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13050358 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6778876 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 530616 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 191226 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 175016 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13225 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34075356 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 43360 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 191226 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7953535 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4758129 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6310003 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6998808 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2012380 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33260601 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 68695 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 404029 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57097 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 943831 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 22264761 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41311324 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41251440 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56013 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20369021 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1895740 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 527174 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63098 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3903100 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3489643 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2214871 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 462169 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 329723 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30742037 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 676819 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30393110 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 17376 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2421658 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1144384 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 483915 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 28469903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.067552 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.605150 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17419876 62.75% 62.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2765921 9.96% 72.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1372782 4.95% 77.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4034544 14.53% 92.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1009748 3.64% 95.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 570537 2.06% 97.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 383332 1.38% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154390 0.56% 99.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 49008 0.18% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17422923 61.20% 61.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2767864 9.72% 70.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1373994 4.83% 75.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4735624 16.63% 92.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1013556 3.56% 95.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 570411 2.00% 97.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 382804 1.34% 99.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 154533 0.54% 99.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 48194 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27760138 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 28469903 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 83197 21.73% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 176333 46.06% 67.80% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 123266 32.20% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 82144 21.47% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 176872 46.24% 67.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 123495 32.29% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 22202311 78.51% 78.52% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21087 0.07% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20489 0.07% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3587142 12.68% 91.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2144327 7.58% 98.94% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 300564 1.06% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24311305 79.99% 80.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21079 0.07% 80.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 80.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20485 0.07% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3589842 11.81% 91.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2146129 7.06% 99.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 300610 0.99% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 28279580 # Type of FU issued -system.cpu2.iq.rate 0.964871 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 382796 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013536 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 84465202 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 31620396 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27707676 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 253261 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119445 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 116967 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 28524107 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 135829 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206522 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30393110 # Type of FU issued +system.cpu2.iq.rate 1.012645 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 382511 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.012585 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 89403074 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33727235 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29817840 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 252936 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119279 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 116815 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30637549 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 135632 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205530 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 435956 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1412 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6012 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178431 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 436638 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1484 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6154 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 181627 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5029 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 168380 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4994 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 170094 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 191161 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3997544 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 279888 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 30686163 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51755 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3488819 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2211142 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 602233 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15645 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 216255 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6012 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63410 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 133827 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197237 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 28083451 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3480678 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 196129 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 191226 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3996466 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 295299 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32798710 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 54858 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3489643 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2214871 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 602209 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15595 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 231865 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6154 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 62873 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134195 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197068 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30195469 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3482644 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 197641 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1378649 # number of nop insts executed -system.cpu2.iew.exec_refs 5608668 # number of memory reference insts executed -system.cpu2.iew.exec_branches 5940571 # Number of branches executed -system.cpu2.iew.exec_stores 2127990 # Number of stores executed -system.cpu2.iew.exec_rate 0.958180 # Inst execution rate -system.cpu2.iew.wb_sent 27865492 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27824643 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15848860 # num instructions producing a value -system.cpu2.iew.wb_consumers 19489990 # num instructions consuming a value +system.cpu2.iew.exec_nop 1379854 # number of nop insts executed +system.cpu2.iew.exec_refs 5611883 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6643679 # Number of branches executed +system.cpu2.iew.exec_stores 2129239 # Number of stores executed +system.cpu2.iew.exec_rate 1.006060 # Inst execution rate +system.cpu2.iew.wb_sent 29976342 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29934655 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17254819 # num instructions producing a value +system.cpu2.iew.wb_consumers 20895222 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.949349 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.813179 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.997370 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.825778 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2662629 # The number of squashed insts skipped by commit +system.cpu2.commit.commitSquashedInsts 2658447 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180156 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27293607 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.025131 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.859726 # Number of insts commited each cycle +system.cpu2.commit.branchMispredicts 180111 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28004103 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.074728 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.862098 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18211809 66.73% 66.73% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2232896 8.18% 74.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1177901 4.32% 79.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 3741262 13.71% 92.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 541174 1.98% 94.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200137 0.73% 95.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164418 0.60% 96.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 176928 0.65% 96.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 847082 3.10% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18216020 65.05% 65.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2235913 7.98% 73.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1176646 4.20% 77.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4445185 15.87% 93.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 540129 1.93% 95.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 200547 0.72% 95.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 166033 0.59% 96.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 176455 0.63% 96.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 847175 3.03% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27293607 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 27979525 # Number of instructions committed -system.cpu2.commit.committedOps 27979525 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28004103 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30096794 # Number of instructions committed +system.cpu2.commit.committedOps 30096794 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5085574 # Number of memory references committed -system.cpu2.commit.loads 3052863 # Number of loads committed -system.cpu2.commit.membars 67982 # Number of memory barriers committed -system.cpu2.commit.branches 5768887 # Number of branches committed -system.cpu2.commit.fp_insts 115191 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 26471742 # Number of committed integer instructions. -system.cpu2.commit.function_calls 239400 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1215445 4.34% 4.34% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 21266434 76.01% 80.35% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20635 0.07% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20039 0.07% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3120845 11.15% 91.65% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2034343 7.27% 98.93% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 300564 1.07% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5086249 # Number of memory references committed +system.cpu2.commit.loads 3053005 # Number of loads committed +system.cpu2.commit.membars 67981 # Number of memory barriers committed +system.cpu2.commit.branches 6474041 # Number of branches committed +system.cpu2.commit.fp_insts 115125 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28589001 # Number of committed integer instructions. +system.cpu2.commit.function_calls 239427 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1215466 4.04% 4.04% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 23382957 77.69% 81.73% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20643 0.07% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20037 0.07% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3120986 10.37% 92.24% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2034876 6.76% 99.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 300609 1.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 27979525 # Class of committed instruction -system.cpu2.commit.bw_lim_events 847082 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 30096794 # Class of committed instruction +system.cpu2.commit.bw_lim_events 847175 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 57015033 # The number of ROB reads -system.cpu2.rob.rob_writes 61749251 # The number of ROB writes -system.cpu2.timesIdled 174924 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1549032 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1748451761 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 26766520 # Number of Instructions Simulated -system.cpu2.committedOps 26766520 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.094994 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.094994 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.913247 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.913247 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 36812900 # number of integer regfile reads -system.cpu2.int_regfile_writes 19756149 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70792 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70904 # number of floating regfile writes -system.cpu2.misc_regfile_reads 3635366 # number of misc regfile reads -system.cpu2.misc_regfile_writes 270473 # number of misc regfile writes +system.cpu2.rob.rob_reads 59838509 # The number of ROB reads +system.cpu2.rob.rob_writes 65974697 # The number of ROB writes +system.cpu2.timesIdled 175016 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1543677 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747747743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 28883768 # Number of Instructions Simulated +system.cpu2.committedOps 28883768 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.039116 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.039116 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.962357 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.962357 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39632695 # number of integer regfile reads +system.cpu2.int_regfile_writes 21162382 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70702 # number of floating regfile reads +system.cpu2.fp_regfile_writes 70843 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4340126 # number of misc regfile reads +system.cpu2.misc_regfile_writes 270474 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1389,25 +1412,25 @@ system.iobus.reqLayer1.occupancy 102000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5523000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5529000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 169052512 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 166547212 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9350000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9356000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17532500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17276500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262652 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.262651 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693890023000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262652 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1693890143000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.262651 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1425,8 +1448,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5715176550 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5715176550 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5628764250 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 5628764250 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles @@ -1449,17 +1472,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 137542.754861 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 137542.754861 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 87544 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 86158 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9998 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9840 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756151 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.755894 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1467,234 +1490,234 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17024 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4816616550 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4816616550 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4743516250 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4743516250 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.409704 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.409704 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278739.383681 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278739.383681 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278636.997768 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278636.997768 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337552 # number of replacements -system.l2c.tags.tagsinuse 65418.667862 # Cycle average of tags in use -system.l2c.tags.total_refs 2487006 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402715 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.175598 # Average number of references to valid blocks. +system.l2c.tags.replacements 337565 # number of replacements +system.l2c.tags.tagsinuse 65420.967844 # Cycle average of tags in use +system.l2c.tags.total_refs 2486640 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402728 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.174490 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54698.574366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2340.440822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2723.231256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 572.328176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 607.228358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2274.234670 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2202.630214 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.834634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041553 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008733 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034702 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033609 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54725.451973 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2331.479005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2701.186077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 572.371097 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 609.192683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2285.385373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2195.901635 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.035576 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041217 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008734 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009296 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034872 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.033507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998245 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1015 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5951 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2685 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55344 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5954 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2697 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55331 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26261755 # Number of tag accesses -system.l2c.tags.data_accesses 26261755 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 506757 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 483132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 121571 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 80695 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 322132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 253945 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1768232 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835902 # number of Writeback hits -system.l2c.Writeback_hits::total 835902 # number of Writeback hits +system.l2c.tags.tag_accesses 26259538 # Number of tag accesses +system.l2c.tags.data_accesses 26259538 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 506712 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 484023 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 121893 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 79858 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 321963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 253653 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1768102 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835667 # number of Writeback hits +system.l2c.Writeback_hits::total 835667 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 90966 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25233 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 70678 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186877 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 506757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 574098 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 121571 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 105928 # 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number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4575 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 17928 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287609 # number of ReadReq misses +system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 90939 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 25234 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 70756 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186929 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 506712 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 574962 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 121893 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 105092 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 302243500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 395601500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 697845000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 535699000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 715862500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1251561500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173792 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.066007 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1804,91 +1827,91 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # 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Transaction distribution -system.membus.trans_dist::UpgradeResp 149 # Transaction distribution -system.membus.trans_dist::ReadExReq 115717 # Transaction distribution -system.membus.trans_dist::ReadExResp 115717 # Transaction distribution +system.membus.trans_dist::UpgradeResp 165 # Transaction distribution +system.membus.trans_dist::ReadExReq 115724 # Transaction distribution +system.membus.trans_dist::ReadExResp 115724 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882304 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916226 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1041133 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30677576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30678792 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36001224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36002440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 140 # Total snoops (count) -system.membus.snoop_fanout::samples 562099 # Request fanout histogram +system.membus.snoop_fanout::samples 562134 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562099 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 562134 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562099 # Request fanout histogram -system.membus.reqLayer0.occupancy 11803000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 562134 # Request fanout histogram +system.membus.reqLayer0.occupancy 11832500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 659094000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 654960000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 769927201 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 770434435 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17910500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17654500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063113 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2063092 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2063004 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2062983 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835902 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302718 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302718 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835667 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17024 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 48 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 57 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302779 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302779 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1929756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5587153 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61750976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142744520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204495496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41919 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3236289 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012893 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112812 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930013 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3656818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5586831 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61758720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142717704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204476424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41934 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3236018 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012894 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112817 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3194564 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3194293 98.71% 98.71% # Request fanout histogram system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3236289 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2206148499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3236018 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2201638999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2029921963 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2030846564 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2294082992 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2289452792 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |