diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt | 2033 |
1 files changed, 0 insertions, 2033 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt deleted file mode 100644 index 848d1d5ab..000000000 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ /dev/null @@ -1,2033 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.842573 # Number of seconds simulated -sim_ticks 1842573194000 # Number of ticks simulated -final_tick 1842573194000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 206946 # Simulator instruction rate (inst/s) -host_op_rate 206946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5715573944 # Simulator tick rate (ticks/s) -host_mem_usage 339016 # Number of bytes of host memory used -host_seconds 322.38 # Real time elapsed on the host -sim_insts 66714903 # Number of instructions simulated -sim_ops 66714903 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 469248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20132864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2123008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 298368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2617024 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25791680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 469248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 298368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 917824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7488960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7488960 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314576 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 40891 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402995 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117015 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 254670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10926493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1152197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 161930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1420309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13997642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 254670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 161930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4064403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4064403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4064403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 254670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10926493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1152197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 161930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1420309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18062045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81087 # Number of read requests accepted -system.physmem.writeReqs 46731 # Number of write requests accepted -system.physmem.readBursts 81087 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 46731 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5188416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue -system.physmem.bytesWritten 2989056 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5189568 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2990784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4742 # Per bank write bursts -system.physmem.perBankRdBursts::1 4753 # Per bank write bursts -system.physmem.perBankRdBursts::2 4837 # Per bank write bursts -system.physmem.perBankRdBursts::3 5252 # Per bank write bursts -system.physmem.perBankRdBursts::4 5163 # Per bank write bursts -system.physmem.perBankRdBursts::5 5213 # Per bank write bursts -system.physmem.perBankRdBursts::6 5141 # Per bank write bursts -system.physmem.perBankRdBursts::7 5015 # Per bank write bursts -system.physmem.perBankRdBursts::8 5238 # Per bank write bursts -system.physmem.perBankRdBursts::9 4880 # Per bank write bursts -system.physmem.perBankRdBursts::10 5475 # Per bank write bursts -system.physmem.perBankRdBursts::11 5008 # Per bank write bursts -system.physmem.perBankRdBursts::12 4911 # Per bank write bursts -system.physmem.perBankRdBursts::13 4972 # Per bank write bursts -system.physmem.perBankRdBursts::14 5564 # Per bank write bursts -system.physmem.perBankRdBursts::15 4905 # Per bank write bursts -system.physmem.perBankWrBursts::0 2655 # Per bank write bursts -system.physmem.perBankWrBursts::1 2725 # Per bank write bursts -system.physmem.perBankWrBursts::2 2864 # Per bank write bursts -system.physmem.perBankWrBursts::3 3189 # Per bank write bursts -system.physmem.perBankWrBursts::4 3009 # Per bank write bursts -system.physmem.perBankWrBursts::5 2838 # Per bank write bursts -system.physmem.perBankWrBursts::6 3113 # Per bank write bursts -system.physmem.perBankWrBursts::7 2705 # Per bank write bursts -system.physmem.perBankWrBursts::8 3288 # Per bank write bursts -system.physmem.perBankWrBursts::9 2746 # Per bank write bursts -system.physmem.perBankWrBursts::10 3262 # Per bank write bursts -system.physmem.perBankWrBursts::11 2782 # Per bank write bursts -system.physmem.perBankWrBursts::12 2699 # Per bank write bursts -system.physmem.perBankWrBursts::13 2735 # Per bank write bursts -system.physmem.perBankWrBursts::14 3348 # Per bank write bursts -system.physmem.perBankWrBursts::15 2746 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 1841561317000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81087 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 46731 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 63494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.808047 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.054900 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 378.494212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7105 33.09% 33.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4792 22.32% 55.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1974 9.19% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1058 4.93% 69.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 851 3.96% 73.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 468 2.18% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 396 1.84% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 380 1.77% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4450 20.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21474 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2032 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 39.890256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 985.167686 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2030 99.90% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2032 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2032 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.984252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.590209 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.991562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.67% 1.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.34% 2.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 3 0.15% 2.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.10% 2.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1678 82.58% 84.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 43 2.12% 86.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 12 0.59% 87.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 18 0.89% 88.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 100 4.92% 93.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.10% 93.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 5 0.25% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.15% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.05% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.10% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.05% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.10% 94.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 2 0.10% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.05% 94.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.05% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.34% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.10% 94.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.10% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 82 4.04% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.05% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.10% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.10% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.05% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.10% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.05% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.10% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.05% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.05% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 7 0.34% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2032 # Writes before turning the bus around for reads -system.physmem.totQLat 878117500 # Total ticks spent queuing -system.physmem.totMemAccLat 2398161250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 405345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10831.73 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29581.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.72 # Average write queue length when enqueuing -system.physmem.readRowHits 69338 # Number of row buffer hits during reads -system.physmem.writeRowHits 36961 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.09 # Row buffer hit rate for writes -system.physmem.avgGap 14407683.71 # Average gap between requests -system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 80173800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 43646625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 312904800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 149675040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89124122880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35767572390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 797968033500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 923446129035 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.080170 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309854007000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45564480000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9260985250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 82169640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 44677875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 319433400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 152966880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89124122880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35452017540 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 802163554500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 927338942715 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.741345 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1310300112750 # Time in different power states -system.physmem_1.memoryStateTime::REF 45564480000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8843530000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4806164 # DTB read hits -system.cpu0.dtb.read_misses 6050 # DTB read misses -system.cpu0.dtb.read_acv 122 # DTB read access violations -system.cpu0.dtb.read_accesses 427464 # DTB read accesses -system.cpu0.dtb.write_hits 3411517 # DTB write hits -system.cpu0.dtb.write_misses 679 # DTB write misses -system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 163616 # DTB write accesses -system.cpu0.dtb.data_hits 8217681 # DTB hits -system.cpu0.dtb.data_misses 6729 # DTB misses -system.cpu0.dtb.data_acv 206 # DTB access violations -system.cpu0.dtb.data_accesses 591080 # DTB accesses -system.cpu0.itb.fetch_hits 2722802 # ITB hits -system.cpu0.itb.fetch_misses 3018 # ITB misses -system.cpu0.itb.fetch_acv 101 # ITB acv -system.cpu0.itb.fetch_accesses 2725820 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 6514 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 3257 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 552798033.019036 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 1352688826.519808 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 3257 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 142000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 3905515000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 3257 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 42110000457 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1800463193543 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 928783152 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6426 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74798 40.97% 40.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105692 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73431 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73431 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148944 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819731049500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39465000 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 370305500 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22431640000 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842572460000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694764 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815810 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed -system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed -system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed -system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed -system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed -system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed -system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed -system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed -system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed -system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed -system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed -system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed -system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed -system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed -system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed -system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed -system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed -system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed -system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed -system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 326 # number of syscalls executed -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed -system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed -system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192227 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1907 -system.cpu0.kern.mode_good::user 1738 -system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29732108000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2585852000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810254498000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4176 # number of times the context was actually changed -system.cpu0.committedInsts 30003730 # Number of instructions committed -system.cpu0.committedOps 30003730 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 27925731 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 163756 # Number of float alu accesses -system.cpu0.num_func_calls 796110 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3567009 # number of instructions that are conditional controls -system.cpu0.num_int_insts 27925731 # number of integer instructions -system.cpu0.num_fp_insts 163756 # number of float instructions -system.cpu0.num_int_register_reads 38434691 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20585928 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84641 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86208 # number of times the floating registers were written -system.cpu0.num_mem_refs 8247251 # number of memory refs -system.cpu0.num_load_insts 4827160 # Number of load instructions -system.cpu0.num_store_insts 3420091 # Number of store instructions -system.cpu0.num_idle_cycles 907147772.055444 # Number of idle cycles -system.cpu0.num_busy_cycles 21635379.944556 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023294 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976706 # Percentage of idle cycles -system.cpu0.Branches 4619076 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1571431 5.24% 5.24% # Class of executed instruction -system.cpu0.op_class::IntAlu 19496987 64.97% 70.20% # Class of executed instruction -system.cpu0.op_class::IntMult 31839 0.11% 70.31% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.31% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12846 0.04% 70.35% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1596 0.01% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::MemRead 4957504 16.52% 86.88% # Class of executed instruction -system.cpu0.op_class::MemWrite 3423190 11.41% 98.28% # Class of executed instruction -system.cpu0.op_class::IprAccess 515272 1.72% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30010665 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1394329 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13513290 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1394841 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.688050 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.899506 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 77.334042 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.764270 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503710 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.151043 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345243 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 64401814 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 64401814 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 3982326 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1071245 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2765188 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7818759 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3123296 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 821204 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357761 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5302261 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113724 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19478 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 59657 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 192859 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122531 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21526 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55288 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199345 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7105622 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1892449 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 4122949 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13121020 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7105622 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1892449 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 4122949 # number of overall hits -system.cpu0.dcache.overall_hits::total 13121020 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 711284 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 95061 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 562348 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1368693 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 164279 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43166 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 643208 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 850653 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9354 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2180 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7624 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19158 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 15 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 875563 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 138227 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1205556 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2219346 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 875563 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 138227 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1205556 # number of overall misses -system.cpu0.dcache.overall_misses::total 2219346 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2249916500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8280122000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10530038500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1722737000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19403438202 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21126175202 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28838500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 118651000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 147489500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 209000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3972653500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27683560202 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31656213702 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3972653500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27683560202 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31656213702 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4693610 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1166306 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3327536 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9187452 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3287575 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 864370 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2000969 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6152914 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123078 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21658 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 67281 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 212017 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122531 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21526 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55303 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199360 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 7981185 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2030676 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5328505 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15340366 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 7981185 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2030676 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5328505 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15340366 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151543 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081506 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.168998 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.148974 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049970 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.049939 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.321448 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.138252 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076001 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100656 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.113316 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090361 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000271 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000075 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109703 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068069 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.226247 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.144674 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109703 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068069 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.226247 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.144674 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23668.134145 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14724.195694 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 7693.499200 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39909.581615 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30166.661798 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24835.244456 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13228.669725 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15562.827912 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7698.585447 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13933.333333 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13933.333333 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28740.068872 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22963.313361 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14263.757748 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28740.068872 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22963.313361 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14263.757748 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1005696 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2108 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 59599 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.874377 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 117.111111 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 837399 # number of writebacks -system.cpu0.dcache.writebacks::total 837399 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 293239 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 293239 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548303 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 548303 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2076 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 2076 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 841542 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 841542 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 841542 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 841542 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 95061 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 269109 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 364170 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43166 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 94905 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 138071 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2180 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5548 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7728 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 15 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 138227 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 364014 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 502241 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 138227 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 364014 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 502241 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1131 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1713 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2844 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1429 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2015 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3444 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2560 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3728 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6288 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2154855500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4439209000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6594064500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1679571000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3050724099 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4730295099 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26658500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69598500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96257000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 194000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3834426500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7489933099 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11324359599 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3834426500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7489933099 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11324359599 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248626500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 373633000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 622259500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 248626500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 373633000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 622259500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081506 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.080873 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039638 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.049939 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047430 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022440 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100656 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.082460 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036450 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000271 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000075 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068069 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.068314 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032740 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068069 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.068314 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032740 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22668.134145 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16495.951455 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18107.105198 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38909.581615 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32145.030283 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34259.874260 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12228.669725 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12544.790916 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12455.615942 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 12933.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12933.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27740.068872 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20575.947900 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22547.660583 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27740.068872 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20575.947900 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22547.660583 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219828.912467 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 218116.170461 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218797.292546 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97119.726562 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 100223.444206 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98959.844148 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 970146 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.204815 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39666884 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 970657 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 40.866015 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10200765500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.084411 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 64.947265 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 183.173139 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.513837 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.126850 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.357760 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998447 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 41630359 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 41630359 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 29500548 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7433858 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2732478 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39666884 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29500548 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7433858 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2732478 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39666884 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29500548 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7433858 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2732478 # number of overall hits -system.cpu0.icache.overall_hits::total 39666884 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 510117 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 127222 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 355287 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 992626 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 510117 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 127222 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 355287 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 992626 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 510117 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 127222 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 355287 # number of overall misses -system.cpu0.icache.overall_misses::total 992626 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1824371000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4938070984 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6762441984 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1824371000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4938070984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6762441984 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1824371000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4938070984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6762441984 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30010665 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7561080 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3087765 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40659510 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30010665 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7561080 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3087765 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40659510 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30010665 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7561080 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3087765 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40659510 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016998 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016826 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115063 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.024413 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016998 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016826 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115063 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.024413 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016998 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016826 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115063 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.024413 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14340.059109 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13898.822597 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6812.678677 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14340.059109 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13898.822597 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6812.678677 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14340.059109 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13898.822597 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6812.678677 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4393 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 224 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.611607 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 970146 # number of writebacks -system.cpu0.icache.writebacks::total 970146 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 21777 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 21777 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 21777 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 21777 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 21777 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 21777 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 127222 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 333510 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 460732 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 127222 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 333510 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 460732 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 127222 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 333510 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 460732 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1697149000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4385581487 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6082730487 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1697149000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4385581487 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6082730487 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1697149000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4385581487 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6082730487 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13202.318239 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13202.318239 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13202.318239 # average overall mshr miss latency -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1185765 # DTB read hits -system.cpu1.dtb.read_misses 1350 # DTB read misses -system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142577 # DTB read accesses -system.cpu1.dtb.write_hits 886140 # DTB write hits -system.cpu1.dtb.write_misses 164 # DTB write misses -system.cpu1.dtb.write_acv 19 # DTB write access violations -system.cpu1.dtb.write_accesses 58302 # DTB write accesses -system.cpu1.dtb.data_hits 2071905 # DTB hits -system.cpu1.dtb.data_misses 1514 # DTB misses -system.cpu1.dtb.data_acv 53 # DTB access violations -system.cpu1.dtb.data_accesses 200879 # DTB accesses -system.cpu1.itb.fetch_hits 858318 # ITB hits -system.cpu1.itb.fetch_misses 678 # ITB misses -system.cpu1.itb.fetch_acv 29 # ITB acv -system.cpu1.itb.fetch_accesses 858996 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 2295 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1148 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1552918826.219512 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 1902969233.500840 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1148 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 123500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 6633070500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1148 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 59822381500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1782750812500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 953371043 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed -system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches -system.cpu1.kern.mode_switch::user 0 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 0 -system.cpu1.kern.mode_good::user 0 -system.cpu1.kern.mode_good::idle 0 -system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode -system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7559512 # Number of instructions committed -system.cpu1.committedOps 7559512 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7024268 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44783 # Number of float alu accesses -system.cpu1.num_func_calls 206891 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 914000 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7024268 # number of integer instructions -system.cpu1.num_fp_insts 44783 # number of float instructions -system.cpu1.num_int_register_reads 9773567 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5124259 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24150 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24568 # number of times the floating registers were written -system.cpu1.num_mem_refs 2078876 # number of memory refs -system.cpu1.num_load_insts 1190479 # Number of load instructions -system.cpu1.num_store_insts 888397 # Number of store instructions -system.cpu1.num_idle_cycles 923345266.952757 # Number of idle cycles -system.cpu1.num_busy_cycles 30025776.047243 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031494 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968506 # Percentage of idle cycles -system.cpu1.Branches 1187005 # Number of branches fetched -system.cpu1.op_class::No_OpClass 406253 5.37% 5.37% # Class of executed instruction -system.cpu1.op_class::IntAlu 4898849 64.79% 70.16% # Class of executed instruction -system.cpu1.op_class::IntMult 8443 0.11% 70.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5163 0.07% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatDiv 816 0.01% 70.35% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::MemRead 1219110 16.12% 86.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 889613 11.77% 98.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 132832 1.76% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7561079 # Class of executed instruction -system.cpu2.branchPred.lookups 10182069 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9237326 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 193435 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7648921 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5487936 # Number of BTB hits -system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.747845 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 365631 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 14350 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1844704 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 187088 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 1657616 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 85690 # Number of mispredicted indirect branches. -system.cpu2.dtb.fetch_hits 0 # ITB hits -system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.fetch_acv 0 # ITB acv -system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3799673 # DTB read hits -system.cpu2.dtb.read_misses 14845 # DTB read misses -system.cpu2.dtb.read_acv 160 # DTB read access violations -system.cpu2.dtb.read_accesses 231351 # DTB read accesses -system.cpu2.dtb.write_hits 2187859 # DTB write hits -system.cpu2.dtb.write_misses 3782 # DTB write misses -system.cpu2.dtb.write_acv 156 # DTB write access violations -system.cpu2.dtb.write_accesses 85049 # DTB write accesses -system.cpu2.dtb.data_hits 5987532 # DTB hits -system.cpu2.dtb.data_misses 18627 # DTB misses -system.cpu2.dtb.data_acv 316 # DTB access violations -system.cpu2.dtb.data_accesses 316400 # DTB accesses -system.cpu2.itb.fetch_hits 533981 # ITB hits -system.cpu2.itb.fetch_misses 2772 # ITB misses -system.cpu2.itb.fetch_acv 207 # ITB acv -system.cpu2.itb.fetch_accesses 536753 # ITB accesses -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.read_acv 0 # DTB read access violations -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.write_acv 0 # DTB write access violations -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.data_hits 0 # DTB hits -system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.data_acv 0 # DTB access violations -system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numPwrStateTransitions 3110 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 1555 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 290577901.929260 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 445615554.555058 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 1555 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::min_value 35500 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 1555 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 1390724556500 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 451848637500 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 30294700 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9331724 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 40046932 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10182069 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6040655 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18950980 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 546368 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 10813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1967 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 55421 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 90541 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 526 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3087771 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 132437 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 28714918 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.394639 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.444168 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 19847963 69.12% 69.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 338255 1.18% 70.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516605 1.80% 72.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4056347 14.13% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 883774 3.08% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 213492 0.74% 90.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 260077 0.91% 90.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 443832 1.55% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2154573 7.50% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 28714918 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.336101 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.321912 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7553623 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 12980509 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7101757 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 570685 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 262482 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 224592 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 11278 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36245198 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 35745 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 262482 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7856240 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4908054 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5914164 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7349808 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2178317 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35245227 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 60989 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 402200 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 73644 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1098810 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23726835 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 43551141 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43490937 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56291 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20541823 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 3185012 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 542390 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 75158 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3906024 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3910206 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2331407 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 534571 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 330323 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32351146 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 700049 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 31671278 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 26658 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 3899534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1737148 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 505950 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 28714918 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.102956 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.635713 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17343310 60.40% 60.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2798035 9.74% 70.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1407296 4.90% 75.04% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4809954 16.75% 91.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1078748 3.76% 95.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 629909 2.19% 97.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 420699 1.47% 99.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 175678 0.61% 99.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 51289 0.18% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 28714918 # Number of insts issued each cycle -system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 83963 19.65% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 211212 49.43% 69.08% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 132122 30.92% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2449 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 25130857 79.35% 79.36% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21000 0.07% 79.42% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 79.42% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20519 0.06% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3970834 12.54% 92.03% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2221095 7.01% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 303300 0.96% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 31671278 # Type of FU issued -system.cpu2.iq.rate 1.045440 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 427297 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013492 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92249666 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 36829058 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 30874313 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 261763 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 128201 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 120289 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 31956268 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 139858 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 223032 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 835467 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1428 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6657 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 271687 # Number of stores squashed -system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4727 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 223048 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 262482 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4297358 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 190047 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34535423 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 71039 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3910206 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2331407 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 624892 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12907 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 136174 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6657 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 75410 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 204692 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 280102 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 31389945 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3824957 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 281333 # Number of squashed instructions skipped in execute -system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1484228 # number of nop insts executed -system.cpu2.iew.exec_refs 6022953 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6845679 # Number of branches executed -system.cpu2.iew.exec_stores 2197996 # Number of stores executed -system.cpu2.iew.exec_rate 1.036153 # Inst execution rate -system.cpu2.iew.wb_sent 31070665 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30994602 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17781356 # num instructions producing a value -system.cpu2.iew.wb_consumers 21603769 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.023103 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.823067 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 4096171 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194099 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 251035 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28008857 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.084369 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.866736 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18128303 64.72% 64.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2274965 8.12% 72.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1151627 4.11% 76.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4494039 16.05% 93.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 560514 2.00% 95.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 204888 0.73% 95.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 167574 0.60% 96.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 175902 0.63% 96.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 851045 3.04% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28008857 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30371950 # Number of instructions committed -system.cpu2.commit.committedOps 30371950 # Number of ops (including micro ops) committed -system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5134459 # Number of memory references committed -system.cpu2.commit.loads 3074739 # Number of loads committed -system.cpu2.commit.membars 68371 # Number of memory barriers committed -system.cpu2.commit.branches 6541536 # Number of branches committed -system.cpu2.commit.fp_insts 115785 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28855389 # Number of committed integer instructions. -system.cpu2.commit.function_calls 240551 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1222737 4.03% 4.03% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 23599707 77.70% 81.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20441 0.07% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20074 0.07% 81.86% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.86% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.86% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.86% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1224 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3143110 10.35% 92.21% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2061357 6.79% 99.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 303300 1.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 30371950 # Class of committed instruction -system.cpu2.commit.bw_lim_events 851045 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 61550290 # The number of ROB reads -system.cpu2.rob.rob_writes 69643370 # The number of ROB writes -system.cpu2.timesIdled 166665 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1579782 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747467532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29151661 # Number of Instructions Simulated -system.cpu2.committedOps 29151661 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.039210 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.039210 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.962269 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.962269 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 41082611 # number of integer regfile reads -system.cpu2.int_regfile_writes 21995152 # number of integer regfile writes -system.cpu2.fp_regfile_reads 71087 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74140 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4380582 # number of misc regfile reads -system.cpu2.misc_regfile_writes 272883 # number of misc regfile writes -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7317 # Transaction distribution -system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51363 # Transaction distribution -system.iobus.trans_dist::WriteResp 51363 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2361000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 133500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 56000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5888500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2490000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 89817179 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9132000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17450000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262350 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693898501000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262350 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078897 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078897 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9479963 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9479963 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2017910216 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2017910216 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 2027390179 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 2027390179 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 2027390179 # number of overall miss cycles -system.iocache.overall_miss_latency::total 2027390179 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54797.473988 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54797.473988 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48563.491914 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 48563.491914 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 48589.339221 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 48589.339221 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 48589.339221 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 48589.339221 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17264 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 17264 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17333 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17333 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17333 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 17333 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6029963 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6029963 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1153715348 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1153715348 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 1159745311 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1159745311 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 1159745311 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1159745311 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415479 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.415479 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415410 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.415410 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415410 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.415410 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87390.768116 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 87390.768116 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66827.812095 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66827.812095 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66909.670051 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66909.670051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66909.670051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66909.670051 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 337759 # number of replacements -system.l2c.tags.tagsinuse 65519.967313 # Cycle average of tags in use -system.l2c.tags.total_refs 4324806 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 403281 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.724051 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 245.396014 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2334.791555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 32190.823829 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 573.204668 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8853.828657 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2257.129240 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 19064.793350 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.003744 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035626 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.491193 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008746 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.135099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034441 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.290906 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.999755 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 698 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 59064 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38232018 # Number of tag accesses -system.l2c.tags.data_accesses 38232018 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1842573194000 # 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number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 3021262500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5725350000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 234482500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 352216500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 586699000 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 234482500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 352216500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 586699000 # number of overall MSHR uncacheable cycles -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.294118 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.172414 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407099 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.252377 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.137371 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007220 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.160920 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061975 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.029900 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.236601 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.110912 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034332 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.236601 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.110912 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034332 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50500 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66582.176189 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79447.540778 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 74005.704932 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73239.834499 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 65233.096881 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 65633.844617 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 65441.862601 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65946.703793 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73712.701588 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 70495.345745 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65946.703793 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73712.701588 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 70495.345745 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207323.165340 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205613.835377 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206293.600563 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91594.726562 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94478.674893 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 93304.548346 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 823847 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 379580 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 295118 # Transaction distribution -system.membus.trans_dist::WriteReq 9811 # Transaction distribution -system.membus.trans_dist::WriteResp 9811 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117015 # Transaction distribution -system.membus.trans_dist::CleanEvict 261705 # Transaction distribution -system.membus.trans_dist::UpgradeReq 133 # Transaction distribution -system.membus.trans_dist::UpgradeResp 97 # Transaction distribution -system.membus.trans_dist::ReadExReq 115450 # Transaction distribution -system.membus.trans_dist::ReadExResp 115450 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287989 # Transaction distribution -system.membus.trans_dist::BadAddressError 15 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 24288 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 30 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177609 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 107817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 107817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1285426 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30634176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30679752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33344136 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 152 # Total snoops (count) -system.membus.snoopTraffic 9536 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 742383 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001299 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036012 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 741419 99.87% 99.87% # Request fanout histogram -system.membus.snoop_fanout::1 964 0.13% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 742383 # Request fanout histogram -system.membus.reqLayer0.occupancy 10929000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 389109129 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 434990750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 365537 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4730225 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2364683 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1647 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1041 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2070475 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 866906 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 970146 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 608698 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302414 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302414 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 970849 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1092499 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 15 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 40 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2911790 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4218095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7129885 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124220224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142912456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 267132680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 338659 # Total snoops (count) -system.toL2Bus.snoopTraffic 4850432 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4115169 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.000990 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.031456 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4111093 99.90% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4076 0.10% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4115169 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1824758000 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 98963 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 691417859 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 769604277 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states -system.cpu2.kern.inst.arm 0 # number of arm instructions executed -system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed -system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches -system.cpu2.kern.mode_switch::user 0 # number of protection mode switches -system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu2.kern.mode_good::kernel 0 -system.cpu2.kern.mode_good::user 0 -system.cpu2.kern.mode_good::idle 0 -system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches -system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches -system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches -system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode -system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode -system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode -system.cpu2.kern.swap_context 0 # number of times the context was actually changed - ----------- End Simulation Statistics ---------- |