diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt | 2613 |
1 files changed, 1417 insertions, 1196 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 3510035fa..936d08062 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841721 # Number of seconds simulated -sim_ticks 1841721066000 # Number of ticks simulated -final_tick 1841721066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842698 # Number of seconds simulated +sim_ticks 1842697801000 # Number of ticks simulated +final_tick 1842697801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 314597 # Simulator instruction rate (inst/s) -host_op_rate 314597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8282501609 # Simulator tick rate (ticks/s) -host_mem_usage 307380 # Number of bytes of host memory used -host_seconds 222.36 # Real time elapsed on the host -sim_insts 69954713 # Number of instructions simulated -sim_ops 69954713 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19360768 # Number of bytes read from this memory +host_inst_rate 215096 # Simulator instruction rate (inst/s) +host_op_rate 215096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5452418287 # Simulator tick rate (ticks/s) +host_mem_usage 309280 # Number of bytes of host memory used +host_seconds 337.96 # Real time elapsed on the host +sim_insts 72693799 # Number of instructions simulated +sim_ops 72693799 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 487424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20019264 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2811776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2696640 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7466048 # Number of bytes written to this memory -system.physmem.bytes_written::total 7466048 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302512 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 147904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2316480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 282624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2529216 # Number of bytes read from this memory +system.physmem.bytes_read::total 28435264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 487424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 282624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 917952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory +system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 312801 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42135 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444383 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116657 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116657 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10512324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1526711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1464196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15442356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053843 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053843 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10512324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1526711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1464196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19496199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109805 # Total number of read requests seen -system.physmem.writeReqs 45348 # Total number of write requests seen -system.physmem.cpureqs 155202 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7027520 # Total number of bytes read from memory -system.physmem.bytesWritten 2902272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7027520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2902272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6891 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6837 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6841 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2758 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2749 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2776 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3031 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3192 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2803 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis +system.physmem.num_reads::cpu1.inst 2311 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 36195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39519 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444301 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 264517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10864106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1257113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 153375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1372561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15431322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 264517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 153375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498157 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 264517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10864106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1257113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 153375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1372561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19479509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 99716 # Total number of read requests seen +system.physmem.writeReqs 44920 # Total number of write requests seen +system.physmem.cpureqs 144680 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6381824 # Total number of bytes read from memory +system.physmem.bytesWritten 2874880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6381824 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2874880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6258 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6396 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6492 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6146 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2882 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2846 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2624 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3004 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3022 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2472 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2760 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840708761500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1841685476500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109805 # Categorize read packet sizes +system.physmem.readPktSize::6 99716 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 45348 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 80824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44920 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 68031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,242 +148,369 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.totQLat 2404806500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4407346500 # Sum of mem lat for all requests -system.physmem.totBusLat 549000000 # Total cycles spent in databus access -system.physmem.totBankLat 1453540000 # Total cycles spent in bank access -system.physmem.avgQLat 21901.70 # Average queueing delay per request -system.physmem.avgBankLat 13238.07 # Average bank access latency per request +system.physmem.wrQLenPdf::0 1388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 15781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 586.280717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.240853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1929.214074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 6626 41.99% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2550 16.16% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1431 9.07% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 896 5.68% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 638 4.04% 76.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 562 3.56% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 391 2.48% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 301 1.91% 84.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 260 1.65% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 205 1.30% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 214 1.36% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 213 1.35% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 77 0.49% 91.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 70 0.44% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 80 0.51% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 90 0.57% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 36 0.23% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 39 0.25% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 57 0.36% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 48 0.30% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 35 0.22% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 177 1.12% 95.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.55% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 34 0.22% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 7 0.04% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 18 0.11% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 14 0.09% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 8 0.05% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 6 0.04% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 4 0.03% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 1 0.01% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.01% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 2 0.01% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.01% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 1 0.01% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.01% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 1 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.01% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.01% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 384 2.43% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.05% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 1 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 15781 # Bytes accessed per row activation +system.physmem.totQLat 1934459750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3605914750 # Sum of mem lat for all requests +system.physmem.totBusLat 498525000 # Total cycles spent in databus access +system.physmem.totBankLat 1172930000 # Total cycles spent in bank access +system.physmem.avgQLat 19401.83 # Average queueing delay per request +system.physmem.avgBankLat 11764.00 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40139.77 # Average memory access latency -system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 36165.84 # Average memory access latency +system.physmem.avgRdBW 3.46 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.46 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.17 # Average write queue length over time -system.physmem.readRowHits 99784 # Number of row buffer hits during reads -system.physmem.writeRowHits 34161 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.33 # Row buffer hit rate for writes -system.physmem.avgGap 11863829.65 # Average gap between requests -system.l2c.replacements 337457 # number of replacements -system.l2c.tagsinuse 65420.293999 # Cycle average of tags in use -system.l2c.total_refs 2475568 # Total number of references to valid blocks. -system.l2c.sampled_refs 402619 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.148662 # Average number of references to valid blocks. +system.physmem.readRowHits 93388 # Number of row buffer hits during reads +system.physmem.writeRowHits 35434 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.88 # Row buffer hit rate for writes +system.physmem.avgGap 12733243.98 # Average gap between requests +system.membus.throughput 19523449 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46002 # Transaction distribution +system.membus.trans_dist::ReadResp 45972 # Transaction distribution +system.membus.trans_dist::WriteReq 3749 # Transaction distribution +system.membus.trans_dist::WriteResp 3749 # Transaction distribution +system.membus.trans_dist::Writeback 44920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 46 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47 # Transaction distribution +system.membus.trans_dist::ReadExReq 56809 # Transaction distribution +system.membus.trans_dist::ReadExResp 56809 # Transaction distribution +system.membus.trans_dist::BadAddressError 30 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 192737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 206111 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 51863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 244600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 257974 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7047808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 7063555 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2208896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 9256704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9272451 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35965768 # Total data (bytes) +system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12475000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 520545500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 35000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 777595953 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 156419750 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.l2c.replacements 337378 # number of replacements +system.l2c.tagsinuse 65422.722236 # Cycle average of tags in use +system.l2c.total_refs 2472063 # Total number of references to valid blocks. +system.l2c.sampled_refs 402541 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.141146 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54855.924450 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2280.990805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2631.435167 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 619.089376 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 660.267485 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2247.126162 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2125.460555 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.837035 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.034805 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040153 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.009447 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.010075 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.034288 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032432 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998234 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 516823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491434 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83916 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 295941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 241655 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1756609 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836144 # number of Writeback hits -system.l2c.Writeback_hits::total 836144 # number of Writeback hits +system.l2c.occ_blocks::writebacks 54907.432737 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2460.754948 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2679.156770 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 579.419963 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 590.394247 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2099.377178 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 2106.186392 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.837821 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.037548 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.040881 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.008841 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.009009 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.032034 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.032138 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998272 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 520270 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493307 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124051 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83977 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 292923 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239241 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1753769 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835411 # number of Writeback hits +system.l2c.Writeback_hits::total 835411 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92196 # 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average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -494,14 +629,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255737 # Cycle average of tags in use +system.iocache.tagsinuse 1.254871 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693878100000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255737 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078484 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078484 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1694871315000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.254871 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078429 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078429 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -510,14 +645,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4330975325 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4330975325 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4340153323 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4340153323 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4340153323 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4340153323 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9512963 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9512963 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4344125507 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4344125507 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4353638470 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4353638470 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4353638470 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4353638470 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -534,19 +669,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104230.249446 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104230.249446 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 104018.054476 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104018.054476 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 104018.054476 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104018.054476 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 117509 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54988.225434 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54988.225434 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104546.724755 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 104546.724755 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 104341.245536 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 104341.245536 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 113861 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11192 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11412 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.499375 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.977305 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -554,36 +689,36 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 16768 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 16768 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 16837 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3458522887 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3458522887 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3464112136 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3464112136 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3464112136 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3464112136 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17349 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5924213 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5924213 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3445287507 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3445287507 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3451211720 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3451211720 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3451211720 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3451211720 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 206257.328662 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 206257.328662 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85858.159420 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 85858.159420 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199380.064062 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199380.064062 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -601,22 +736,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4882934 # DTB read hits -system.cpu0.dtb.read_misses 6016 # DTB read misses -system.cpu0.dtb.read_acv 120 # DTB read access violations -system.cpu0.dtb.read_accesses 427387 # DTB read accesses -system.cpu0.dtb.write_hits 3510109 # DTB write hits -system.cpu0.dtb.write_misses 663 # DTB write misses -system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162920 # DTB write accesses -system.cpu0.dtb.data_hits 8393043 # DTB hits -system.cpu0.dtb.data_misses 6679 # DTB misses -system.cpu0.dtb.data_acv 202 # DTB access violations -system.cpu0.dtb.data_accesses 590307 # DTB accesses -system.cpu0.itb.fetch_hits 2747668 # ITB hits -system.cpu0.itb.fetch_misses 3002 # ITB misses -system.cpu0.itb.fetch_acv 100 # ITB acv -system.cpu0.itb.fetch_accesses 2750670 # ITB accesses +system.cpu0.dtb.read_hits 4916475 # DTB read hits +system.cpu0.dtb.read_misses 6063 # DTB read misses +system.cpu0.dtb.read_acv 126 # DTB read access violations +system.cpu0.dtb.read_accesses 427415 # DTB read accesses +system.cpu0.dtb.write_hits 3510632 # DTB write hits +system.cpu0.dtb.write_misses 668 # DTB write misses +system.cpu0.dtb.write_acv 84 # DTB write access violations +system.cpu0.dtb.write_accesses 162993 # DTB write accesses +system.cpu0.dtb.data_hits 8427107 # DTB hits +system.cpu0.dtb.data_misses 6731 # DTB misses +system.cpu0.dtb.data_acv 210 # DTB access violations +system.cpu0.dtb.data_accesses 590408 # DTB accesses +system.cpu0.itb.fetch_hits 2754785 # ITB hits +system.cpu0.itb.fetch_misses 3015 # ITB misses +system.cpu0.itb.fetch_acv 104 # ITB acv +system.cpu0.itb.fetch_accesses 2757800 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -629,51 +764,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928534019 # number of cpu cycles simulated +system.cpu0.numCycles 928378822 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33030135 # Number of instructions committed -system.cpu0.committedOps 33030135 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30904296 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 168660 # Number of float alu accesses -system.cpu0.num_func_calls 809909 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4463035 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30904296 # number of integer instructions -system.cpu0.num_fp_insts 168660 # number of float instructions -system.cpu0.num_int_register_reads 43221651 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22562663 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87082 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88661 # number of times the floating registers were written -system.cpu0.num_mem_refs 8422848 # number of memory refs -system.cpu0.num_load_insts 4904051 # Number of load instructions -system.cpu0.num_store_insts 3518797 # Number of store instructions -system.cpu0.num_idle_cycles 214028158129.505707 # Number of idle cycles -system.cpu0.num_busy_cycles -213099624110.505707 # Number of busy cycles -system.cpu0.not_idle_fraction -229.501149 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.501149 # Percentage of idle cycles +system.cpu0.committedInsts 33851772 # Number of instructions committed +system.cpu0.committedOps 33851772 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31712153 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169925 # Number of float alu accesses +system.cpu0.num_func_calls 812668 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4695347 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31712153 # number of integer instructions +system.cpu0.num_fp_insts 169925 # number of float instructions +system.cpu0.num_int_register_reads 44553309 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23136473 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87700 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89305 # number of times the floating registers were written +system.cpu0.num_mem_refs 8457205 # number of memory refs +system.cpu0.num_load_insts 4937806 # Number of load instructions +system.cpu0.num_store_insts 3519399 # Number of store instructions +system.cpu0.num_idle_cycles 213007832176.448029 # Number of idle cycles +system.cpu0.num_busy_cycles -212079453354.448029 # Number of busy cycles +system.cpu0.not_idle_fraction -228.440641 # Percentage of non-idle cycles +system.cpu0.idle_fraction 229.440641 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211352 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105677 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182552 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818574542500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39495500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 364949500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22741309000 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841720296500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819523663000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39251000 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365640000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22768477500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842697031500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694825 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815850 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -712,29 +847,29 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175295 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192206 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches +system.cpu0.kern.callpal::total 192238 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1907 system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322074 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.321965 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29798472500 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2570740000 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809351079500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29806042000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2607375500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810283609500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -767,372 +902,458 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 953317 # number of replacements -system.cpu0.icache.tagsinuse 511.202573 # Cycle average of tags in use -system.cpu0.icache.total_refs 42520473 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953828 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 44.578764 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10247489000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 251.172377 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 83.809654 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 176.220543 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.490571 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.163691 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.344181 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998443 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32512787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7733014 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2274672 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42520473 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32512787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7733014 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2274672 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42520473 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32512787 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7733014 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2274672 # number of overall hits -system.cpu0.icache.overall_hits::total 42520473 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 524229 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129219 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 317357 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970805 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 524229 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129219 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 317357 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970805 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 524229 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129219 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 317357 # number of overall misses -system.cpu0.icache.overall_misses::total 970805 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820764500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4451463485 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6272227985 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1820764500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4451463485 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6272227985 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1820764500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4451463485 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6272227985 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33037016 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7862233 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2592029 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43491278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33037016 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7862233 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2592029 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43491278 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33037016 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7862233 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2592029 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43491278 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015868 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016435 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122436 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022322 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015868 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016435 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122436 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022322 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015868 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016435 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122436 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022322 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14090.532352 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14026.674959 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6460.852576 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14090.532352 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14026.674959 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6460.852576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14090.532352 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14026.674959 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6460.852576 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7042 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 180 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 39.122222 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.toL2Bus.throughput 110454960 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 786209 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 786164 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371427 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150852 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133572 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 847417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1371009 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 2218426 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27116864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55346243 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 82463107 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203524040 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2135036000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1907460021 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2223763109 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1469142 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2977 # Transaction distribution +system.iobus.trans_dist::ReadResp 2977 # Transaction distribution +system.iobus.trans_dist::WriteReq 21029 # Transaction distribution +system.iobus.trans_dist::WriteResp 21029 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 48012 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15747 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1123115 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2707184 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 6219000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 1797000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 157278470 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 9565000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 17530000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.replacements 950939 # number of replacements +system.cpu0.icache.tagsinuse 511.192426 # Cycle average of tags in use +system.cpu0.icache.total_refs 43369559 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 951450 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 45.582594 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10375508000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 249.451681 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 99.242283 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 162.498462 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.487210 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.193833 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.317380 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998423 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 33330806 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7798498 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2240255 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43369559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 33330806 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7798498 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2240255 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43369559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 33330806 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7798498 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2240255 # number of overall hits +system.cpu0.icache.overall_hits::total 43369559 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 527907 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 126362 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 313908 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 968177 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 527907 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 126362 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 313908 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 968177 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 527907 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 126362 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 313908 # number of overall misses +system.cpu0.icache.overall_misses::total 968177 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1815628000 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6433967128 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9702733128 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3268766000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6433967128 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9702733128 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287559000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353651000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 641210000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356203000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 430620000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786823000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 643762000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 784271000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1428033000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087118 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088515 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041030 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045415 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021583 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099840 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 144505 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 341032 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 485537 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 144505 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341032 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 485537 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2060552500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4252408235 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6312960735 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1528691000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2589747290 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4118438290 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24153500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66206002 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90359502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 23000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 23000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3589243500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6842155525 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10431399025 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3589243500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6842155525 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10431399025 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295697000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311546500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607243500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 363354500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790734000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 659051500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 738926000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083742 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086377 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039510 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051114 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046891 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021691 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100373 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099599 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037310 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18847.946095 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16439.918892 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17128.636129 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26831.748695 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25295.057091 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25853.870875 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.134892 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12798.145117 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.765247 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032237 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032237 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20733.659013 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16820.503202 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17924.719500 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33878.310396 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29355.224833 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30885.816310 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11213.324048 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12230.925919 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11941.258359 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 23000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1147,22 +1368,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1221065 # DTB read hits -system.cpu1.dtb.read_misses 1489 # DTB read misses -system.cpu1.dtb.read_acv 40 # DTB read access violations -system.cpu1.dtb.read_accesses 143781 # DTB read accesses -system.cpu1.dtb.write_hits 929390 # DTB write hits -system.cpu1.dtb.write_misses 202 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 59266 # DTB write accesses -system.cpu1.dtb.data_hits 2150455 # DTB hits -system.cpu1.dtb.data_misses 1691 # DTB misses -system.cpu1.dtb.data_acv 64 # DTB access violations -system.cpu1.dtb.data_accesses 203047 # DTB accesses -system.cpu1.itb.fetch_hits 872017 # ITB hits -system.cpu1.itb.fetch_misses 756 # ITB misses -system.cpu1.itb.fetch_acv 43 # ITB acv -system.cpu1.itb.fetch_accesses 872773 # ITB accesses +system.cpu1.dtb.read_hits 1206143 # DTB read hits +system.cpu1.dtb.read_misses 1395 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 142828 # DTB read accesses +system.cpu1.dtb.write_hits 904590 # DTB write hits +system.cpu1.dtb.write_misses 190 # DTB write misses +system.cpu1.dtb.write_acv 23 # DTB write access violations +system.cpu1.dtb.write_accesses 58592 # DTB write accesses +system.cpu1.dtb.data_hits 2110733 # DTB hits +system.cpu1.dtb.data_misses 1585 # DTB misses +system.cpu1.dtb.data_acv 58 # DTB access violations +system.cpu1.dtb.data_accesses 201420 # DTB accesses +system.cpu1.itb.fetch_hits 862559 # ITB hits +system.cpu1.itb.fetch_misses 707 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 863266 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1175,28 +1396,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953614996 # number of cpu cycles simulated +system.cpu1.numCycles 953614983 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7860477 # Number of instructions committed -system.cpu1.committedOps 7860477 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7311992 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45303 # Number of float alu accesses -system.cpu1.num_func_calls 212165 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 960179 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7311992 # number of integer instructions -system.cpu1.num_fp_insts 45303 # number of float instructions -system.cpu1.num_int_register_reads 10165443 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5319467 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24490 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24717 # number of times the floating registers were written -system.cpu1.num_mem_refs 2158115 # number of memory refs -system.cpu1.num_load_insts 1226297 # Number of load instructions -system.cpu1.num_store_insts 931818 # Number of store instructions -system.cpu1.num_idle_cycles -703122010.262243 # Number of idle cycles -system.cpu1.num_busy_cycles 1656737006.262243 # Number of busy cycles -system.cpu1.not_idle_fraction 1.737323 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.737323 # Percentage of idle cycles +system.cpu1.committedInsts 7923216 # Number of instructions committed +system.cpu1.committedOps 7923216 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7378774 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44696 # Number of float alu accesses +system.cpu1.num_func_calls 212761 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1003934 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7378774 # number of integer instructions +system.cpu1.num_fp_insts 44696 # number of float instructions +system.cpu1.num_int_register_reads 10322317 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5366754 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24140 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24473 # number of times the floating registers were written +system.cpu1.num_mem_refs 2118035 # number of memory refs +system.cpu1.num_load_insts 1211092 # Number of load instructions +system.cpu1.num_store_insts 906943 # Number of store instructions +system.cpu1.num_idle_cycles -710985323.015638 # Number of idle cycles +system.cpu1.num_busy_cycles 1664600306.015638 # Number of busy cycles +system.cpu1.not_idle_fraction 1.745569 # Percentage of non-idle cycles +system.cpu1.idle_fraction -0.745569 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1214,35 +1435,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8370437 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7682240 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 128031 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6854257 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5743720 # Number of BTB hits +system.cpu2.branchPred.lookups 8997247 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8318296 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 124435 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7453298 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6389224 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 83.797850 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 284899 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 14987 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.723448 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 282371 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13443 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3211638 # DTB read hits -system.cpu2.dtb.read_misses 11756 # DTB read misses -system.cpu2.dtb.read_acv 123 # DTB read access violations -system.cpu2.dtb.read_accesses 216825 # DTB read accesses -system.cpu2.dtb.write_hits 1985602 # DTB write hits -system.cpu2.dtb.write_misses 2511 # DTB write misses -system.cpu2.dtb.write_acv 137 # DTB write access violations -system.cpu2.dtb.write_accesses 81903 # DTB write accesses -system.cpu2.dtb.data_hits 5197240 # DTB hits -system.cpu2.dtb.data_misses 14267 # DTB misses -system.cpu2.dtb.data_acv 260 # DTB access violations -system.cpu2.dtb.data_accesses 298728 # DTB accesses -system.cpu2.itb.fetch_hits 370869 # ITB hits -system.cpu2.itb.fetch_misses 5705 # ITB misses -system.cpu2.itb.fetch_acv 274 # ITB acv -system.cpu2.itb.fetch_accesses 376574 # ITB accesses +system.cpu2.dtb.read_hits 3184667 # DTB read hits +system.cpu2.dtb.read_misses 11563 # DTB read misses +system.cpu2.dtb.read_acv 122 # DTB read access violations +system.cpu2.dtb.read_accesses 218108 # DTB read accesses +system.cpu2.dtb.write_hits 2003168 # DTB write hits +system.cpu2.dtb.write_misses 2582 # DTB write misses +system.cpu2.dtb.write_acv 105 # DTB write access violations +system.cpu2.dtb.write_accesses 82984 # DTB write accesses +system.cpu2.dtb.data_hits 5187835 # DTB hits +system.cpu2.dtb.data_misses 14145 # DTB misses +system.cpu2.dtb.data_acv 227 # DTB access violations +system.cpu2.dtb.data_accesses 301092 # DTB accesses +system.cpu2.itb.fetch_hits 370432 # ITB hits +system.cpu2.itb.fetch_misses 5697 # ITB misses +system.cpu2.itb.fetch_acv 245 # ITB acv +system.cpu2.itb.fetch_accesses 376129 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1255,270 +1476,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30454355 # number of cpu cycles simulated +system.cpu2.numCycles 31194709 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8502723 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34791371 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8370437 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6028619 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8097928 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 618452 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9649671 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10614 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63437 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 88147 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 485 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2592037 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 89025 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26817742 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.297327 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.307851 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8336463 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36595534 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8997247 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6671595 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8714180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 607609 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9678498 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11323 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1980 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 64467 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 86613 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2554168 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 86055 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27288913 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.341040 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.295561 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18719814 69.80% 69.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 271918 1.01% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 439106 1.64% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4240914 15.81% 88.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 731900 2.73% 91.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 166811 0.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 194731 0.73% 92.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 431926 1.61% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1620622 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18574733 68.07% 68.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269160 0.99% 69.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 428961 1.57% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4866915 17.83% 88.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 754326 2.76% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165422 0.61% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 191254 0.70% 92.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 429367 1.57% 94.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1608775 5.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26817742 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.274852 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.142410 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8640997 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9744638 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7501940 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293665 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 390587 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 167981 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12867 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34389263 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40403 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 390587 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8994385 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2850333 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5733998 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7360278 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1242256 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33240737 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2380 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234906 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 409580 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22320164 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41423386 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41259446 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 163940 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20500425 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1819739 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 502711 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59638 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3682174 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3369954 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2075842 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 372990 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 254270 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30724821 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 626542 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30272457 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 30970 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2165066 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1087715 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 442386 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26817742 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.128822 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.564509 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27288913 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288422 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.173133 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8484758 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9763089 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8105885 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 306526 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 382761 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165822 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12764 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36197990 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39851 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 382761 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8844170 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2798398 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5770090 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7975185 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1272419 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35047656 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 232046 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 447152 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23489226 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43822690 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43659490 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 163200 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21694214 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1795012 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 501276 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59320 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3724979 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3343402 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2093050 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 368261 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 257932 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32557394 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 620599 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32107794 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 34091 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2143269 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1080696 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 438167 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27288913 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.176588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.573888 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15272797 56.95% 56.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3099841 11.56% 68.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1551477 5.79% 74.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5057037 18.86% 93.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 907037 3.38% 96.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 485633 1.81% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 283575 1.06% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141972 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18373 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15150790 55.52% 55.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3070151 11.25% 66.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1548988 5.68% 72.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5689584 20.85% 93.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 903005 3.31% 96.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480338 1.76% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 283929 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 143393 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18735 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26817742 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27288913 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34129 13.74% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 111357 44.84% 58.58% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 102854 41.42% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33803 13.75% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 111727 45.45% 59.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100297 40.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24602631 81.27% 81.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20294 0.07% 81.35% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8465 0.03% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3340354 11.03% 92.41% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2007868 6.63% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289173 0.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26449669 82.38% 82.39% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20147 0.06% 82.45% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8446 0.03% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3312033 10.32% 92.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2025467 6.31% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288360 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30272457 # Type of FU issued -system.cpu2.iq.rate 0.994027 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 248340 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008203 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87406741 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33405587 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29873950 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 235225 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114899 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 111509 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30395868 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122481 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 188565 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32107794 # Type of FU issued +system.cpu2.iq.rate 1.029271 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 245827 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 91550157 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35210267 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 31710626 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234262 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114809 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110859 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32229265 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121908 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186278 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 411297 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 939 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4131 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 160227 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 409987 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1098 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3916 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 156672 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4708 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 24260 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4171 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28368 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 390587 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2070216 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 210596 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32630441 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224813 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3369954 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2075842 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 556425 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 148713 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2116 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4131 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 65748 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 128933 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 194681 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30112166 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3231643 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 160291 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 382761 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2017515 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 205037 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34446466 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224960 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3343402 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2093050 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 551127 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 142834 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3916 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63764 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127616 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 191380 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31948816 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3204490 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 158978 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1279078 # number of nop insts executed -system.cpu2.iew.exec_refs 5224243 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6789433 # Number of branches executed -system.cpu2.iew.exec_stores 1992600 # Number of stores executed -system.cpu2.iew.exec_rate 0.988764 # Inst execution rate -system.cpu2.iew.wb_sent 30017965 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29985459 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17323993 # num instructions producing a value -system.cpu2.iew.wb_consumers 20546016 # num instructions consuming a value +system.cpu2.iew.exec_nop 1268473 # number of nop insts executed +system.cpu2.iew.exec_refs 5214665 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7427208 # Number of branches executed +system.cpu2.iew.exec_stores 2010175 # Number of stores executed +system.cpu2.iew.exec_rate 1.024174 # Inst execution rate +system.cpu2.iew.wb_sent 31853816 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31821485 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18500784 # num instructions producing a value +system.cpu2.iew.wb_consumers 21694431 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.984603 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.843180 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.020092 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.852790 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2350466 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 184156 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180720 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26427155 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.144119 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.849310 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2318994 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182432 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 176935 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26906152 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.192355 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846387 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16325181 61.77% 61.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2317842 8.77% 70.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1215370 4.60% 75.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4792789 18.14% 93.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 500443 1.89% 95.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186108 0.70% 95.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 178909 0.68% 96.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180996 0.68% 97.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 729517 2.76% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16157542 60.05% 60.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2331595 8.67% 68.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1218913 4.53% 73.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5433463 20.19% 93.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 503772 1.87% 95.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185469 0.69% 96.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 177448 0.66% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 178843 0.66% 97.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 719107 2.67% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26427155 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30235823 # Number of instructions committed -system.cpu2.commit.committedOps 30235823 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26906152 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32081688 # Number of instructions committed +system.cpu2.commit.committedOps 32081688 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4874272 # Number of memory references committed -system.cpu2.commit.loads 2958657 # Number of loads committed -system.cpu2.commit.membars 64665 # Number of memory barriers committed -system.cpu2.commit.branches 6641301 # Number of branches committed -system.cpu2.commit.fp_insts 110294 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28781664 # Number of committed integer instructions. -system.cpu2.commit.function_calls 230734 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 729517 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4869793 # Number of memory references committed +system.cpu2.commit.loads 2933415 # Number of loads committed +system.cpu2.commit.membars 63859 # Number of memory barriers committed +system.cpu2.commit.branches 7280639 # Number of branches committed +system.cpu2.commit.fp_insts 109636 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30638732 # Number of committed integer instructions. +system.cpu2.commit.function_calls 228563 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 719107 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58211181 # The number of ROB reads -system.cpu2.rob.rob_writes 65562875 # The number of ROB writes -system.cpu2.timesIdled 242498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3636613 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745370399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29064101 # Number of Instructions Simulated -system.cpu2.committedOps 29064101 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29064101 # Number of Instructions Simulated -system.cpu2.cpi 1.047834 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.047834 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.954350 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.954350 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39595533 # number of integer regfile reads -system.cpu2.int_regfile_writes 21195830 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68078 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68404 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4592506 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258747 # number of misc regfile writes +system.cpu2.rob.rob_reads 60513787 # The number of ROB reads +system.cpu2.rob.rob_writes 69183653 # The number of ROB writes +system.cpu2.timesIdled 245794 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3905796 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746583104 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 30918811 # Number of Instructions Simulated +system.cpu2.committedOps 30918811 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 30918811 # Number of Instructions Simulated +system.cpu2.cpi 1.008923 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.008923 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.991156 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.991156 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42017360 # number of integer regfile reads +system.cpu2.int_regfile_writes 22376128 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67819 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67985 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5215792 # number of misc regfile reads +system.cpu2.misc_regfile_writes 257331 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |