diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt | 3027 |
1 files changed, 1510 insertions, 1517 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index b0cdac391..43a4f79aa 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842592 # Number of seconds simulated -sim_ticks 1842591955000 # Number of ticks simulated -final_tick 1842591955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841539 # Number of seconds simulated +sim_ticks 1841538755500 # Number of ticks simulated +final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212167 # Simulator instruction rate (inst/s) -host_op_rate 212167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5858461865 # Simulator tick rate (ticks/s) -host_mem_usage 373744 # Number of bytes of host memory used -host_seconds 314.52 # Real time elapsed on the host -sim_insts 66730424 # Number of instructions simulated -sim_ops 66730424 # Number of ops (including micro ops) simulated +host_inst_rate 221552 # Simulator instruction rate (inst/s) +host_op_rate 221552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5785089232 # Simulator tick rate (ticks/s) +host_mem_usage 374344 # Number of bytes of host memory used +host_seconds 318.33 # Real time elapsed on the host +sim_insts 70525499 # Number of instructions simulated +sim_ops 70525499 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20072256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2246976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2555648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 467648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20091072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2148032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 308096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2634304 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25796928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 921088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481920 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481920 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313629 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2295 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39932 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25797120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 467648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 308096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 922752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7481856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7481856 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4814 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41161 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403077 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116905 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116905 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10893489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1219465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1386985 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403080 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116904 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116904 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 253944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1166433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 167304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1430491 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14000348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4060541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4060541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4060541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10893489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1219465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1386985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14008459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 253944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 167304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 501077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4062828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4062828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4062828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 253944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1166433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 167304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1430491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18060889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81945 # Number of read requests accepted -system.physmem.writeReqs 62218 # Number of write requests accepted -system.physmem.readBursts 81945 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 62218 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5243136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue -system.physmem.bytesWritten 3931008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5244480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3981952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 773 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 65 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5216 # Per bank write bursts -system.physmem.perBankRdBursts::1 4952 # Per bank write bursts -system.physmem.perBankRdBursts::2 4966 # Per bank write bursts -system.physmem.perBankRdBursts::3 5032 # Per bank write bursts -system.physmem.perBankRdBursts::4 5011 # Per bank write bursts -system.physmem.perBankRdBursts::5 5077 # Per bank write bursts -system.physmem.perBankRdBursts::6 5139 # Per bank write bursts -system.physmem.perBankRdBursts::7 5153 # Per bank write bursts -system.physmem.perBankRdBursts::8 5336 # Per bank write bursts -system.physmem.perBankRdBursts::9 5012 # Per bank write bursts -system.physmem.perBankRdBursts::10 5284 # Per bank write bursts -system.physmem.perBankRdBursts::11 5137 # Per bank write bursts -system.physmem.perBankRdBursts::12 4814 # Per bank write bursts -system.physmem.perBankRdBursts::13 5083 # Per bank write bursts -system.physmem.perBankRdBursts::14 5582 # Per bank write bursts -system.physmem.perBankRdBursts::15 5130 # Per bank write bursts -system.physmem.perBankWrBursts::0 3820 # Per bank write bursts -system.physmem.perBankWrBursts::1 3672 # Per bank write bursts -system.physmem.perBankWrBursts::2 3762 # Per bank write bursts -system.physmem.perBankWrBursts::3 4075 # Per bank write bursts -system.physmem.perBankWrBursts::4 3759 # Per bank write bursts -system.physmem.perBankWrBursts::5 3520 # Per bank write bursts -system.physmem.perBankWrBursts::6 4123 # Per bank write bursts -system.physmem.perBankWrBursts::7 3706 # Per bank write bursts -system.physmem.perBankWrBursts::8 4379 # Per bank write bursts -system.physmem.perBankWrBursts::9 3471 # Per bank write bursts -system.physmem.perBankWrBursts::10 3889 # Per bank write bursts -system.physmem.perBankWrBursts::11 3981 # Per bank write bursts -system.physmem.perBankWrBursts::12 3541 # Per bank write bursts -system.physmem.perBankWrBursts::13 3879 # Per bank write bursts -system.physmem.perBankWrBursts::14 4169 # Per bank write bursts -system.physmem.perBankWrBursts::15 3676 # Per bank write bursts +system.physmem.bw_total::total 18071287 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81850 # Number of read requests accepted +system.physmem.writeReqs 64472 # Number of write requests accepted +system.physmem.readBursts 81850 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 64472 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5236928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1472 # Total number of bytes read from write queue +system.physmem.bytesWritten 3416192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5238400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4126208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 23 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11076 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4878 # Per bank write bursts +system.physmem.perBankRdBursts::1 4919 # Per bank write bursts +system.physmem.perBankRdBursts::2 4947 # Per bank write bursts +system.physmem.perBankRdBursts::3 4947 # Per bank write bursts +system.physmem.perBankRdBursts::4 5010 # Per bank write bursts +system.physmem.perBankRdBursts::5 5136 # Per bank write bursts +system.physmem.perBankRdBursts::6 5318 # Per bank write bursts +system.physmem.perBankRdBursts::7 5111 # Per bank write bursts +system.physmem.perBankRdBursts::8 5349 # Per bank write bursts +system.physmem.perBankRdBursts::9 4830 # Per bank write bursts +system.physmem.perBankRdBursts::10 5530 # Per bank write bursts +system.physmem.perBankRdBursts::11 5119 # Per bank write bursts +system.physmem.perBankRdBursts::12 4880 # Per bank write bursts +system.physmem.perBankRdBursts::13 5044 # Per bank write bursts +system.physmem.perBankRdBursts::14 5637 # Per bank write bursts +system.physmem.perBankRdBursts::15 5172 # Per bank write bursts +system.physmem.perBankWrBursts::0 3097 # Per bank write bursts +system.physmem.perBankWrBursts::1 3264 # Per bank write bursts +system.physmem.perBankWrBursts::2 3389 # Per bank write bursts +system.physmem.perBankWrBursts::3 3378 # Per bank write bursts +system.physmem.perBankWrBursts::4 3165 # Per bank write bursts +system.physmem.perBankWrBursts::5 3060 # Per bank write bursts +system.physmem.perBankWrBursts::6 3647 # Per bank write bursts +system.physmem.perBankWrBursts::7 3165 # Per bank write bursts +system.physmem.perBankWrBursts::8 3847 # Per bank write bursts +system.physmem.perBankWrBursts::9 3079 # Per bank write bursts +system.physmem.perBankWrBursts::10 3680 # Per bank write bursts +system.physmem.perBankWrBursts::11 3339 # Per bank write bursts +system.physmem.perBankWrBursts::12 2997 # Per bank write bursts +system.physmem.perBankWrBursts::13 3248 # Per bank write bursts +system.physmem.perBankWrBursts::14 3739 # Per bank write bursts +system.physmem.perBankWrBursts::15 3284 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1841579678500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1840526879500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81945 # Read request sizes (log2) +system.physmem.readPktSize::6 81850 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 62218 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64472 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -153,216 +153,196 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 411.784371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 233.119875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 394.569349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7102 31.88% 31.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4721 21.19% 53.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1798 8.07% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1010 4.53% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 955 4.29% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 478 2.15% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 370 1.66% 73.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 364 1.63% 75.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5481 24.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22279 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.475810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1006.180082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2127 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 41 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.924780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 222.627349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 384.024543 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7145 32.28% 32.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4994 22.56% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1972 8.91% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1000 4.52% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 834 3.77% 72.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 471 2.13% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 534 2.41% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 337 1.52% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4848 21.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22135 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 42.863279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1017.016663 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1907 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2129 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2129 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.850164 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.675931 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 36.499081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.60% 1.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.33% 1.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 1.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 1 0.05% 2.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1615 75.86% 77.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 1.64% 79.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.47% 79.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 84 3.95% 83.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 64 3.01% 86.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 45 2.11% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.42% 89.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.52% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 35 1.64% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.23% 91.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 21 0.99% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.09% 92.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.14% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.09% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.23% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.19% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.05% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.14% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.19% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.05% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.05% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.28% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.09% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.05% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 15 0.70% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.14% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.09% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.05% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.19% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 43 2.02% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.05% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 11 0.52% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.14% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.14% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.09% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 6 0.28% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.19% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 5 0.23% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.14% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.14% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.14% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2129 # Writes before turning the bus around for reads -system.physmem.totQLat 814366500 # Total ticks spent queuing -system.physmem.totMemAccLat 2350441500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9940.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 1909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.961236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.965205 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.780578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 45 2.36% 2.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 1768 92.61% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 14 0.73% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 2 0.10% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 2 0.10% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 1 0.05% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 1 0.05% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 2 0.10% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.58% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.63% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 5 0.26% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 8 0.42% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 1 0.05% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.05% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.10% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.10% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.31% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.26% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 2 0.10% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.10% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.05% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.05% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.10% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.16% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 4 0.21% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 2 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1909 # Writes before turning the bus around for reads +system.physmem.totQLat 884680000 # Total ticks spent queuing +system.physmem.totMemAccLat 2418936250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 409135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10811.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28690.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29561.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.24 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 70260 # Number of row buffer hits during reads -system.physmem.writeRowHits 50807 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.69 # Row buffer hit rate for writes -system.physmem.avgGap 12774287.98 # Average gap between requests -system.physmem.pageHitRate 84.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 83779920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 45618375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 316258800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 197231760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35724246975 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 802806617250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 928299910200 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.726630 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309959191250 # Time in different power states -system.physmem_0.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.99 # Average write queue length when enqueuing +system.physmem.readRowHits 70087 # Number of row buffer hits during reads +system.physmem.writeRowHits 42983 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes +system.physmem.avgGap 12578606.63 # Average gap between requests +system.physmem.pageHitRate 83.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 81814320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 44558250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 314074800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 169549200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35647575705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 798651060750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 923964608865 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.989912 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309028017250 # Time in different power states +system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9222216250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9101184500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 84649320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 46030875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 322748400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 200782800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35431940430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799831550250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 925043859195 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.972279 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1310405285500 # Time in different power states -system.physmem_1.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_1.actEnergy 85526280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 46513500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 324175800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 176340240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35475772860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 801505403250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 926669707770 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.770193 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309231204000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8771812500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8903896000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4841130 # DTB read hits -system.cpu0.dtb.read_misses 6162 # DTB read misses -system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 429577 # DTB read accesses -system.cpu0.dtb.write_hits 3448228 # DTB write hits -system.cpu0.dtb.write_misses 688 # DTB write misses -system.cpu0.dtb.write_acv 85 # DTB write access violations -system.cpu0.dtb.write_accesses 165228 # DTB write accesses -system.cpu0.dtb.data_hits 8289358 # DTB hits -system.cpu0.dtb.data_misses 6850 # DTB misses -system.cpu0.dtb.data_acv 211 # DTB access violations -system.cpu0.dtb.data_accesses 594805 # DTB accesses -system.cpu0.itb.fetch_hits 2744473 # ITB hits -system.cpu0.itb.fetch_misses 3071 # ITB misses -system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2747544 # ITB accesses +system.cpu0.dtb.read_hits 4781172 # DTB read hits +system.cpu0.dtb.read_misses 6058 # DTB read misses +system.cpu0.dtb.read_acv 118 # DTB read access violations +system.cpu0.dtb.read_accesses 428328 # DTB read accesses +system.cpu0.dtb.write_hits 3391530 # DTB write hits +system.cpu0.dtb.write_misses 675 # DTB write misses +system.cpu0.dtb.write_acv 82 # DTB write access violations +system.cpu0.dtb.write_accesses 163639 # DTB write accesses +system.cpu0.dtb.data_hits 8172702 # DTB hits +system.cpu0.dtb.data_misses 6733 # DTB misses +system.cpu0.dtb.data_acv 200 # DTB access violations +system.cpu0.dtb.data_accesses 591967 # DTB accesses +system.cpu0.itb.fetch_hits 2720050 # ITB hits +system.cpu0.itb.fetch_misses 3046 # ITB misses +system.cpu0.itb.fetch_acv 99 # ITB acv +system.cpu0.itb.fetch_accesses 2723096 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -375,87 +355,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 929111283 # number of cpu cycles simulated +system.cpu0.numCycles 930048733 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30392058 # Number of instructions committed -system.cpu0.committedOps 30392058 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28296981 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165313 # Number of float alu accesses -system.cpu0.num_func_calls 800920 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3653475 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28296981 # number of integer instructions -system.cpu0.num_fp_insts 165313 # number of float instructions -system.cpu0.num_int_register_reads 38988704 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20831324 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85482 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86956 # number of times the floating registers were written -system.cpu0.num_mem_refs 8319320 # number of memory refs -system.cpu0.num_load_insts 4862427 # Number of load instructions -system.cpu0.num_store_insts 3456893 # Number of store instructions -system.cpu0.num_idle_cycles 905971177.002448 # Number of idle cycles -system.cpu0.num_busy_cycles 23140105.997552 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024906 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975094 # Percentage of idle cycles -system.cpu0.Branches 4712544 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1584509 5.21% 5.21% # Class of executed instruction -system.cpu0.op_class::IntAlu 19793641 65.11% 70.32% # Class of executed instruction -system.cpu0.op_class::IntMult 31883 0.10% 70.43% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.43% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12951 0.04% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.01% 70.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::MemRead 4993701 16.43% 86.90% # Class of executed instruction -system.cpu0.op_class::MemWrite 3459999 11.38% 98.29% # Class of executed instruction -system.cpu0.op_class::IprAccess 520829 1.71% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31504183 # Number of instructions committed +system.cpu0.committedOps 31504183 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29439494 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 162688 # Number of float alu accesses +system.cpu0.num_func_calls 792913 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4107229 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29439494 # number of integer instructions +system.cpu0.num_fp_insts 162688 # number of float instructions +system.cpu0.num_int_register_reads 41004383 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21582488 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84172 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 85625 # number of times the floating registers were written +system.cpu0.num_mem_refs 8202083 # number of memory refs +system.cpu0.num_load_insts 4802046 # Number of load instructions +system.cpu0.num_store_insts 3400037 # Number of store instructions +system.cpu0.num_idle_cycles 907048310.649553 # Number of idle cycles +system.cpu0.num_busy_cycles 23000422.350447 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024730 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975270 # Percentage of idle cycles +system.cpu0.Branches 5154717 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1560474 4.95% 4.95% # Class of executed instruction +system.cpu0.op_class::IntAlu 21056937 66.82% 71.78% # Class of executed instruction +system.cpu0.op_class::IntMult 31354 0.10% 71.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12843 0.04% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1601 0.01% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::MemRead 4932088 15.65% 87.57% # Class of executed instruction +system.cpu0.op_class::MemWrite 3403118 10.80% 98.37% # Class of executed instruction +system.cpu0.op_class::IprAccess 512701 1.63% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30399119 # Class of executed instruction +system.cpu0.op_class::total 31511116 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6424 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211373 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211361 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105693 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182558 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819763275500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38885000 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357575500 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22431449500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842591185500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818811073000 98.77% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38572000 0.00% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 355311500 0.02% 98.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22333065000 1.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841538021500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694748 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815799 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694801 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815834 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -491,278 +471,276 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175301 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192228 # number of callpals executed +system.cpu0.kern.callpal::total 192212 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1910 -system.cpu0.kern.mode_good::user 1740 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322526 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1906 +system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391474 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29641344500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2562591500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810387245000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393017 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13281490 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393529 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.530831 # Average number of references to valid blocks. +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29730845000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2571229000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809235945500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1393219 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13266024 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393731 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.518353 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.752731 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 75.043138 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.201949 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509283 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146569 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.344144 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 178.252416 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.663502 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.081899 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.348149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.321608 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.330238 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63366474 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63366474 # 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miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050408 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.319840 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.138108 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.074343 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101905 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130772 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000199 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000055 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109567 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068847 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234932 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146480 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109567 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068847 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234932 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146480 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23383.689991 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14723.800471 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 7696.280978 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39879.335652 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30341.425666 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25022.595031 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13227.252353 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16314.489929 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8134.410577 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16818.363636 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16818.363636 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28532.384455 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23085.451201 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14352.705617 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28532.384455 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23085.451201 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14352.705617 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 977120 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1794 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 54184 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.033368 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 99.666667 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835667 # number of writebacks -system.cpu0.dcache.writebacks::total 835667 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10784984532 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249355000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342279000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591634000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320316500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419818000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740134500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569671500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762097000 # 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mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000128 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032909 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032909 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21117.509413 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16730.942626 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17881.477625 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35723.557518 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30061.023798 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31874.517165 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.944867 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12151.812730 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.794932 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835707 # number of writebacks +system.cpu0.dcache.writebacks::total 835707 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 287560 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 287560 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546849 # 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number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 139778 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2231 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6004 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8235 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 140963 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 365873 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 506836 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 140963 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 365873 # 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number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 168498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 168498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3795432990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7290735552 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11086168542 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3795432990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7290735552 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11086168542 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 222473500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 331326000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 553799500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 293979000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 446199000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740178000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 516452500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 777525000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1293977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082548 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087131 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041044 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050408 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047670 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022729 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102034 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040445 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068847 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5505189175 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1522394000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982795175 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5505189175 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011087 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011087 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011087 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16722 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16722 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16722 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16722 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16722 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16722 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128848 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329647 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 458495 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 128848 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 329647 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 458495 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 128848 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 329647 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 458495 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1645092750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4148478396 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5793571146 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1645092750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4148478396 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5793571146 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1645092750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4148478396 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5793571146 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010849 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010849 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010849 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12636.061780 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1166781 # DTB read hits -system.cpu1.dtb.read_misses 1314 # DTB read misses -system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 141633 # DTB read accesses -system.cpu1.dtb.write_hits 872888 # DTB write hits -system.cpu1.dtb.write_misses 168 # DTB write misses +system.cpu1.dtb.read_hits 1194215 # DTB read hits +system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 141030 # DTB read accesses +system.cpu1.dtb.write_hits 894755 # DTB write hits +system.cpu1.dtb.write_misses 169 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57088 # DTB write accesses -system.cpu1.dtb.data_hits 2039669 # DTB hits -system.cpu1.dtb.data_misses 1482 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 198721 # DTB accesses -system.cpu1.itb.fetch_hits 848090 # ITB hits -system.cpu1.itb.fetch_misses 662 # ITB misses -system.cpu1.itb.fetch_acv 32 # ITB acv -system.cpu1.itb.fetch_accesses 848752 # ITB accesses +system.cpu1.dtb.write_accesses 57515 # DTB write accesses +system.cpu1.dtb.data_hits 2088970 # DTB hits +system.cpu1.dtb.data_misses 1485 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 198545 # DTB accesses +system.cpu1.itb.fetch_hits 856400 # ITB hits +system.cpu1.itb.fetch_misses 653 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 857053 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -942,64 +920,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953408444 # number of cpu cycles simulated +system.cpu1.numCycles 953255662 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7454598 # Number of instructions committed -system.cpu1.committedOps 7454598 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6929268 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43953 # Number of float alu accesses -system.cpu1.num_func_calls 203515 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 903765 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6929268 # number of integer instructions -system.cpu1.num_fp_insts 43953 # number of float instructions -system.cpu1.num_int_register_reads 9641119 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5054145 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23746 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written -system.cpu1.num_mem_refs 2046592 # number of memory refs -system.cpu1.num_load_insts 1171450 # Number of load instructions -system.cpu1.num_store_insts 875142 # Number of store instructions -system.cpu1.num_idle_cycles 924951081.946169 # Number of idle cycles -system.cpu1.num_busy_cycles 28457362.053831 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029848 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970152 # Percentage of idle cycles -system.cpu1.Branches 1171881 # Number of branches fetched -system.cpu1.op_class::No_OpClass 398972 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 4837309 64.88% 70.23% # Class of executed instruction -system.cpu1.op_class::IntMult 8193 0.11% 70.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5097 0.07% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::MemRead 1199545 16.09% 86.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 876356 11.75% 98.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 129854 1.74% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7921357 # Number of instructions committed +system.cpu1.committedOps 7921357 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7380748 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45896 # Number of float alu accesses +system.cpu1.num_func_calls 207012 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1022630 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7380748 # number of integer instructions +system.cpu1.num_fp_insts 45896 # number of float instructions +system.cpu1.num_int_register_reads 10351742 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5363285 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24726 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written +system.cpu1.num_mem_refs 2096070 # number of memory refs +system.cpu1.num_load_insts 1198996 # Number of load instructions +system.cpu1.num_store_insts 897074 # Number of store instructions +system.cpu1.num_idle_cycles 923177922.874727 # Number of idle cycles +system.cpu1.num_busy_cycles 30077739.125273 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031553 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968447 # Percentage of idle cycles +system.cpu1.Branches 1296149 # Number of branches fetched +system.cpu1.op_class::No_OpClass 410448 5.18% 5.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 5236817 66.10% 71.28% # Class of executed instruction +system.cpu1.op_class::IntMult 8727 0.11% 71.39% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.39% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5162 0.07% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.46% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::MemRead 1228055 15.50% 86.96% # Class of executed instruction +system.cpu1.op_class::MemWrite 898300 11.34% 98.30% # Class of executed instruction +system.cpu1.op_class::IprAccess 134580 1.70% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7456136 # Class of executed instruction +system.cpu1.op_class::total 7922899 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1017,35 +995,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9673449 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8936896 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125098 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7569787 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5584968 # Number of BTB hits +system.cpu2.branchPred.lookups 10412478 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9668294 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 126557 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8251745 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6275895 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 73.779725 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 299823 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7809 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 76.055368 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 302998 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7851 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3461968 # DTB read hits -system.cpu2.dtb.read_misses 12174 # DTB read misses -system.cpu2.dtb.read_acv 114 # DTB read access violations -system.cpu2.dtb.read_accesses 224881 # DTB read accesses -system.cpu2.dtb.write_hits 2122047 # DTB write hits -system.cpu2.dtb.write_misses 2563 # DTB write misses -system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 83942 # DTB write accesses -system.cpu2.dtb.data_hits 5584015 # DTB hits -system.cpu2.dtb.data_misses 14737 # DTB misses -system.cpu2.dtb.data_acv 220 # DTB access violations -system.cpu2.dtb.data_accesses 308823 # DTB accesses -system.cpu2.itb.fetch_hits 534012 # ITB hits -system.cpu2.itb.fetch_misses 5788 # ITB misses -system.cpu2.itb.fetch_acv 158 # ITB acv -system.cpu2.itb.fetch_accesses 539800 # ITB accesses +system.cpu2.dtb.read_hits 3529660 # DTB read hits +system.cpu2.dtb.read_misses 12347 # DTB read misses +system.cpu2.dtb.read_acv 141 # DTB read access violations +system.cpu2.dtb.read_accesses 225697 # DTB read accesses +system.cpu2.dtb.write_hits 2155841 # DTB write hits +system.cpu2.dtb.write_misses 2820 # DTB write misses +system.cpu2.dtb.write_acv 143 # DTB write access violations +system.cpu2.dtb.write_accesses 84900 # DTB write accesses +system.cpu2.dtb.data_hits 5685501 # DTB hits +system.cpu2.dtb.data_misses 15167 # DTB misses +system.cpu2.dtb.data_acv 284 # DTB access violations +system.cpu2.dtb.data_accesses 310597 # DTB accesses +system.cpu2.itb.fetch_hits 538073 # ITB hits +system.cpu2.itb.fetch_misses 5955 # ITB misses +system.cpu2.itb.fetch_acv 169 # ITB acv +system.cpu2.itb.fetch_accesses 544028 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1058,305 +1036,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30013580 # number of cpu cycles simulated +system.cpu2.numCycles 30702821 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9363383 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37425902 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9673449 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5884791 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18558568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 408186 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10133 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 231517 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 99918 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 308 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2804138 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 92736 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 28469903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.314578 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.374234 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9319148 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 39738878 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10412478 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6578893 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 19243837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 412304 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 656 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 233877 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 108804 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2828172 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 93139 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 29124256 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.364460 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.368556 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20072313 70.50% 70.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312422 1.10% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 471724 1.66% 73.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3982470 13.99% 87.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 833365 2.93% 90.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 193345 0.68% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 238464 0.84% 91.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 434747 1.53% 93.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1931053 6.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20002999 68.68% 68.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 306830 1.05% 69.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 477568 1.64% 71.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4658363 15.99% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 855343 2.94% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 200502 0.69% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 234860 0.81% 91.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433547 1.49% 93.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1954244 6.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 28469903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.322302 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.246966 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7673000 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13050358 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6778876 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 530616 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 191226 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 175016 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13225 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34075356 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 43360 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 191226 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7953535 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4758129 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6310003 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6998808 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2012380 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33260601 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68695 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 404029 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57097 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 943831 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 22264761 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41311324 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41251440 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56013 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20369021 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1895740 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 527174 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63098 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3903100 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3489643 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2214871 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 462169 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329723 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30742037 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 676819 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30393110 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 17376 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2421658 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1144384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 483915 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 28469903 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.067552 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.605150 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 29124256 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.339138 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.294307 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7666487 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 12991565 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7744961 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 527663 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 193001 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 177358 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13514 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36364188 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42851 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 193001 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7942048 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4601261 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6305683 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7969678 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2112012 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35538074 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 62867 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 396006 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 59218 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1045972 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23773076 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44310063 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44249815 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56335 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21846032 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1927044 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 532665 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63556 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3796199 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3529311 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2248768 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 470664 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 333419 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32987424 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 681806 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32666998 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16031 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2457717 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1151235 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 487594 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 29124256 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.121642 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.623821 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17422923 61.20% 61.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2767864 9.72% 70.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1373994 4.83% 75.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4735624 16.63% 92.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1013556 3.56% 95.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 570411 2.00% 97.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 382804 1.34% 99.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154533 0.54% 99.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48194 0.17% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17381860 59.68% 59.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2746661 9.43% 69.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1371662 4.71% 73.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5386342 18.49% 92.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1029310 3.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 605779 2.08% 97.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 390861 1.34% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 167562 0.58% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44219 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 28469903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 29124256 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 82144 21.47% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 176872 46.24% 67.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 123495 32.29% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 85214 22.02% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179569 46.41% 68.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 122132 31.57% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24311305 79.99% 80.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21079 0.07% 80.07% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 80.07% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20485 0.07% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3589842 11.81% 91.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2146129 7.06% 99.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 300610 0.99% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26477502 81.05% 81.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21078 0.06% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20355 0.06% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1225 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3659635 11.20% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2180799 6.68% 99.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 303954 0.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30393110 # Type of FU issued -system.cpu2.iq.rate 1.012645 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 382511 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.012585 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 89403074 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33727235 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29817840 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 252936 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119279 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 116815 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30637549 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 135632 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205530 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32666998 # Type of FU issued +system.cpu2.iq.rate 1.063974 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 386915 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011844 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 94607462 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36013478 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32054290 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253736 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119374 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117198 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32915380 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136083 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205891 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 436638 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1484 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6154 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 181627 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 443704 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1465 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6049 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 180746 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4994 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 170094 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5094 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 200289 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 191226 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3996466 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 295299 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32798710 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 54858 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3489643 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2214871 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 602209 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15595 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 231865 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6154 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62873 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134195 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197068 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30195469 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3482644 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 197641 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 193001 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3976817 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 219021 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35063617 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 53776 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3529311 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2248768 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 606766 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12977 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 164349 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6049 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63932 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 135830 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 199762 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32464526 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3550760 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1379854 # number of nop insts executed -system.cpu2.iew.exec_refs 5611883 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6643679 # Number of branches executed -system.cpu2.iew.exec_stores 2129239 # Number of stores executed -system.cpu2.iew.exec_rate 1.006060 # Inst execution rate -system.cpu2.iew.wb_sent 29976342 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29934655 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17254819 # num instructions producing a value -system.cpu2.iew.wb_consumers 20895222 # num instructions consuming a value +system.cpu2.iew.exec_nop 1394387 # number of nop insts executed +system.cpu2.iew.exec_refs 5714159 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7350868 # Number of branches executed +system.cpu2.iew.exec_stores 2163399 # Number of stores executed +system.cpu2.iew.exec_rate 1.057379 # Inst execution rate +system.cpu2.iew.wb_sent 32215343 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32171488 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18756374 # num instructions producing a value +system.cpu2.iew.wb_consumers 22505351 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.997370 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.825778 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.047835 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.833418 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2658447 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180111 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28004103 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.074728 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.862098 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2693673 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194212 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 181849 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28653786 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.128143 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.870801 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18216020 65.05% 65.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2235913 7.98% 73.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1176646 4.20% 77.23% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4445185 15.87% 93.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 540129 1.93% 95.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200547 0.72% 95.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 166033 0.59% 96.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 176455 0.63% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 847175 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18143596 63.32% 63.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2243135 7.83% 71.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1187950 4.15% 75.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5112990 17.84% 93.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 566123 1.98% 95.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 201198 0.70% 95.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164794 0.58% 96.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 163684 0.57% 96.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 870316 3.04% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28004103 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30096794 # Number of instructions committed -system.cpu2.commit.committedOps 30096794 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28653786 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32325567 # Number of instructions committed +system.cpu2.commit.committedOps 32325567 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5086249 # Number of memory references committed -system.cpu2.commit.loads 3053005 # Number of loads committed -system.cpu2.commit.membars 67981 # Number of memory barriers committed -system.cpu2.commit.branches 6474041 # Number of branches committed -system.cpu2.commit.fp_insts 115125 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28589001 # Number of committed integer instructions. -system.cpu2.commit.function_calls 239427 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1215466 4.04% 4.04% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 23382957 77.69% 81.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20643 0.07% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20037 0.07% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3120986 10.37% 92.24% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2034876 6.76% 99.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 300609 1.00% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5153629 # Number of memory references committed +system.cpu2.commit.loads 3085607 # Number of loads committed +system.cpu2.commit.membars 68228 # Number of memory barriers committed +system.cpu2.commit.branches 7176692 # Number of branches committed +system.cpu2.commit.fp_insts 115672 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30802580 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241655 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1228058 3.80% 3.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 25528107 78.97% 82.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20647 0.06% 82.83% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.83% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20076 0.06% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1225 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3153835 9.76% 92.66% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2069665 6.40% 99.06% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 303954 0.94% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 30096794 # Class of committed instruction -system.cpu2.commit.bw_lim_events 847175 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 32325567 # Class of committed instruction +system.cpu2.commit.bw_lim_events 870316 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 59838509 # The number of ROB reads -system.cpu2.rob.rob_writes 65974697 # The number of ROB writes -system.cpu2.timesIdled 175016 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1543677 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747747743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 28883768 # Number of Instructions Simulated -system.cpu2.committedOps 28883768 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.039116 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.039116 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.962357 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.962357 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39632695 # number of integer regfile reads -system.cpu2.int_regfile_writes 21162382 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70702 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70843 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4340126 # number of misc regfile reads -system.cpu2.misc_regfile_writes 270474 # number of misc regfile writes +system.cpu2.rob.rob_reads 62726939 # The number of ROB reads +system.cpu2.rob.rob_writes 70507401 # The number of ROB writes +system.cpu2.timesIdled 178497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1578565 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745106872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31099959 # Number of Instructions Simulated +system.cpu2.committedOps 31099959 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.987230 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.987230 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.012935 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.012935 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42640475 # number of integer regfile reads +system.cpu2.int_regfile_writes 22658201 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70901 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71243 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5010785 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273099 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1371,10 +1349,10 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51363 # Transaction distribution -system.iobus.trans_dist::WriteResp 9811 # Transaction distribution +system.iobus.trans_dist::WriteReq 51362 # Transaction distribution +system.iobus.trans_dist::WriteResp 9810 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1386,11 +1364,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1402,37 +1380,41 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2232000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5529000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5364000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 58000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 166547212 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 100878274 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9356000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8843000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17276500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17495500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262651 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254165 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693890143000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262651 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693892917000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254165 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078385 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078385 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1446,14 +1428,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5628764250 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5628764250 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9417462 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9444962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9444962 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 3667270812 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 3667270812 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9444962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9444962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9444962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9444962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1470,19 +1452,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 86158 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54595.156069 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54595.156069 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 88257.383808 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 88257.383808 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54595.156069 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54595.156069 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9840 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4243 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.755894 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.308037 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1490,234 +1472,237 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17024 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4743516250 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4743516250 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5749962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5749962 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2768710812 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2768710812 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5749962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5749962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5749962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5749962 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.409704 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.409704 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278636.997768 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278636.997768 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82142.314286 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 160226.320139 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 160226.320139 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82142.314286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82142.314286 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337565 # number of replacements -system.l2c.tags.tagsinuse 65420.967844 # Cycle average of tags in use -system.l2c.tags.total_refs 2486640 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402728 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.174490 # Average number of references to valid blocks. +system.l2c.tags.replacements 337569 # number of replacements +system.l2c.tags.tagsinuse 65419.566617 # Cycle average of tags in use +system.l2c.tags.total_refs 2487366 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402731 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.176247 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54725.451973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2331.479005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2701.186077 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 572.371097 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 609.192683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2285.385373 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2195.901635 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035576 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041217 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009296 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034872 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033507 # 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Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.833435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.034524 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041683 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008187 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009149 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.036862 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.034384 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998223 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 974 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2636 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55307 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26265257 # Number of tag accesses +system.l2c.tags.data_accesses 26265257 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 499689 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 475179 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 126551 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83555 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 324793 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 258988 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1768755 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835707 # number of Writeback hits +system.l2c.Writeback_hits::total 835707 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75392 # number of writebacks +system.l2c.writebacks::total 75392 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2297 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 15641 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4814 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 16829 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 39581 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 17971 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 24427 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 42398 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2297 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 33612 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4814 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 41256 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 81979 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2297 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 33612 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4814 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 41256 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 81979 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 158665250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 968947500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 340372000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1046522250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2514507000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 347508 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 347508 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 36002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 36002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1138484010 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1854617279 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2993101289 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 158665250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2107431510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 340372000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2901139529 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5507608289 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 158665250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2107431510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 340372000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2901139529 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5507608289 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 207045500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 309444000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 516489500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 276013000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 418496000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 694509000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 483058500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 727940000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1210998500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.157678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.061015 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019247 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.578947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.354839 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408460 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.254337 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.140043 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034749 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034749 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61949.204015 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62185.646800 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63528.132185 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 31591.636364 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 31591.636364 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 18001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63351.177453 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75924.889630 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70595.341502 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1827,92 +1820,92 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 294932 # Transaction distribution -system.membus.trans_dist::ReadResp 294926 # Transaction distribution -system.membus.trans_dist::WriteReq 9811 # Transaction distribution -system.membus.trans_dist::WriteResp 9811 # Transaction distribution -system.membus.trans_dist::Writeback 116905 # Transaction distribution +system.membus.trans_dist::ReadReq 295002 # Transaction distribution +system.membus.trans_dist::ReadResp 294996 # Transaction distribution +system.membus.trans_dist::WriteReq 9810 # Transaction distribution +system.membus.trans_dist::WriteResp 9810 # Transaction distribution +system.membus.trans_dist::Writeback 116904 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 163 # Transaction distribution +system.membus.trans_dist::UpgradeReq 145 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 165 # Transaction distribution -system.membus.trans_dist::ReadExReq 115724 # Transaction distribution -system.membus.trans_dist::ReadExResp 115724 # Transaction distribution +system.membus.trans_dist::UpgradeResp 147 # Transaction distribution +system.membus.trans_dist::ReadExReq 115657 # Transaction distribution +system.membus.trans_dist::ReadExResp 115657 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882256 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041133 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30678792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1041083 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30677824 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36002440 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 140 # Total snoops (count) -system.membus.snoop_fanout::samples 562134 # Request fanout histogram +system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 157 # Total snoops (count) +system.membus.snoop_fanout::samples 562136 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 562136 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562134 # Request fanout histogram -system.membus.reqLayer0.occupancy 11832500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 562136 # Request fanout histogram +system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 654960000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 770434435 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 438835201 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17654500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17657500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063004 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062983 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835667 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17024 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 48 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 57 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302779 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302779 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2063715 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2063694 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835707 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 42 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302749 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302749 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3656818 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5586831 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61758720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142717704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204476424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930984 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657230 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5588214 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61790208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3236018 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012894 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112817 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3236737 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012895 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112822 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3194293 98.71% 98.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3194999 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 41738 1.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3236018 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2201638999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3236737 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2030846564 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2289452792 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 689338845 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 790311532 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |