diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt | 3090 |
1 files changed, 1549 insertions, 1541 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 8f58e32e6..54688b406 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841615 # Number of seconds simulated -sim_ticks 1841615117500 # Number of ticks simulated -final_tick 1841615117500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.843590 # Number of seconds simulated +sim_ticks 1843589966000 # Number of ticks simulated +final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220643 # Simulator instruction rate (inst/s) -host_op_rate 220643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5550131764 # Simulator tick rate (ticks/s) -host_mem_usage 377148 # Number of bytes of host memory used -host_seconds 331.81 # Real time elapsed on the host -sim_insts 73212541 # Number of instructions simulated -sim_ops 73212541 # Number of ops (including micro ops) simulated +host_inst_rate 220463 # Simulator instruction rate (inst/s) +host_op_rate 220463 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5656183181 # Simulator tick rate (ticks/s) +host_mem_usage 378132 # Number of bytes of host memory used +host_seconds 325.94 # Real time elapsed on the host +sim_insts 71858146 # Number of instructions simulated +sim_ops 71858146 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 495296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20794752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 141504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1560960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 279936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2513472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 498752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20812864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 142016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1542016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 270784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2513856 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25786880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 495296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 141504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 279936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 916736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7468864 # Number of bytes written to this memory -system.physmem.bytes_written::total 7468864 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 324918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24390 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4374 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39273 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25781248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 498752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 142016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 270784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 911552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7470272 # Number of bytes written to this memory +system.physmem.bytes_written::total 7470272 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 325201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39279 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 268947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 11291584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 847604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 152006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1364819 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116723 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116723 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 270533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 11289313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 836420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 146879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1363566 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14002318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 268947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 152006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 497789 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4055605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4055605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4055605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 268947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 11291584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 847604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 152006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1364819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13984264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 270533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 146879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494444 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4052025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4052025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 270533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 11289313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 836420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 146879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1363566 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18057923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 70263 # Number of read requests accepted -system.physmem.writeReqs 43985 # Number of write requests accepted -system.physmem.readBursts 70263 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 43985 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 4495872 # Total number of bytes read from DRAM +system.physmem.bw_total::total 18036288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 69838 # Number of read requests accepted +system.physmem.writeReqs 42816 # Number of write requests accepted +system.physmem.readBursts 69838 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 42816 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 4468672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue -system.physmem.bytesWritten 2813888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 4496832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2815040 # Total written bytes from the system interface side +system.physmem.bytesWritten 2738752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 4469632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2740224 # Total written bytes from the system interface side system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 17213 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4359 # Per bank write bursts -system.physmem.perBankRdBursts::1 4121 # Per bank write bursts -system.physmem.perBankRdBursts::2 4307 # Per bank write bursts -system.physmem.perBankRdBursts::3 4650 # Per bank write bursts -system.physmem.perBankRdBursts::4 3946 # Per bank write bursts -system.physmem.perBankRdBursts::5 4779 # Per bank write bursts -system.physmem.perBankRdBursts::6 4258 # Per bank write bursts -system.physmem.perBankRdBursts::7 4152 # Per bank write bursts -system.physmem.perBankRdBursts::8 4721 # Per bank write bursts -system.physmem.perBankRdBursts::9 4422 # Per bank write bursts -system.physmem.perBankRdBursts::10 4675 # Per bank write bursts -system.physmem.perBankRdBursts::11 4103 # Per bank write bursts -system.physmem.perBankRdBursts::12 4083 # Per bank write bursts -system.physmem.perBankRdBursts::13 4580 # Per bank write bursts -system.physmem.perBankRdBursts::14 4738 # Per bank write bursts -system.physmem.perBankRdBursts::15 4354 # Per bank write bursts -system.physmem.perBankWrBursts::0 2794 # Per bank write bursts -system.physmem.perBankWrBursts::1 2415 # Per bank write bursts -system.physmem.perBankWrBursts::2 2758 # Per bank write bursts -system.physmem.perBankWrBursts::3 3153 # Per bank write bursts -system.physmem.perBankWrBursts::4 2458 # Per bank write bursts -system.physmem.perBankWrBursts::5 2922 # Per bank write bursts -system.physmem.perBankWrBursts::6 2626 # Per bank write bursts -system.physmem.perBankWrBursts::7 2424 # Per bank write bursts -system.physmem.perBankWrBursts::8 3273 # Per bank write bursts -system.physmem.perBankWrBursts::9 2590 # Per bank write bursts -system.physmem.perBankWrBursts::10 2930 # Per bank write bursts -system.physmem.perBankWrBursts::11 2458 # Per bank write bursts -system.physmem.perBankWrBursts::12 2433 # Per bank write bursts -system.physmem.perBankWrBursts::13 2833 # Per bank write bursts -system.physmem.perBankWrBursts::14 3042 # Per bank write bursts -system.physmem.perBankWrBursts::15 2858 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 59609 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4348 # Per bank write bursts +system.physmem.perBankRdBursts::1 4129 # Per bank write bursts +system.physmem.perBankRdBursts::2 4337 # Per bank write bursts +system.physmem.perBankRdBursts::3 4598 # Per bank write bursts +system.physmem.perBankRdBursts::4 3888 # Per bank write bursts +system.physmem.perBankRdBursts::5 4661 # Per bank write bursts +system.physmem.perBankRdBursts::6 4236 # Per bank write bursts +system.physmem.perBankRdBursts::7 4148 # Per bank write bursts +system.physmem.perBankRdBursts::8 4711 # Per bank write bursts +system.physmem.perBankRdBursts::9 4417 # Per bank write bursts +system.physmem.perBankRdBursts::10 4595 # Per bank write bursts +system.physmem.perBankRdBursts::11 4084 # Per bank write bursts +system.physmem.perBankRdBursts::12 4057 # Per bank write bursts +system.physmem.perBankRdBursts::13 4571 # Per bank write bursts +system.physmem.perBankRdBursts::14 4705 # Per bank write bursts +system.physmem.perBankRdBursts::15 4338 # Per bank write bursts +system.physmem.perBankWrBursts::0 2799 # Per bank write bursts +system.physmem.perBankWrBursts::1 2436 # Per bank write bursts +system.physmem.perBankWrBursts::2 2776 # Per bank write bursts +system.physmem.perBankWrBursts::3 2976 # Per bank write bursts +system.physmem.perBankWrBursts::4 2273 # Per bank write bursts +system.physmem.perBankWrBursts::5 2670 # Per bank write bursts +system.physmem.perBankWrBursts::6 2480 # Per bank write bursts +system.physmem.perBankWrBursts::7 2289 # Per bank write bursts +system.physmem.perBankWrBursts::8 3133 # Per bank write bursts +system.physmem.perBankWrBursts::9 2510 # Per bank write bursts +system.physmem.perBankWrBursts::10 2861 # Per bank write bursts +system.physmem.perBankWrBursts::11 2441 # Per bank write bursts +system.physmem.perBankWrBursts::12 2439 # Per bank write bursts +system.physmem.perBankWrBursts::13 2832 # Per bank write bursts +system.physmem.perBankWrBursts::14 3033 # Per bank write bursts +system.physmem.perBankWrBursts::15 2845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 1840603135000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 1842578089000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 70263 # Read request sizes (log2) +system.physmem.readPktSize::6 69838 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 43985 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 42816 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,195 +153,199 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 1909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.690812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 203.028180 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 371.433574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7252 35.78% 35.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4628 22.84% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1637 8.08% 66.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 935 4.61% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 704 3.47% 74.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 532 2.63% 77.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 447 2.21% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 402 1.98% 81.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3729 18.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20266 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1889 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.186342 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 837.829732 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 1887 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.185887 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.348650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 370.654869 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7177 35.77% 35.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4604 22.94% 58.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1640 8.17% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 939 4.68% 71.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 711 3.54% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 484 2.41% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 449 2.24% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 396 1.97% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3666 18.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20066 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.694924 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 845.707060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1850 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1889 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.275278 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.746797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.833114 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.80% 1.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.48% 2.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.11% 2.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.11% 2.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1521 80.52% 83.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51 2.70% 85.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 9 0.48% 86.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 92 4.87% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.11% 91.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 5 0.26% 91.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.90% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.64% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.42% 93.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.05% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.11% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.16% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.11% 93.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.21% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.53% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 16 0.85% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 73 3.86% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.05% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.11% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 6 0.32% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.11% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1889 # Writes before turning the bus around for reads -system.physmem.totQLat 866118250 # Total ticks spent queuing -system.physmem.totMemAccLat 2183268250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 351240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12329.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 1852 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.106371 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.632339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.643623 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.84% 1.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.38% 2.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.22% 2.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 3 0.16% 2.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1503 81.16% 83.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 52 2.81% 86.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 11 0.59% 87.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 74 4.00% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.22% 91.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 8 0.43% 91.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.92% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.43% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.38% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.05% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.16% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.43% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.43% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.05% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 15 0.81% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.05% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 66 3.56% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.05% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 2 0.11% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.11% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.16% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1852 # Writes before turning the bus around for reads +system.physmem.totQLat 871326250 # Total ticks spent queuing +system.physmem.totMemAccLat 2180507500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 349115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12479.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31079.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31229.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.98 # Average write queue length when enqueuing -system.physmem.readRowHits 59265 # Number of row buffer hits during reads -system.physmem.writeRowHits 34684 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.85 # Row buffer hit rate for writes -system.physmem.avgGap 16110593.93 # Average gap between requests -system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75993120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 41365500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 269661600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 139644000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36119290320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 800836482750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 926543498730 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.762999 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1308404512000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45532240000 # Time in different power states +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.08 # Average write queue length when enqueuing +system.physmem.readRowHits 58948 # Number of row buffer hits during reads +system.physmem.writeRowHits 33602 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.48 # Row buffer hit rate for writes +system.physmem.avgGap 16356082.24 # Average gap between requests +system.physmem.pageHitRate 82.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75161520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 40936500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 267891000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 134129520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 36125026515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 799629184500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 925463073795 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.948938 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1310373436000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9805597500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9753765000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 77217840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41955375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 278272800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 145262160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35704397295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 801349556250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 926657723160 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.725709 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1308993682000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45532240000 # Time in different power states +system.physmem_1.actEnergy 76537440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41650125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 276728400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 143169120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35621035650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799049139750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 924399004725 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.002289 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1311095993000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9217388750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9016803000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4860395 # DTB read hits -system.cpu0.dtb.read_misses 6162 # DTB read misses +system.cpu0.dtb.read_hits 4864865 # DTB read hits +system.cpu0.dtb.read_misses 6190 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428546 # DTB read accesses -system.cpu0.dtb.write_hits 3431856 # DTB write hits -system.cpu0.dtb.write_misses 685 # DTB write misses +system.cpu0.dtb.read_accesses 429298 # DTB read accesses +system.cpu0.dtb.write_hits 3435007 # DTB write hits +system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 164529 # DTB write accesses -system.cpu0.dtb.data_hits 8292251 # DTB hits -system.cpu0.dtb.data_misses 6847 # DTB misses +system.cpu0.dtb.write_accesses 165213 # DTB write accesses +system.cpu0.dtb.data_hits 8299872 # DTB hits +system.cpu0.dtb.data_misses 6878 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 593075 # DTB accesses -system.cpu0.itb.fetch_hits 2736971 # ITB hits -system.cpu0.itb.fetch_misses 3081 # ITB misses +system.cpu0.dtb.data_accesses 594511 # DTB accesses +system.cpu0.itb.fetch_hits 2740787 # ITB hits +system.cpu0.itb.fetch_misses 3088 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2740052 # ITB accesses +system.cpu0.itb.fetch_accesses 2743875 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -354,87 +358,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 927057463 # number of cpu cycles simulated +system.cpu0.numCycles 928566651 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31701170 # Number of instructions committed -system.cpu0.committedOps 31701170 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29591762 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 163845 # Number of float alu accesses -system.cpu0.num_func_calls 797475 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4044448 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29591762 # number of integer instructions -system.cpu0.num_fp_insts 163845 # number of float instructions -system.cpu0.num_int_register_reads 41150829 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21753171 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84843 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86199 # number of times the floating registers were written -system.cpu0.num_mem_refs 8322031 # number of memory refs -system.cpu0.num_load_insts 4881580 # Number of load instructions -system.cpu0.num_store_insts 3440451 # Number of store instructions -system.cpu0.num_idle_cycles 904905994.152015 # Number of idle cycles -system.cpu0.num_busy_cycles 22151468.847985 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023894 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976106 # Percentage of idle cycles -system.cpu0.Branches 5099323 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1600258 5.05% 5.05% # Class of executed instruction -system.cpu0.op_class::IntAlu 21086062 66.50% 71.55% # Class of executed instruction -system.cpu0.op_class::IntMult 31841 0.10% 71.65% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12946 0.04% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1618 0.01% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 5012305 15.81% 87.50% # Class of executed instruction -system.cpu0.op_class::MemWrite 3443548 10.86% 98.36% # Class of executed instruction -system.cpu0.op_class::IprAccess 519649 1.64% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31708227 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211399 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211440 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818498105000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39129500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 356633500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22720515500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841614383500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1820420159000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39420000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 369089000 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22760564000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1843589232000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -473,451 +422,508 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192207 # number of callpals executed +system.cpu0.kern.callpal::total 192243 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 169 system.cpu0.kern.mode_switch_good::kernel 0.322243 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29940410000 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2625898500 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809048073000 98.23% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29996442500 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2592008500 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1811000779000 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393243 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13232435 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393755 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.494090 # Average number of references to valid blocks. +system.cpu0.committedInsts 32582067 # Number of instructions committed +system.cpu0.committedOps 32582067 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30467910 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163902 # Number of float alu accesses +system.cpu0.num_func_calls 798063 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4326151 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30467910 # number of integer instructions +system.cpu0.num_fp_insts 163902 # number of float instructions +system.cpu0.num_int_register_reads 42599897 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22343202 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84869 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86282 # number of times the floating registers were written +system.cpu0.num_mem_refs 8329685 # number of memory refs +system.cpu0.num_load_insts 4886081 # Number of load instructions +system.cpu0.num_store_insts 3443604 # Number of store instructions +system.cpu0.num_idle_cycles 904742998.483282 # Number of idle cycles +system.cpu0.num_busy_cycles 23823652.516718 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025656 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974344 # Percentage of idle cycles +system.cpu0.Branches 5381713 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1604740 4.92% 4.92% # Class of executed instruction +system.cpu0.op_class::IntAlu 21953707 67.37% 72.29% # Class of executed instruction +system.cpu0.op_class::IntMult 32143 0.10% 72.39% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.39% # Class of executed instruction +system.cpu0.op_class::FloatAdd 13006 0.04% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1630 0.01% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::MemRead 5016903 15.39% 87.83% # Class of executed instruction +system.cpu0.op_class::MemWrite 3446713 10.58% 98.40% # Class of executed instruction +system.cpu0.op_class::IprAccess 520313 1.60% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 32589155 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1393262 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13241810 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393774 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.500687 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 242.565333 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 83.938780 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 185.493697 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.473760 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.163943 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.362292 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.746834 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216845 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034134 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497552 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236752 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265692 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63378181 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63378181 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4021743 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1010855 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2545337 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7577935 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3142602 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 763669 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1364636 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5270907 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114486 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18184 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51520 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184190 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123337 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20114 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55874 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199325 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7164345 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1774524 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3909973 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12848842 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7164345 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1774524 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3909973 # number of overall hits -system.cpu0.dcache.overall_hits::total 12848842 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 725431 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 86189 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 553303 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1364923 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 164575 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 38232 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 676790 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 879597 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9407 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2049 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7768 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19224 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63387052 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63387052 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4025112 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1019452 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2537983 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7582547 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3145682 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 772489 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1357389 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275560 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114073 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19050 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51169 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184292 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122917 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21014 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55400 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199331 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7170794 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1791941 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3895372 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12858107 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7170794 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1791941 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3895372 # number of overall hits +system.cpu0.dcache.overall_hits::total 12858107 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 726690 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 86798 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 548610 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1362098 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 165054 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 38388 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 671853 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 875295 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9398 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2090 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7704 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19192 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 890006 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 124421 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1230093 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2244520 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 890006 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 124421 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1230093 # number of overall misses -system.cpu0.dcache.overall_misses::total 2244520 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2328658500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8887314500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11215973000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2137506500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29622827624 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 31760334124 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27247000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 151557500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 178804500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 125000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 125000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4466165000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 38510142124 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42976307124 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4466165000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 38510142124 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42976307124 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4747174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1097044 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3098640 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8942858 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3307177 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 801901 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2041426 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6150504 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123893 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20233 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 59288 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203414 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55878 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199330 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8054351 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1898945 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5140066 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15093362 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8054351 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1898945 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5140066 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15093362 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.152813 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.078565 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.178563 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152627 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049763 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047677 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331528 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.143012 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075928 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101270 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.131021 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094507 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 891744 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 125186 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1220463 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2237393 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 891744 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 125186 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1220463 # number of overall misses +system.cpu0.dcache.overall_misses::total 2237393 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2310299500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8894370000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11204669500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2132273000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29520003133 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 31652276133 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27861500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 150264500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 178126000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 111000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 111000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4442572500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 38414373133 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 42856945633 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4442572500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 38414373133 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 42856945633 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4751802 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1106250 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3086593 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8944645 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3310736 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 810877 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2029242 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6150855 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123471 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21140 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58873 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203484 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122918 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21014 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55403 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199335 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8062538 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 1917127 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5115835 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15095500 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8062538 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 1917127 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5115835 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15095500 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.152929 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.078461 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.177740 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152281 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049854 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047341 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331086 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.142305 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076115 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.098865 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130858 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094317 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000072 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000025 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110500 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065521 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.239315 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.148709 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110500 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065521 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.239315 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.148709 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 27018.047547 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16062.292270 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8217.293576 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55908.832915 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43769.600059 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36107.824520 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13297.706198 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19510.491761 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9301.107990 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 31250 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35895.588365 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31306.691546 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19147.215050 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35895.588365 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31306.691546 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19147.215050 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1653965 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2392 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 59941 # number of cycles access was blocked +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110603 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065299 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.238566 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.148216 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110603 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065299 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.238566 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.148216 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26616.966981 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16212.555367 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8226.037701 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55545.300615 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43938.187569 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 36161.838161 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13330.861244 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19504.737799 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9281.263026 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 37000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27750 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35487.774192 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31475.245979 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19154.858191 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35487.774192 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31475.245979 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19154.858191 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1652146 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2580 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 59796 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.593217 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 199.333333 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.629708 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 215 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835815 # number of writebacks -system.cpu0.dcache.writebacks::total 835815 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 291179 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 291179 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 576940 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 576940 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 835859 # number of writebacks +system.cpu0.dcache.writebacks::total 835859 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 288357 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 288357 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 572581 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 572581 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1582 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1582 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 868119 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 868119 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 868119 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 868119 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 262124 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 348313 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38232 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99850 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 138082 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2049 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6186 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8235 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 124421 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 361974 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 486395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 124421 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 361974 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 486395 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1341 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1578 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2919 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1620 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 1904 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3524 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2961 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3482 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6443 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2242469500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4680386500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6922856000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2099274500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4628925917 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6728200417 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25198000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77699000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102897000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 121000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 121000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4341744000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9309312417 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13651056417 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4341744000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9309312417 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13651056417 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 280410000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 323287500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 603697500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 352231500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 401647500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 753879000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 632641500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 724935000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1357576500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078565 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084593 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038949 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047677 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048912 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022451 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101270 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.104338 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040484 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000072 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070422 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032226 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070422 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032226 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 26018.047547 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17855.619859 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19875.387941 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54908.832915 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46358.797366 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.122282 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12297.706198 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12560.459101 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12495.081967 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 30250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34895.588365 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25718.179806 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28065.782784 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34895.588365 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25718.179806 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28065.782784 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 209105.145414 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 204871.673004 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206816.546763 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 217426.851852 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 210949.317227 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213927.071510 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 213658.054711 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 208195.002872 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210705.649542 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_hits::cpu2.data 860938 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 860938 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 860938 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 860938 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86798 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 260253 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 347051 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38388 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99272 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137660 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2090 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6122 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8212 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 125186 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 359525 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484711 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 125186 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 359525 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484711 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2652 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1618 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 1898 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3516 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223501500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676661000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6900162500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2093885000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4616741882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6710626882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25771500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103207500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 108000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 108000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4317386500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9293402882 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13610789382 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4317386500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9293402882 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13610789382 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 293417500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 298094000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591511500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372514000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 424017500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796531500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665931500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 722111500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388043000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078461 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084317 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048921 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022381 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.098865 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103987 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25616.966981 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17969.671819 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19882.272346 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54545.300615 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46505.982372 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48747.834389 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.807579 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.888456 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 36000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230231.149567 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226544.795222 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225969.290804 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.396887 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 964359 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.170929 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 40638696 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 964870 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.118312 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10553576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 255.050326 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 76.933985 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 179.186618 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.498145 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.150262 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.349974 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998381 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 963474 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.175730 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41537475 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 963985 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 43.089337 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10558559500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250464 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956509 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.968757 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.510255 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160071 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328064 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998390 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42585531 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42585531 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31196035 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7004527 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2438134 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 40638696 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31196035 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7004527 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2438134 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 40638696 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31196035 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7004527 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2438134 # number of overall hits -system.cpu0.icache.overall_hits::total 40638696 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 512192 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 123075 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 346520 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 981787 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 512192 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 123075 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 346520 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 981787 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 512192 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 123075 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 346520 # number of overall misses -system.cpu0.icache.overall_misses::total 981787 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1869616000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5082111473 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6951727473 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1869616000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5082111473 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6951727473 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1869616000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5082111473 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6951727473 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 31708227 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7127602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2784654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41620483 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 31708227 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7127602 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2784654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41620483 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 31708227 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7127602 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2784654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41620483 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016153 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.017267 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.124439 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023589 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016153 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.017267 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.124439 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023589 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016153 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017267 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.124439 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023589 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15190.867357 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14666.141848 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7080.688044 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15190.867357 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14666.141848 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7080.688044 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15190.867357 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14666.141848 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7080.688044 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7863 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43482483 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43482483 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 32077013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7031290 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2429172 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41537475 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32077013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7031290 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2429172 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41537475 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32077013 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7031290 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2429172 # number of overall hits +system.cpu0.icache.overall_hits::total 41537475 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 512142 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 125208 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 343493 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 980843 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 512142 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 125208 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 343493 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 980843 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 512142 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 125208 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 343493 # number of overall misses +system.cpu0.icache.overall_misses::total 980843 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1899043000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5060933969 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6959976969 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1899043000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5060933969 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6959976969 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1899043000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5060933969 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6959976969 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32589155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7156498 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2772665 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42518318 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32589155 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7156498 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2772665 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42518318 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32589155 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7156498 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2772665 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42518318 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015715 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.017496 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.123886 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023069 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015715 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.017496 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.123886 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023069 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015715 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017496 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.123886 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023069 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15167.105936 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14733.732475 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7095.913382 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15167.105936 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14733.732475 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7095.913382 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15167.105936 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14733.732475 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7095.913382 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8552 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 357 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.058651 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.955182 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16739 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16739 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16739 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16739 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16739 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16739 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 123075 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329781 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 452856 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 123075 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 329781 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 452856 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 123075 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 329781 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 452856 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1746541000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4501465478 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6248006478 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1746541000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4501465478 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6248006478 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1746541000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4501465478 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6248006478 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010881 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010881 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010881 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13796.894549 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13796.894549 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13796.894549 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 963474 # number of writebacks +system.cpu0.icache.writebacks::total 963474 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16678 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16678 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16678 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16678 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16678 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16678 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 125208 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326815 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 452023 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 125208 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 326815 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 452023 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 125208 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 326815 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 452023 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1773835000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4488659473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6262494473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1773835000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4488659473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6262494473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1773835000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4488659473 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6262494473 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010631 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010631 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010631 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13854.371289 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13854.371289 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13854.371289 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1115382 # DTB read hits -system.cpu1.dtb.read_misses 1270 # DTB read misses -system.cpu1.dtb.read_acv 33 # DTB read access violations -system.cpu1.dtb.read_accesses 123322 # DTB read accesses -system.cpu1.dtb.write_hits 822469 # DTB write hits +system.cpu1.dtb.read_hits 1125427 # DTB read hits +system.cpu1.dtb.read_misses 1262 # DTB read misses +system.cpu1.dtb.read_acv 31 # DTB read access violations +system.cpu1.dtb.read_accesses 117717 # DTB read accesses +system.cpu1.dtb.write_hits 832316 # DTB write hits system.cpu1.dtb.write_misses 154 # DTB write misses system.cpu1.dtb.write_acv 18 # DTB write access violations -system.cpu1.dtb.write_accesses 50514 # DTB write accesses -system.cpu1.dtb.data_hits 1937851 # DTB hits -system.cpu1.dtb.data_misses 1424 # DTB misses -system.cpu1.dtb.data_acv 51 # DTB access violations -system.cpu1.dtb.data_accesses 173836 # DTB accesses -system.cpu1.itb.fetch_hits 768661 # ITB hits +system.cpu1.dtb.write_accesses 48434 # DTB write accesses +system.cpu1.dtb.data_hits 1957743 # DTB hits +system.cpu1.dtb.data_misses 1416 # DTB misses +system.cpu1.dtb.data_acv 49 # DTB access violations +system.cpu1.dtb.data_accesses 166151 # DTB accesses +system.cpu1.itb.fetch_hits 753702 # ITB hits system.cpu1.itb.fetch_misses 636 # ITB misses system.cpu1.itb.fetch_acv 28 # ITB acv -system.cpu1.itb.fetch_accesses 769297 # ITB accesses +system.cpu1.itb.fetch_accesses 754338 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -930,64 +936,9 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953409174 # number of cpu cycles simulated +system.cpu1.numCycles 953452897 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7126126 # Number of instructions committed -system.cpu1.committedOps 7126126 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6614481 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 39892 # Number of float alu accesses -system.cpu1.num_func_calls 202987 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 849967 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6614481 # number of integer instructions -system.cpu1.num_fp_insts 39892 # number of float instructions -system.cpu1.num_int_register_reads 9205425 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4843983 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 21026 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21409 # number of times the floating registers were written -system.cpu1.num_mem_refs 1944596 # number of memory refs -system.cpu1.num_load_insts 1119921 # Number of load instructions -system.cpu1.num_store_insts 824675 # Number of store instructions -system.cpu1.num_idle_cycles 926242764.786654 # Number of idle cycles -system.cpu1.num_busy_cycles 27166409.213346 # Number of busy cycles -system.cpu1.not_idle_fraction 0.028494 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.971506 # Percentage of idle cycles -system.cpu1.Branches 1116663 # Number of branches fetched -system.cpu1.op_class::No_OpClass 388723 5.45% 5.45% # Class of executed instruction -system.cpu1.op_class::IntAlu 4626654 64.91% 70.37% # Class of executed instruction -system.cpu1.op_class::IntMult 7726 0.11% 70.47% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.47% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3756 0.05% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatDiv 538 0.01% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::MemRead 1147644 16.10% 86.64% # Class of executed instruction -system.cpu1.op_class::MemWrite 825879 11.59% 98.22% # Class of executed instruction -system.cpu1.op_class::IprAccess 126681 1.78% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7127601 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1005,35 +956,90 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 11557403 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10821969 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 122344 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 9245404 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 7393469 # Number of BTB hits +system.cpu1.committedInsts 7155032 # Number of instructions committed +system.cpu1.committedOps 7155032 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6639972 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 39507 # Number of float alu accesses +system.cpu1.num_func_calls 205327 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 849342 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6639972 # number of integer instructions +system.cpu1.num_fp_insts 39507 # number of float instructions +system.cpu1.num_int_register_reads 9236476 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4860513 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 20546 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21005 # number of times the floating registers were written +system.cpu1.num_mem_refs 1964570 # number of memory refs +system.cpu1.num_load_insts 1130012 # Number of load instructions +system.cpu1.num_store_insts 834558 # Number of store instructions +system.cpu1.num_idle_cycles 924897585.359422 # Number of idle cycles +system.cpu1.num_busy_cycles 28555311.640577 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029949 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970051 # Percentage of idle cycles +system.cpu1.Branches 1119214 # Number of branches fetched +system.cpu1.op_class::No_OpClass 390317 5.45% 5.45% # Class of executed instruction +system.cpu1.op_class::IntAlu 4631234 64.71% 70.17% # Class of executed instruction +system.cpu1.op_class::IntMult 7711 0.11% 70.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3307 0.05% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatDiv 440 0.01% 70.33% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::MemRead 1158585 16.19% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 835763 11.68% 98.20% # Class of executed instruction +system.cpu1.op_class::IprAccess 129140 1.80% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 7156497 # Class of executed instruction +system.cpu2.branchPred.lookups 10791906 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10058996 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 121698 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8434906 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6656118 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.969128 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 299976 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7838 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 78.911585 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 298697 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7721 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3543723 # DTB read hits -system.cpu2.dtb.read_misses 12250 # DTB read misses -system.cpu2.dtb.read_acv 123 # DTB read access violations -system.cpu2.dtb.read_accesses 249931 # DTB read accesses -system.cpu2.dtb.write_hits 2185333 # DTB write hits -system.cpu2.dtb.write_misses 2753 # DTB write misses -system.cpu2.dtb.write_acv 125 # DTB write access violations -system.cpu2.dtb.write_accesses 92110 # DTB write accesses -system.cpu2.dtb.data_hits 5729056 # DTB hits -system.cpu2.dtb.data_misses 15003 # DTB misses -system.cpu2.dtb.data_acv 248 # DTB access violations -system.cpu2.dtb.data_accesses 342041 # DTB accesses -system.cpu2.itb.fetch_hits 552866 # ITB hits -system.cpu2.itb.fetch_misses 5354 # ITB misses -system.cpu2.itb.fetch_acv 182 # ITB acv -system.cpu2.itb.fetch_accesses 558220 # ITB accesses +system.cpu2.dtb.read_hits 3520448 # DTB read hits +system.cpu2.dtb.read_misses 12146 # DTB read misses +system.cpu2.dtb.read_acv 125 # DTB read access violations +system.cpu2.dtb.read_accesses 256305 # DTB read accesses +system.cpu2.dtb.write_hits 2173477 # DTB write hits +system.cpu2.dtb.write_misses 2690 # DTB write misses +system.cpu2.dtb.write_acv 124 # DTB write access violations +system.cpu2.dtb.write_accesses 93625 # DTB write accesses +system.cpu2.dtb.data_hits 5693925 # DTB hits +system.cpu2.dtb.data_misses 14836 # DTB misses +system.cpu2.dtb.data_acv 249 # DTB access violations +system.cpu2.dtb.data_accesses 349930 # DTB accesses +system.cpu2.itb.fetch_hits 553155 # ITB hits +system.cpu2.itb.fetch_misses 5226 # ITB misses +system.cpu2.itb.fetch_acv 187 # ITB acv +system.cpu2.itb.fetch_accesses 558381 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1046,304 +1052,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 33083271 # number of cpu cycles simulated +system.cpu2.numCycles 32236279 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9301099 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 42932048 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 11557403 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 7693445 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 21583805 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 404638 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 962 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10456 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1990 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 197395 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 92170 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2784665 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90858 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 31390787 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.367664 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.311444 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9243840 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40617547 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10791906 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6954815 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20753592 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 401538 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 916 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10212 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2008 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 193151 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 89388 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1068 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2772679 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90084 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 30494706 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.331954 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.325119 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 21183291 67.48% 67.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 297740 0.95% 68.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 468841 1.49% 69.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5764163 18.36% 88.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 882544 2.81% 91.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 193394 0.62% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 232558 0.74% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 434405 1.38% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1933851 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 21037778 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 294298 0.97% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 469114 1.54% 71.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5033169 16.51% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 879924 2.89% 90.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194801 0.64% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 230028 0.75% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433107 1.42% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1922487 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 31390787 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.349343 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.297697 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7618981 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 14231209 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8576643 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 528584 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 189420 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 174742 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13252 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 39552027 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 41601 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 189420 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7898470 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4727919 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6647041 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8797977 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2884017 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 38737545 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 58522 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 372966 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 93481 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1809588 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 25849349 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 48570643 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 48506980 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 59488 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 23977354 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1871995 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 535640 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63418 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3866497 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3518835 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2279192 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 461417 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 331685 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 36218811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 686292 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 35933838 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15798 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2519858 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1130776 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 490718 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 31390787 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.144726 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.617565 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30494706 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.334775 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.259995 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7573321 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 14126025 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7836977 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 524605 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 187915 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 174630 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13216 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37265458 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 41467 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 187915 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7850244 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4676437 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6613578 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8057400 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2863279 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 36458401 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 57802 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 368784 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 93789 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1799072 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 24336413 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 45554095 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 45489801 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 60051 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22465786 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1870627 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 531021 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 62908 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3828322 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3503706 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2266582 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 453499 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 325031 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33954893 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 679527 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 33661057 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16143 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2513373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1127788 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 486024 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30494706 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.103833 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.612725 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18577248 59.18% 59.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2723782 8.68% 67.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1358088 4.33% 72.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 6489843 20.67% 92.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1045865 3.33% 96.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 589790 1.88% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 396015 1.26% 99.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 165397 0.53% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44759 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18452821 60.51% 60.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2702851 8.86% 69.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1349809 4.43% 73.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5753089 18.87% 92.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1041578 3.42% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 588420 1.93% 98.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 396893 1.30% 99.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 164409 0.54% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44836 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 31390787 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30494706 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 81235 20.78% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 183347 46.90% 67.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126357 32.32% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 81527 21.02% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179819 46.37% 67.39% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126481 32.61% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2960 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 29699192 82.65% 82.66% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21615 0.06% 82.72% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 21814 0.06% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1480 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3672081 10.22% 93.00% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2209398 6.15% 99.15% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 305298 0.85% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 3131 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27465013 81.59% 81.60% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21327 0.06% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 22209 0.07% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3648084 10.84% 92.57% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2197360 6.53% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 302367 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 35933838 # Type of FU issued -system.cpu2.iq.rate 1.086163 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 390939 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.010879 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 103401518 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39305388 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 35307106 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 263682 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 125410 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122335 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36181025 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 140792 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 202971 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 33661057 # Type of FU issued +system.cpu2.iq.rate 1.044198 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387827 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011522 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 97956454 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 37027606 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 33043548 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 264336 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 125822 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122705 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 33904668 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 141085 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 200240 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 432355 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1077 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5954 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178558 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 431120 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5749 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178621 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4490 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 225000 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4239 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 217381 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 189420 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4054480 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 208473 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 38277538 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51152 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3518835 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2279192 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 610930 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12812 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 160010 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5954 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 60508 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134714 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 35737943 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3564708 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 195895 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 187915 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4008679 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 205535 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35998675 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51747 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3503706 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2266582 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 605109 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12931 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 157162 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5749 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 59808 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134012 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193820 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33465262 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3541255 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 195795 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1372435 # number of nop insts executed -system.cpu2.iew.exec_refs 5757521 # number of memory reference insts executed -system.cpu2.iew.exec_branches 8471480 # Number of branches executed -system.cpu2.iew.exec_stores 2192813 # Number of stores executed -system.cpu2.iew.exec_rate 1.080242 # Inst execution rate -system.cpu2.iew.wb_sent 35472276 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 35429441 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 20887132 # num instructions producing a value -system.cpu2.iew.wb_consumers 24638595 # num instructions consuming a value +system.cpu2.iew.exec_nop 1364255 # number of nop insts executed +system.cpu2.iew.exec_refs 5722116 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7732316 # Number of branches executed +system.cpu2.iew.exec_stores 2180861 # Number of stores executed +system.cpu2.iew.exec_rate 1.038124 # Inst execution rate +system.cpu2.iew.wb_sent 33208664 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 33166253 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 19395256 # num instructions producing a value +system.cpu2.iew.wb_consumers 23138933 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.070917 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.847740 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.028849 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.838209 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2638965 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 195574 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 178349 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 30927462 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.150843 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846358 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2630446 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 193503 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 177071 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 30033551 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.109504 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.847540 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 19331784 62.51% 62.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2240622 7.24% 69.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1164134 3.76% 73.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6211408 20.08% 93.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 591221 1.91% 95.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 197085 0.64% 96.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 163594 0.53% 96.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 163249 0.53% 97.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 864365 2.79% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 19200071 63.93% 63.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2226295 7.41% 71.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1158853 3.86% 75.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5473619 18.23% 93.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 589521 1.96% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 197097 0.66% 96.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164200 0.55% 96.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 162437 0.54% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 861458 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 30927462 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 35592650 # Number of instructions committed -system.cpu2.commit.committedOps 35592650 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 30033551 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 33322350 # Number of instructions committed +system.cpu2.commit.committedOps 33322350 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5187114 # Number of memory references committed -system.cpu2.commit.loads 3086480 # Number of loads committed -system.cpu2.commit.membars 68869 # Number of memory barriers committed -system.cpu2.commit.branches 8299152 # Number of branches committed -system.cpu2.commit.fp_insts 120520 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 34085086 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241488 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1210365 3.40% 3.40% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 28775352 80.85% 84.25% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 21144 0.06% 84.31% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21379 0.06% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1480 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3155349 8.87% 93.24% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2102283 5.91% 99.14% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 305298 0.86% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5160547 # Number of memory references committed +system.cpu2.commit.loads 3072586 # Number of loads committed +system.cpu2.commit.membars 67946 # Number of memory barriers committed +system.cpu2.commit.branches 7560075 # Number of branches committed +system.cpu2.commit.fp_insts 120848 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31822701 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240099 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1204434 3.61% 3.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26541208 79.65% 83.26% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20874 0.06% 83.33% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21768 0.07% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3140532 9.42% 92.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2089601 6.27% 99.09% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 302367 0.91% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 35592650 # Class of committed instruction -system.cpu2.commit.bw_lim_events 864365 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 68219321 # The number of ROB reads -system.cpu2.rob.rob_writes 76925100 # The number of ROB writes -system.cpu2.timesIdled 177793 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1692484 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1742724515 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 34385245 # Number of Instructions Simulated -system.cpu2.committedOps 34385245 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.962136 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.962136 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.039354 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.039354 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 46956630 # number of integer regfile reads -system.cpu2.int_regfile_writes 24762728 # number of integer regfile writes -system.cpu2.fp_regfile_reads 74199 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74347 # number of floating regfile writes -system.cpu2.misc_regfile_reads 6109617 # number of misc regfile reads -system.cpu2.misc_regfile_writes 275370 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 33322350 # Class of committed instruction +system.cpu2.commit.bw_lim_events 861458 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 65049813 # The number of ROB reads +system.cpu2.rob.rob_writes 72365341 # The number of ROB writes +system.cpu2.timesIdled 178213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1741573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747477665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 32121047 # Number of Instructions Simulated +system.cpu2.committedOps 32121047 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.003587 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.003587 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.996425 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.996425 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 43934131 # number of integer regfile reads +system.cpu2.int_regfile_writes 23251716 # number of integer regfile writes +system.cpu2.fp_regfile_reads 74710 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74652 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5374912 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272966 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1358,9 +1365,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51362 # Transaction distribution -system.iobus.trans_dist::WriteResp 51362 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51364 # Transaction distribution +system.iobus.trans_dist::WriteResp 51364 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5196 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1372,11 +1379,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1388,37 +1395,37 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45584 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2206000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2564500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 116500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 55500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5525000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2084000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2121000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 88878376 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 84230549 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9362000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17358000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16458000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254039 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261273 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693946387000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254039 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078377 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078377 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694926918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261273 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078830 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1432,14 +1439,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9722962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9722962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2243179414 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2243179414 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9722962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9722962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9722962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9722962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9458962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9458962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2126843587 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2126843587 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9458962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9458962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9458962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9458962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1456,266 +1463,270 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56202.092486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 56202.092486 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 53984.872305 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 53984.872305 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 56202.092486 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 56202.092486 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54676.080925 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54676.080925 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 51185.107504 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 51185.107504 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54676.080925 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54676.080925 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5.166667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 71 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17168 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 17168 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 71 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 71 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 71 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 71 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6172962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6172962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1384779414 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1384779414 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 6172962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6172962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 6172962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6172962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.410405 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.413169 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.413169 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.410405 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.410405 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 86943.126761 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80660.497088 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80660.497088 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 86943.126761 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 86943.126761 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16272 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 16272 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 69 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 69 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 69 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 69 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6008962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6008962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1313243587 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1313243587 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 6008962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6008962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 6008962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6008962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.391606 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.391606 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.398844 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.398844 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 87086.405797 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80705.726831 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80705.726831 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337421 # number of replacements -system.l2c.tags.tagsinuse 65422.020035 # Cycle average of tags in use -system.l2c.tags.total_refs 4006967 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402583 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.953145 # Average number of references to valid blocks. +system.l2c.tags.replacements 337614 # number of replacements +system.l2c.tags.tagsinuse 65425.004009 # Cycle average of tags in use +system.l2c.tags.total_refs 4005267 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402776 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.944155 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54749.853403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2632.785518 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2879.050483 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 437.699618 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 567.874446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2112.962465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2041.794102 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.040173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043931 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.006679 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008665 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032241 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.031155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998261 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54894.973613 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2664.591905 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2878.625445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 441.912379 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 553.808439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2003.360689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1987.731539 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837631 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.040658 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.006743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008450 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.030569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.030330 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998306 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 717 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6187 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2728 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55352 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 713 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2779 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55356 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38426412 # Number of tag accesses -system.l2c.tags.data_accesses 38426412 # Number of data accesses -system.l2c.Writeback_hits::writebacks 835815 # number of Writeback hits -system.l2c.Writeback_hits::total 835815 # number of Writeback hits +system.l2c.tags.tag_accesses 38412750 # Number of tag accesses +system.l2c.tags.data_accesses 38412750 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 835859 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 835859 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 963177 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 963177 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 90170 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 24197 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 72759 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187126 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 504433 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 120864 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 325383 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 950680 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 484059 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 77838 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 255762 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 817659 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 504433 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 574229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 120864 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 102035 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 325383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 328521 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955465 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 504433 # number of overall hits -system.l2c.overall_hits::cpu0.data 574229 # number of overall hits -system.l2c.overall_hits::cpu1.inst 120864 # number of overall hits -system.l2c.overall_hits::cpu1.data 102035 # number of overall hits -system.l2c.overall_hits::cpu2.inst 325383 # number of overall hits -system.l2c.overall_hits::cpu2.data 328521 # number of overall hits -system.l2c.overall_hits::total 1955465 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 90398 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 24435 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 72282 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187115 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 504328 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 122989 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 322557 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 949874 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 485259 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 78702 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 253717 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 817678 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 504328 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 575657 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 122989 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 103137 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 322557 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 325999 # number of demand (read+write) hits +system.l2c.demand_hits::total 1954667 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 504328 # number of overall hits +system.l2c.overall_hits::cpu0.data 575657 # number of overall hits +system.l2c.overall_hits::cpu1.inst 122989 # number of overall hits +system.l2c.overall_hits::cpu1.data 103137 # number of overall hits +system.l2c.overall_hits::cpu2.inst 322557 # number of overall hits +system.l2c.overall_hits::cpu2.data 325999 # number of overall hits +system.l2c.overall_hits::total 1954667 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 13 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 22 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 74394 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14034 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 27292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115720 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 7739 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 2211 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 4374 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 14324 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 250779 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 10400 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 12328 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 273507 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 7739 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 325173 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2211 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 24434 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4374 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 39620 # number of demand (read+write) misses -system.l2c.demand_misses::total 403551 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7739 # number of overall misses -system.l2c.overall_misses::cpu0.data 325173 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2211 # number of overall misses -system.l2c.overall_misses::cpu1.data 24434 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4374 # number of overall misses -system.l2c.overall_misses::cpu2.data 39620 # number of overall misses -system.l2c.overall_misses::total 403551 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu2.data 564500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 564500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_misses::cpu0.data 74645 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13952 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 27192 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115789 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 7793 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 2219 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 4231 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 14243 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 250829 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 10186 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 12435 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 273450 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 7793 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 325474 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2219 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 24138 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4231 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 39627 # number of demand (read+write) misses +system.l2c.demand_misses::total 403482 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7793 # number of overall misses +system.l2c.overall_misses::cpu0.data 325474 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2219 # number of overall misses +system.l2c.overall_misses::cpu1.data 24138 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4231 # number of overall misses +system.l2c.overall_misses::cpu2.data 39627 # number of overall misses +system.l2c.overall_misses::total 403482 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu2.data 574000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 574000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu2.data 80500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1787831500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 3697147500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5484979000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 292437000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 582353000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 874790000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 1317958500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 1536135500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 2854094000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 292437000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3105790000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 582353000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 5233283000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9213863000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 292437000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3105790000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 582353000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 5233283000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9213863000 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 835815 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835815 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::cpu1.data 1779331000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 3689980500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5469311500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 292933000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 566377000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 859310000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 1287928500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 1552705500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 2840634000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 292933000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3067259500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 566377000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 5242686000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9169255500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 292933000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3067259500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 566377000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 5242686000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9169255500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 835859 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 835859 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 963177 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 963177 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 33 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 23 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 35 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 164564 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 38231 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 100051 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302846 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 512172 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 123075 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 329757 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 965004 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 734838 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 88238 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 268090 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1091166 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 512172 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 899402 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 123075 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 126469 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 329757 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 368141 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2359016 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 512172 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 899402 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 123075 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 126469 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 329757 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 368141 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2359016 # number of overall (read+write) accesses +system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 165043 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 38387 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 99474 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302904 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 512121 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 125208 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 326788 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 964117 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 736088 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 88888 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 266152 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1091128 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 512121 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 901131 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 125208 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 127275 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 326788 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 365626 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2358149 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 512121 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 901131 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 125208 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 127275 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 326788 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 365626 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2358149 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.619048 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.636364 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.608696 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.628571 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.452067 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.367084 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.272781 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382108 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015110 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.017965 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.013264 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.014843 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.341271 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.117863 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.045985 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.250656 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015110 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.361544 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.017965 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.193201 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.013264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.107622 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171068 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015110 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.361544 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.017965 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.193201 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.013264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.107622 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171068 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 43423.076923 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 26880.952381 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.333333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.452276 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.363456 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.273358 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382263 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015217 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.017723 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.012947 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.014773 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.340760 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.114594 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.046721 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.250612 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015217 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.361184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.017723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.189652 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.012947 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.108381 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171101 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015217 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.361184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.017723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.189652 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.012947 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.108381 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171101 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 41000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 26090.909091 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 80500 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 40250 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127392.867322 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 135466.345449 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 47398.712409 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132264.586160 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133139.689072 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 61071.628037 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 126726.778846 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 124605.410448 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 10435.177162 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 132264.586160 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 127109.355816 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 133139.689072 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 132086.900555 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 22831.966715 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 132264.586160 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 127109.355816 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 133139.689072 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 132086.900555 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 22831.966715 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127532.325115 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 135700.959841 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 47235.156189 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132011.266336 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133863.625620 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 60332.092958 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 126441.046534 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 124865.741858 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 10388.129457 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 132011.266336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 127071.816223 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 133863.625620 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 132300.855477 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 22725.314884 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 132011.266336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 127071.816223 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 133863.625620 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 132300.855477 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 22725.314884 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1724,228 +1735,225 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75189 # number of writebacks -system.l2c.writebacks::total 75189 # number of writebacks -system.l2c.CleanEvict_mshr_misses::writebacks 181 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 181 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 13 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 75211 # number of writebacks +system.l2c.writebacks::total 75211 # number of writebacks +system.l2c.UpgradeReq_mshr_misses::cpu2.data 14 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 14034 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 27292 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 41326 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2211 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 4374 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 6585 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 10400 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12328 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 22728 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2211 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 24434 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4374 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 39620 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 70639 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2211 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 24434 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4374 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 39620 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 70639 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1341 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1578 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 2919 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1620 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 1904 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 3524 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2961 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3482 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 6443 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 922500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 922500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::cpu1.data 13952 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 27192 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 41144 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2219 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 4231 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 6450 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 10186 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12435 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 22621 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2219 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 24138 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4231 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 39627 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 70215 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2219 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 24138 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4231 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 39627 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 70215 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 2652 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1618 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 1898 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 3516 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 1004500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1004500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 70500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1647491500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3424227500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5071719000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 270327000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 538613000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 808940000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1213958500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1444189500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 2658148000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 270327000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2861450000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 538613000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 4868417000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8538807000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 270327000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2861450000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 538613000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 4868417000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8538807000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 263647500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 303562500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 567210000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 333601500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 379751500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 713353000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 597249000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 683314000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1280563000 # number of overall MSHR uncacheable cycles -system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.619048 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.393939 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.367084 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.272781 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.136459 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006824 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.117863 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.045985 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020829 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.193201 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.107622 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.029944 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.193201 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.107622 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.029944 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70961.538462 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1639811000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3418060500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5057871500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 270743000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 524067000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 794810000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1186068500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1461566500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 2647635000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 270743000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2825879500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 524067000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 4879627000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8500316500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 270743000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2825879500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 524067000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 4879627000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8500316500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 276798000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 281540000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 558338000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 353898000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402187000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 756085000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 630696000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 683727000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1314423000 # number of overall MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.608696 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.363456 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.273358 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.135832 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006690 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.114594 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046721 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.029775 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.029775 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 71750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71750 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 70500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117392.867322 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125466.345449 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 122724.652761 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122845.861807 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116726.778846 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117147.104153 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116954.769447 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117109.355816 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122877.763756 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 120879.499993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117109.355816 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122877.763756 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 120879.499993 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196605.145414 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 192371.673004 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 194316.546763 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 205926.851852 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 199449.317227 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 202427.071510 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 201705.167173 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 196241.815049 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 198752.599721 # average overall mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117532.325115 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125700.959841 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 122930.961987 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123226.356589 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116441.046534 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117536.509851 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117043.234163 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208275.395034 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 212804.232804 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210534.690799 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218725.587145 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211900.421496 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215041.240046 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214012.894469 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212271.654766 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213103.599222 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294893 # Transaction distribution -system.membus.trans_dist::WriteReq 9810 # Transaction distribution -system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116701 # Transaction distribution -system.membus.trans_dist::CleanEvict 261800 # Transaction distribution -system.membus.trans_dist::UpgradeReq 141 # Transaction distribution +system.membus.trans_dist::ReadResp 294754 # Transaction distribution +system.membus.trans_dist::WriteReq 9812 # Transaction distribution +system.membus.trans_dist::WriteResp 9812 # Transaction distribution +system.membus.trans_dist::WritebackDirty 116723 # Transaction distribution +system.membus.trans_dist::CleanEvict 261691 # Transaction distribution +system.membus.trans_dist::UpgradeReq 160 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 143 # Transaction distribution -system.membus.trans_dist::ReadExReq 115600 # Transaction distribution -system.membus.trans_dist::ReadExResp 115600 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288004 # Transaction distribution -system.membus.trans_dist::BadAddressError 255 # Transaction distribution +system.membus.trans_dist::UpgradeResp 162 # Transaction distribution +system.membus.trans_dist::ReadExReq 115651 # Transaction distribution +system.membus.trans_dist::ReadExResp 115651 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287866 # Transaction distribution +system.membus.trans_dist::BadAddressError 256 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143509 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177927 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1302846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30608832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30654400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33318656 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 161 # Total snoops (count) -system.membus.snoop_fanout::samples 840917 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 512 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177708 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1302629 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30604608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30650192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33314576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 159 # Total snoops (count) +system.membus.snoop_fanout::samples 840768 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840917 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840768 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840917 # Request fanout histogram -system.membus.reqLayer0.occupancy 11282500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840768 # Request fanout histogram +system.membus.reqLayer0.occupancy 11147000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 355534840 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 348692458 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 348500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 377985955 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 375048955 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 28782491 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 27286702 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4716700 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2358029 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1601 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1128 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1128 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4714972 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2357166 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1129 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1129 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2063159 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 879803 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1563697 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 38 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302846 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302846 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 965048 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091237 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 255 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 17168 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2894139 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214034 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7108173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61761536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142741760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204503296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421014 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5154488 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.000869 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.029472 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2062235 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 878682 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 963177 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 599628 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 39 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302904 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302904 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 964165 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091197 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 256 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 16272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891480 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214095 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7105575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123348160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142745680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266093840 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421214 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4208473 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000983 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.031334 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5150007 99.91% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4481 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4204337 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4136 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5154488 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1335525500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4208473 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1783329500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 102462 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 99462 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 679735096 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 678448171 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 746367473 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 743541954 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |