diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt | 2179 |
1 files changed, 1086 insertions, 1093 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 190a0b7d0..1e558125c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,21 +4,21 @@ sim_seconds 1.843590 # Nu sim_ticks 1843589966000 # Number of ticks simulated final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221527 # Simulator instruction rate (inst/s) -host_op_rate 221527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5683484333 # Simulator tick rate (ticks/s) -host_mem_usage 334252 # Number of bytes of host memory used -host_seconds 324.38 # Real time elapsed on the host -sim_insts 71858146 # Number of instructions simulated -sim_ops 71858146 # Number of ops (including micro ops) simulated +host_inst_rate 235004 # Simulator instruction rate (inst/s) +host_op_rate 235004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6029262323 # Simulator tick rate (ticks/s) +host_mem_usage 334496 # Number of bytes of host memory used +host_seconds 305.77 # Real time elapsed on the host +sim_insts 71858166 # Number of instructions simulated +sim_ops 71858166 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 498752 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 20812864 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 142016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1542016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1542464 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 270784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2513856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2513408 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 25781248 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 498752 # Number of instructions bytes read from this memory @@ -30,9 +30,9 @@ system.physmem.bytes_written::total 7470272 # Nu system.physmem.num_reads::cpu0.inst 7793 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 325201 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24101 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 4231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39279 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39272 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 402832 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 116723 # Number of write requests responded to by this memory @@ -40,9 +40,9 @@ system.physmem.num_writes::total 116723 # Nu system.physmem.bw_read::cpu0.inst 270533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 11289313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 77032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 836420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 836663 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 146879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1363566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1363323 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 13984264 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 270533 # Instruction read bandwidth from this memory (bytes/s) @@ -55,58 +55,58 @@ system.physmem.bw_total::writebacks 4052025 # To system.physmem.bw_total::cpu0.inst 270533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 11289313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 77032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 836420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 836663 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 146879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1363566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1363323 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18036288 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 69838 # Number of read requests accepted -system.physmem.writeReqs 42816 # Number of write requests accepted +system.physmem.writeReqs 43200 # Number of write requests accepted system.physmem.readBursts 69838 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 42816 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 43200 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 4468672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue -system.physmem.bytesWritten 2738752 # Total number of bytes written to DRAM +system.physmem.bytesWritten 2763328 # Total number of bytes written to DRAM system.physmem.bytesReadSys 4469632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2740224 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 2764800 # Total written bytes from the system interface side system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 59609 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 4348 # Per bank write bursts system.physmem.perBankRdBursts::1 4129 # Per bank write bursts system.physmem.perBankRdBursts::2 4337 # Per bank write bursts system.physmem.perBankRdBursts::3 4598 # Per bank write bursts system.physmem.perBankRdBursts::4 3888 # Per bank write bursts system.physmem.perBankRdBursts::5 4661 # Per bank write bursts -system.physmem.perBankRdBursts::6 4236 # Per bank write bursts +system.physmem.perBankRdBursts::6 4235 # Per bank write bursts system.physmem.perBankRdBursts::7 4148 # Per bank write bursts -system.physmem.perBankRdBursts::8 4711 # Per bank write bursts +system.physmem.perBankRdBursts::8 4712 # Per bank write bursts system.physmem.perBankRdBursts::9 4417 # Per bank write bursts system.physmem.perBankRdBursts::10 4595 # Per bank write bursts system.physmem.perBankRdBursts::11 4084 # Per bank write bursts -system.physmem.perBankRdBursts::12 4057 # Per bank write bursts -system.physmem.perBankRdBursts::13 4571 # Per bank write bursts +system.physmem.perBankRdBursts::12 4058 # Per bank write bursts +system.physmem.perBankRdBursts::13 4570 # Per bank write bursts system.physmem.perBankRdBursts::14 4705 # Per bank write bursts system.physmem.perBankRdBursts::15 4338 # Per bank write bursts system.physmem.perBankWrBursts::0 2799 # Per bank write bursts system.physmem.perBankWrBursts::1 2436 # Per bank write bursts -system.physmem.perBankWrBursts::2 2776 # Per bank write bursts -system.physmem.perBankWrBursts::3 2976 # Per bank write bursts -system.physmem.perBankWrBursts::4 2273 # Per bank write bursts -system.physmem.perBankWrBursts::5 2670 # Per bank write bursts +system.physmem.perBankWrBursts::2 2792 # Per bank write bursts +system.physmem.perBankWrBursts::3 3104 # Per bank write bursts +system.physmem.perBankWrBursts::4 2401 # Per bank write bursts +system.physmem.perBankWrBursts::5 2782 # Per bank write bursts system.physmem.perBankWrBursts::6 2480 # Per bank write bursts system.physmem.perBankWrBursts::7 2289 # Per bank write bursts -system.physmem.perBankWrBursts::8 3133 # Per bank write bursts +system.physmem.perBankWrBursts::8 3134 # Per bank write bursts system.physmem.perBankWrBursts::9 2510 # Per bank write bursts system.physmem.perBankWrBursts::10 2861 # Per bank write bursts system.physmem.perBankWrBursts::11 2441 # Per bank write bursts system.physmem.perBankWrBursts::12 2439 # Per bank write bursts -system.physmem.perBankWrBursts::13 2832 # Per bank write bursts +system.physmem.perBankWrBursts::13 2831 # Per bank write bursts system.physmem.perBankWrBursts::14 3033 # Per bank write bursts system.physmem.perBankWrBursts::15 2845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 1842578089000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 1842577981000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,11 +120,11 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 42816 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5331 # What read queue length does an incoming req see +system.physmem.writePktSize::6 43200 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -155,190 +155,183 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.185887 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.348650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 370.654869 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7177 35.77% 35.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4604 22.94% 58.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1640 8.17% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 939 4.68% 71.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 711 3.54% 75.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 484 2.41% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 449 2.24% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 396 1.97% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3666 18.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20066 # Bytes accessed per row activation +system.physmem.wrQLenPdf::15 746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.141427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.044984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 371.054922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7137 35.54% 35.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4621 23.01% 58.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1666 8.30% 66.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 928 4.62% 71.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 708 3.53% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 489 2.44% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 446 2.22% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 393 1.96% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3693 18.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20081 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 1852 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 37.694924 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 845.707060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 845.707136 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 1850 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 1852 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 1852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.106371 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.632339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.643623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.84% 1.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.38% 2.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.22% 2.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 3 0.16% 2.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1503 81.16% 83.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 52 2.81% 86.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 11 0.59% 87.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 74 4.00% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.22% 91.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 8 0.43% 91.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.92% 92.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.43% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.38% 93.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.05% 93.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.16% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.43% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.43% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 15 0.81% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.05% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 66 3.56% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.05% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.11% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.11% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.16% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.313715 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.866365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.527044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 41 2.21% 2.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 7 0.38% 2.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 1554 83.91% 86.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 22 1.19% 87.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 8 0.43% 88.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 17 0.92% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 85 4.59% 93.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 1 0.05% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 5 0.27% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 12 0.65% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 79 4.27% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.05% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 1 0.05% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 2 0.11% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.11% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 1 0.05% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 1 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.22% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 1852 # Writes before turning the bus around for reads -system.physmem.totQLat 871326250 # Total ticks spent queuing -system.physmem.totMemAccLat 2180507500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 868841000 # Total ticks spent queuing +system.physmem.totMemAccLat 2178022250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 349115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12479.07 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12443.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31229.07 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31193.48 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.08 # Average write queue length when enqueuing -system.physmem.readRowHits 58948 # Number of row buffer hits during reads -system.physmem.writeRowHits 33602 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.48 # Row buffer hit rate for writes -system.physmem.avgGap 16356082.24 # Average gap between requests -system.physmem.pageHitRate 82.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75161520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 40936500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 267891000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 134129520 # Energy for write commands per rank (pJ) +system.physmem.avgWrQLen 4.02 # Average write queue length when enqueuing +system.physmem.readRowHits 58950 # Number of row buffer hits during reads +system.physmem.writeRowHits 33969 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.63 # Row buffer hit rate for writes +system.physmem.avgGap 16300518.24 # Average gap between requests +system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75327840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 41027250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 267883200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 136617840 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36125026515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 799629184500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 925463073795 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.948938 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1310373436000 # Time in different power states +system.physmem_0.actBackEnergy 36136650240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 799618982250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 925467232860 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.951944 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1310356278000 # Time in different power states system.physmem_0.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9753765000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9770912000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 76537440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41650125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 276728400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 76484520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41621250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 276736200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 143169120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35621035650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799049139750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 924399004725 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.002289 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1311095993000 # Time in different power states +system.physmem_1.actBackEnergy 35633622105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799038075000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 924400452435 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.003354 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1311078051250 # Time in different power states system.physmem_1.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9016803000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9034735750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4864865 # DTB read hits +system.cpu0.dtb.read_hits 4864866 # DTB read hits system.cpu0.dtb.read_misses 6190 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 429298 # DTB read accesses -system.cpu0.dtb.write_hits 3435007 # DTB write hits +system.cpu0.dtb.write_hits 3435008 # DTB write hits system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 165213 # DTB write accesses -system.cpu0.dtb.data_hits 8299872 # DTB hits +system.cpu0.dtb.data_hits 8299874 # DTB hits system.cpu0.dtb.data_misses 6878 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations system.cpu0.dtb.data_accesses 594511 # DTB accesses @@ -374,10 +367,10 @@ system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # nu system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1820420159000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1820420490500 98.74% 98.74% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 39420000 0.00% 98.75% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 369089000 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22760564000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22760232500 1.23% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1843589232000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -442,32 +435,32 @@ system.cpu0.kern.mode_switch_good::kernel 0.322243 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29996442500 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2592008500 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1811000779000 98.23% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 29995203000 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2591439000 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1811002588000 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.cpu0.committedInsts 32582067 # Number of instructions committed system.cpu0.committedOps 32582067 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 30467910 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 163902 # Number of float alu accesses -system.cpu0.num_func_calls 798063 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4326151 # number of instructions that are conditional controls +system.cpu0.num_func_calls 798062 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4326152 # number of instructions that are conditional controls system.cpu0.num_int_insts 30467910 # number of integer instructions system.cpu0.num_fp_insts 163902 # number of float instructions system.cpu0.num_int_register_reads 42599897 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22343202 # number of times the integer registers were written +system.cpu0.num_int_register_writes 22343200 # number of times the integer registers were written system.cpu0.num_fp_register_reads 84869 # number of times the floating registers were read system.cpu0.num_fp_register_writes 86282 # number of times the floating registers were written -system.cpu0.num_mem_refs 8329685 # number of memory refs -system.cpu0.num_load_insts 4886081 # Number of load instructions -system.cpu0.num_store_insts 3443604 # Number of store instructions -system.cpu0.num_idle_cycles 904742998.483282 # Number of idle cycles -system.cpu0.num_busy_cycles 23823652.516718 # Number of busy cycles +system.cpu0.num_mem_refs 8329687 # number of memory refs +system.cpu0.num_load_insts 4886082 # Number of load instructions +system.cpu0.num_store_insts 3443605 # Number of store instructions +system.cpu0.num_idle_cycles 904742998.451047 # Number of idle cycles +system.cpu0.num_busy_cycles 23823652.548953 # Number of busy cycles system.cpu0.not_idle_fraction 0.025656 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.974344 # Percentage of idle cycles system.cpu0.Branches 5381713 # Number of branches fetched system.cpu0.op_class::No_OpClass 1604740 4.92% 4.92% # Class of executed instruction -system.cpu0.op_class::IntAlu 21953707 67.37% 72.29% # Class of executed instruction +system.cpu0.op_class::IntAlu 21953705 67.37% 72.29% # Class of executed instruction system.cpu0.op_class::IntMult 32143 0.10% 72.39% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 72.39% # Class of executed instruction system.cpu0.op_class::FloatAdd 13006 0.04% 72.43% # Class of executed instruction @@ -496,196 +489,196 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.43% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.43% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.43% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::MemRead 5016903 15.39% 87.83% # Class of executed instruction -system.cpu0.op_class::MemWrite 3446713 10.58% 98.40% # Class of executed instruction +system.cpu0.op_class::MemRead 5016904 15.39% 87.83% # Class of executed instruction +system.cpu0.op_class::MemWrite 3446714 10.58% 98.40% # Class of executed instruction system.cpu0.op_class::IprAccess 520313 1.60% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 32589155 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1393262 # number of replacements +system.cpu0.dcache.tags.replacements 1393265 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13241810 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393774 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.500687 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13241654 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393777 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.500554 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.746834 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216845 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034134 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497552 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236752 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265692 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.747103 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216699 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034010 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497553 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236751 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265691 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63387052 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63387052 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4025112 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1019452 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2537983 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7582547 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3145682 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 772489 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357389 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5275560 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 63386315 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63386315 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4025113 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1019893 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2537393 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7582399 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3145683 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 772678 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1357185 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275546 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114073 # 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number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 288309 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 572598 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 572598 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1581 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1581 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 860907 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 860907 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 860907 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 860907 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86811 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 260246 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 347057 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38389 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99268 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137657 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2090 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6122 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8212 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 125186 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 359525 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 484711 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 125186 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 359525 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 484711 # number of overall MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 125200 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 359514 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484714 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 125200 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 359514 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484714 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2652 # number of ReadReq MSHR uncacheable @@ -695,235 +688,235 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3516 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223501500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676661000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6900162500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2093885000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4616741882 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6710626882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223397500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676165000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6899562500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092034000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4615486880 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6707520880 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25771500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103207500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 108000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 108000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4317386500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9293402882 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13610789382 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4317386500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9293402882 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13610789382 # number of overall MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103208000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 105000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 105000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4315431500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9291651880 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13607083380 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4315431500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9291651880 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13607083380 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 293417500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 298094000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591511500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372514000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372517000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 424017500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796531500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665931500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796534500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665934500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 722111500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388043000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078461 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084317 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048921 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022381 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388046000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078441 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084333 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048923 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022380 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.098865 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103987 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103978 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040356 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25616.966981 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17969.671819 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19882.272346 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54545.300615 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46505.982372 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48747.834389 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25611.932820 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17968.249272 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19880.199794 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54495.662820 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46495.213765 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.333423 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.807579 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.888456 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 36000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.889252 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.949342 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230231.149567 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230233.003708 # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226544.795222 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225969.290804 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226545.648464 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225970.308789 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.396887 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.883268 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 963474 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.175730 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41537475 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 963985 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 43.089337 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 963447 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.175727 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41538422 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 963958 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 43.091527 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 10558559500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250464 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956509 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.968757 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250530 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956033 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.969164 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.510255 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160071 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328064 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160070 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328065 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998390 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43482483 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43482483 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32077013 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7031290 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2429172 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41537475 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32077013 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13857.183250 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1125427 # DTB read hits +system.cpu1.dtb.read_hits 1125881 # DTB read hits system.cpu1.dtb.read_misses 1262 # DTB read misses system.cpu1.dtb.read_acv 31 # DTB read access violations -system.cpu1.dtb.read_accesses 117717 # DTB read accesses -system.cpu1.dtb.write_hits 832316 # DTB write hits +system.cpu1.dtb.read_accesses 118172 # DTB read accesses +system.cpu1.dtb.write_hits 832506 # DTB write hits system.cpu1.dtb.write_misses 154 # DTB write misses system.cpu1.dtb.write_acv 18 # DTB write access violations -system.cpu1.dtb.write_accesses 48434 # DTB write accesses -system.cpu1.dtb.data_hits 1957743 # DTB hits +system.cpu1.dtb.write_accesses 48626 # DTB write accesses +system.cpu1.dtb.data_hits 1958387 # DTB hits system.cpu1.dtb.data_misses 1416 # DTB misses system.cpu1.dtb.data_acv 49 # DTB access violations -system.cpu1.dtb.data_accesses 166151 # DTB accesses -system.cpu1.itb.fetch_hits 753702 # ITB hits +system.cpu1.dtb.data_accesses 166798 # DTB accesses +system.cpu1.itb.fetch_hits 755228 # ITB hits system.cpu1.itb.fetch_misses 636 # ITB misses system.cpu1.itb.fetch_acv 28 # ITB acv -system.cpu1.itb.fetch_accesses 754338 # ITB accesses +system.cpu1.itb.fetch_accesses 755864 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -936,7 +929,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953452897 # number of cpu cycles simulated +system.cpu1.numCycles 953452805 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -956,35 +949,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7155032 # Number of instructions committed -system.cpu1.committedOps 7155032 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6639972 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 39507 # Number of float alu accesses -system.cpu1.num_func_calls 205327 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 849342 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6639972 # number of integer instructions -system.cpu1.num_fp_insts 39507 # number of float instructions -system.cpu1.num_int_register_reads 9236476 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4860513 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 20546 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21005 # number of times the floating registers were written -system.cpu1.num_mem_refs 1964570 # number of memory refs -system.cpu1.num_load_insts 1130012 # Number of load instructions -system.cpu1.num_store_insts 834558 # Number of store instructions -system.cpu1.num_idle_cycles 924897585.359422 # Number of idle cycles -system.cpu1.num_busy_cycles 28555311.640577 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029949 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970051 # Percentage of idle cycles -system.cpu1.Branches 1119214 # Number of branches fetched -system.cpu1.op_class::No_OpClass 390317 5.45% 5.45% # Class of executed instruction -system.cpu1.op_class::IntAlu 4631234 64.71% 70.17% # Class of executed instruction -system.cpu1.op_class::IntMult 7711 0.11% 70.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3307 0.05% 70.32% # Class of executed instruction +system.cpu1.committedInsts 7156553 # Number of instructions committed +system.cpu1.committedOps 7156553 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6641394 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 39637 # Number of float alu accesses +system.cpu1.num_func_calls 205363 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 849545 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6641394 # number of integer instructions +system.cpu1.num_fp_insts 39637 # number of float instructions +system.cpu1.num_int_register_reads 9238548 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4861490 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 20633 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21093 # number of times the floating registers were written +system.cpu1.num_mem_refs 1965214 # number of memory refs +system.cpu1.num_load_insts 1130466 # Number of load instructions +system.cpu1.num_store_insts 834748 # Number of store instructions +system.cpu1.num_idle_cycles 924897133.577308 # Number of idle cycles +system.cpu1.num_busy_cycles 28555671.422692 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029950 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970050 # Percentage of idle cycles +system.cpu1.Branches 1119461 # Number of branches fetched +system.cpu1.op_class::No_OpClass 390354 5.45% 5.45% # Class of executed instruction +system.cpu1.op_class::IntAlu 4632011 64.71% 70.16% # Class of executed instruction +system.cpu1.op_class::IntMult 7720 0.11% 70.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3352 0.05% 70.32% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatDiv 440 0.01% 70.33% # Class of executed instruction +system.cpu1.op_class::FloatDiv 449 0.01% 70.33% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction @@ -1006,40 +999,40 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::MemRead 1158585 16.19% 86.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 835763 11.68% 98.20% # Class of executed instruction +system.cpu1.op_class::MemRead 1159039 16.19% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 835953 11.68% 98.20% # Class of executed instruction system.cpu1.op_class::IprAccess 129140 1.80% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7156497 # Class of executed instruction -system.cpu2.branchPred.lookups 10791906 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10058996 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 121698 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8434906 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6656118 # Number of BTB hits +system.cpu1.op_class::total 7158018 # Class of executed instruction +system.cpu2.branchPred.lookups 10791255 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10058403 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 121654 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8435844 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6655738 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 78.911585 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 298697 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7721 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 78.898306 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 298678 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7720 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3520448 # DTB read hits -system.cpu2.dtb.read_misses 12146 # DTB read misses +system.cpu2.dtb.read_hits 3519605 # DTB read hits +system.cpu2.dtb.read_misses 12192 # DTB read misses system.cpu2.dtb.read_acv 125 # DTB read access violations -system.cpu2.dtb.read_accesses 256305 # DTB read accesses -system.cpu2.dtb.write_hits 2173477 # DTB write hits -system.cpu2.dtb.write_misses 2690 # DTB write misses +system.cpu2.dtb.read_accesses 255658 # DTB read accesses +system.cpu2.dtb.write_hits 2173211 # DTB write hits +system.cpu2.dtb.write_misses 2700 # DTB write misses system.cpu2.dtb.write_acv 124 # DTB write access violations -system.cpu2.dtb.write_accesses 93625 # DTB write accesses -system.cpu2.dtb.data_hits 5693925 # DTB hits -system.cpu2.dtb.data_misses 14836 # DTB misses +system.cpu2.dtb.write_accesses 93379 # DTB write accesses +system.cpu2.dtb.data_hits 5692816 # DTB hits +system.cpu2.dtb.data_misses 14892 # DTB misses system.cpu2.dtb.data_acv 249 # DTB access violations -system.cpu2.dtb.data_accesses 349930 # DTB accesses -system.cpu2.itb.fetch_hits 553155 # ITB hits -system.cpu2.itb.fetch_misses 5226 # ITB misses -system.cpu2.itb.fetch_acv 187 # ITB acv -system.cpu2.itb.fetch_accesses 558381 # ITB accesses +system.cpu2.dtb.data_accesses 349037 # DTB accesses +system.cpu2.itb.fetch_hits 552522 # ITB hits +system.cpu2.itb.fetch_misses 5239 # ITB misses +system.cpu2.itb.fetch_acv 186 # ITB acv +system.cpu2.itb.fetch_accesses 557761 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1052,143 +1045,143 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 32236279 # number of cpu cycles simulated +system.cpu2.numCycles 32231216 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9243840 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 40617547 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10791906 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6954815 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 20753592 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 401538 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 9243140 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40614337 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10791255 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6954416 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20748537 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 401448 # Number of cycles fetch has spent squashing system.cpu2.fetch.TlbCycles 916 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10212 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 2008 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 193151 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 89388 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1068 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2772679 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90084 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.MiscStallCycles 10245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2007 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 193088 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 89379 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1066 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2772079 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 89992 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 30494706 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.331954 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.325119 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 30488864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.332104 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.325204 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 21037778 68.99% 68.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 294298 0.97% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 469114 1.54% 71.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5033169 16.51% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 879924 2.89% 90.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194801 0.64% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 230028 0.75% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433107 1.42% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1922487 6.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 21032791 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 294156 0.96% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 468874 1.54% 71.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5033027 16.51% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 879823 2.89% 90.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194768 0.64% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 230051 0.75% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433078 1.42% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1922296 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 30494706 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.334775 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.259995 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7573321 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 14126025 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7836977 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 524605 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 187915 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 174630 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13216 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 37265458 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 41467 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 187915 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7850244 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4676437 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6613578 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8057400 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2863279 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 36458401 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 57802 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 368784 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 93789 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1799072 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 24336413 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 45554095 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 45489801 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 60051 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22465786 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1870627 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 531021 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 62908 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3828322 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3503706 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2266582 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 453499 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 325031 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 33954893 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 679527 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 33661057 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16143 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2513373 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1127788 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 486024 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 30494706 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.103833 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.612725 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30488864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.334808 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.260093 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7572995 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 14121086 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7836457 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 524591 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 187872 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 174587 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13215 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37262943 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 41463 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 187872 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7849913 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4677015 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6609993 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8056869 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2861349 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 36455800 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 58084 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 369048 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 93720 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1797134 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 24334504 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 45550794 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 45486602 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 59958 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22464723 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1869781 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 530990 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 62923 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3828293 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3503034 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2266301 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 453472 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 325651 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33952570 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 679538 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 33658910 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16165 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2512562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1127430 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 486035 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30488864 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.103974 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.612784 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18452821 60.51% 60.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2702851 8.86% 69.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1349809 4.43% 73.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5753089 18.87% 92.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1041578 3.42% 96.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 588420 1.93% 98.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 396893 1.30% 99.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 164409 0.54% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44836 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18447860 60.51% 60.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2702530 8.86% 69.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1349610 4.43% 73.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5752968 18.87% 92.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1041424 3.42% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 588365 1.93% 98.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 396836 1.30% 99.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 164449 0.54% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44822 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 30494706 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30488864 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 81527 21.02% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 179819 46.37% 67.39% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126481 32.61% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 81533 21.03% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179737 46.36% 67.39% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126415 32.61% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 3131 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 27465013 81.59% 81.60% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21327 0.06% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 3114 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27463980 81.59% 81.60% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21318 0.06% 81.67% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 22209 0.07% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 22163 0.07% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1557 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.74% # Type of FU issued @@ -1210,101 +1203,101 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.74% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3648084 10.84% 92.57% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2197360 6.53% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3647310 10.84% 92.57% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2197101 6.53% 99.10% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 302367 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 33661057 # Type of FU issued -system.cpu2.iq.rate 1.044198 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 387827 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.011522 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 97956454 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 37027606 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 33043548 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 264336 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 125822 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122705 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 33904668 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 141085 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 200240 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 33658910 # Type of FU issued +system.cpu2.iq.rate 1.044295 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387685 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011518 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 97946508 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 37024649 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 33041720 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 264026 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 125654 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122549 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 33902559 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 140922 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 200179 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 431120 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5749 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178621 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 430903 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1110 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5745 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178531 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 4239 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 217381 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.cacheBlocked 217245 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 187915 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4008679 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 205535 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35998675 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51747 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3503706 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2266582 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 605109 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12931 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 157162 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5749 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 59808 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134012 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193820 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33465262 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3541255 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 195795 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 187872 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4009534 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 206574 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35996335 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51785 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3503034 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2266301 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 605122 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12947 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 158194 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5745 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 59769 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 133968 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193737 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33463084 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3540458 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 195826 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1364255 # number of nop insts executed -system.cpu2.iew.exec_refs 5722116 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7732316 # Number of branches executed -system.cpu2.iew.exec_stores 2180861 # Number of stores executed -system.cpu2.iew.exec_rate 1.038124 # Inst execution rate -system.cpu2.iew.wb_sent 33208664 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 33166253 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 19395256 # num instructions producing a value -system.cpu2.iew.wb_consumers 23138933 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.028849 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.838209 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 2630446 # The number of squashed insts skipped by commit +system.cpu2.iew.exec_nop 1364227 # number of nop insts executed +system.cpu2.iew.exec_refs 5721059 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7732015 # Number of branches executed +system.cpu2.iew.exec_stores 2180601 # Number of stores executed +system.cpu2.iew.exec_rate 1.038220 # Inst execution rate +system.cpu2.iew.wb_sent 33206737 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 33164269 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 19394211 # num instructions producing a value +system.cpu2.iew.wb_consumers 23137569 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.028949 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.838213 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 2629534 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 193503 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177071 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 30033551 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.109504 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.847540 # Number of insts commited each cycle +system.cpu2.commit.branchMispredicts 177029 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 30027785 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.109667 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.847605 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 19200071 63.93% 63.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2226295 7.41% 71.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1158853 3.86% 75.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5473619 18.23% 93.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 589521 1.96% 95.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 197097 0.66% 96.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164200 0.55% 96.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 162437 0.54% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 861458 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 19194769 63.92% 63.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2226064 7.41% 71.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1158797 3.86% 75.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5473612 18.23% 93.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 589514 1.96% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 197059 0.66% 96.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164152 0.55% 96.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 162472 0.54% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 861346 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 30033551 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 33322350 # Number of instructions committed -system.cpu2.commit.committedOps 33322350 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 30027785 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 33320829 # Number of instructions committed +system.cpu2.commit.committedOps 33320829 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5160547 # Number of memory references committed -system.cpu2.commit.loads 3072586 # Number of loads committed +system.cpu2.commit.refs 5159901 # Number of memory references committed +system.cpu2.commit.loads 3072131 # Number of loads committed system.cpu2.commit.membars 67946 # Number of memory barriers committed -system.cpu2.commit.branches 7560075 # Number of branches committed -system.cpu2.commit.fp_insts 120848 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31822701 # Number of committed integer instructions. -system.cpu2.commit.function_calls 240099 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1204434 3.61% 3.61% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 26541208 79.65% 83.26% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20874 0.06% 83.33% # Class of committed instruction +system.cpu2.commit.branches 7559828 # Number of branches committed +system.cpu2.commit.fp_insts 120718 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31821279 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240082 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1204397 3.61% 3.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26540433 79.65% 83.27% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20865 0.06% 83.33% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21768 0.07% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21723 0.07% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1557 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.40% # Class of committed instruction @@ -1326,29 +1319,29 @@ system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.40% system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3140532 9.42% 92.82% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2089601 6.27% 99.09% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3140077 9.42% 92.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2089410 6.27% 99.09% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 302367 0.91% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 33322350 # Class of committed instruction -system.cpu2.commit.bw_lim_events 861458 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 65049813 # The number of ROB reads -system.cpu2.rob.rob_writes 72365341 # The number of ROB writes -system.cpu2.timesIdled 178213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1741573 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747477665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 32121047 # Number of Instructions Simulated -system.cpu2.committedOps 32121047 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.003587 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.003587 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.996425 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.996425 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 43934131 # number of integer regfile reads -system.cpu2.int_regfile_writes 23251716 # number of integer regfile writes -system.cpu2.fp_regfile_reads 74710 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74652 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5374912 # number of misc regfile reads -system.cpu2.misc_regfile_writes 272966 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 33320829 # Class of committed instruction +system.cpu2.commit.bw_lim_events 861346 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 65041726 # The number of ROB reads +system.cpu2.rob.rob_writes 72360391 # The number of ROB writes +system.cpu2.timesIdled 178229 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1742352 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747482810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 32119546 # Number of Instructions Simulated +system.cpu2.committedOps 32119546 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.003477 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.003477 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.996535 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.996535 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 43931463 # number of integer regfile reads +system.cpu2.int_regfile_writes 23250358 # number of integer regfile writes +system.cpu2.fp_regfile_reads 74602 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74558 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5374687 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272957 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1391,7 +1384,7 @@ system.iobus.pkt_size_system.bridge.master::total 45584 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2564500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2566000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 118500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1399,20 +1392,20 @@ system.iobus.reqLayer22.occupancy 55500 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2121000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2120500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 84230549 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 86466426 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16458000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16844000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements system.iocache.tags.tagsinuse 1.261273 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694926918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1694926915000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 1.261273 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078830 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078830 # Average percentage of cache occupancy @@ -1429,14 +1422,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9458962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9458962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2126843587 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2126843587 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9458962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9458962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9458962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9458962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9575962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9575962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2102569464 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2102569464 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9575962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9575962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9575962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9575962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1453,77 +1446,77 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54676.080925 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54676.080925 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 51185.107504 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 51185.107504 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54676.080925 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54676.080925 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55352.381503 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 55352.381503 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 50600.920870 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 50600.920870 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 55352.381503 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 55352.381503 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5.166667 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16272 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 16272 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 69 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 69 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 69 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 69 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6008962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6008962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1313243587 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1313243587 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 6008962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6008962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 6008962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6008962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.391606 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.391606 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.398844 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.398844 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 87086.405797 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80705.726831 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80705.726831 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16656 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 16656 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6075962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6075962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1269053528 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1269053528 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 6075962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6075962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 6075962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6075962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.400847 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.400847 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86799.457143 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.974544 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.974544 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 86799.457143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 86799.457143 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 337614 # number of replacements -system.l2c.tags.tagsinuse 65425.004009 # Cycle average of tags in use -system.l2c.tags.total_refs 4005267 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65425.009940 # Cycle average of tags in use +system.l2c.tags.total_refs 4005222 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 402776 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.944155 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 9.944043 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54894.973613 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2664.591905 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2878.625445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 441.912379 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 553.808439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2003.360689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1987.731539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 54894.998559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2664.593878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2878.621970 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 441.912362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 553.890082 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2003.349443 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1987.643647 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.837631 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.040658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.043924 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.006743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008450 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008452 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.030569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.030330 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.030329 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.998306 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id @@ -1532,12 +1525,12 @@ system.l2c.tags.age_task_id_blocks_1024::2 6136 # system.l2c.tags.age_task_id_blocks_1024::3 2779 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 55356 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38412750 # Number of tag accesses -system.l2c.tags.data_accesses 38412750 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 835859 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 835859 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 963177 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 963177 # number of WritebackClean hits +system.l2c.tags.tag_accesses 38412363 # Number of tag accesses +system.l2c.tags.data_accesses 38412363 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 835864 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 835864 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 963150 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 963150 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits @@ -1545,31 +1538,31 @@ system.l2c.UpgradeReq_hits::total 13 # nu system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # 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number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 949847 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 485259 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 78702 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 253717 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 817678 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 504328 # number of demand (read+write) hits +system.l2c.ReadSharedReq_hits::cpu1.data 78708 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 253716 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 817683 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 504325 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 575657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 122989 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 103137 # 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number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115789 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 27191 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115788 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 7793 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 2219 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu2.inst 4231 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 14243 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 250829 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 10186 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 12435 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 273450 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 10193 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 12429 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.029775 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.029775 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 71750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71750 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117532.325115 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125700.959841 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 122930.961987 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123226.356589 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116441.046534 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117536.509851 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117043.234163 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.114656 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046700 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020733 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.189686 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.108365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.029776 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.189686 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.108365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.029776 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68607.142857 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68607.142857 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117398.795872 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125662.406679 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 122860.134166 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123414.186667 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116335.867752 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117560.865717 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117008.907258 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 116950.072479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123120.911156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121025.870597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 116950.072479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123120.911156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121025.870597 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208275.395034 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 212804.232804 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210534.690799 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218725.587145 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218727.441286 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211900.421496 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215041.240046 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214012.894469 # average overall mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215042.093288 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214013.912453 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212271.654766 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 213103.599222 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213104.085603 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294754 # Transaction distribution +system.membus.trans_dist::ReadResp 294755 # Transaction distribution system.membus.trans_dist::WriteReq 9812 # Transaction distribution system.membus.trans_dist::WriteResp 9812 # Transaction distribution system.membus.trans_dist::WritebackDirty 116723 # Transaction distribution -system.membus.trans_dist::CleanEvict 261691 # Transaction distribution +system.membus.trans_dist::CleanEvict 261851 # Transaction distribution system.membus.trans_dist::UpgradeReq 160 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 162 # Transaction distribution -system.membus.trans_dist::ReadExReq 115651 # Transaction distribution -system.membus.trans_dist::ReadExResp 115651 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287866 # Transaction distribution +system.membus.trans_dist::UpgradeResp 116 # Transaction distribution +system.membus.trans_dist::ReadExReq 115650 # Transaction distribution +system.membus.trans_dist::ReadExResp 115650 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287867 # Transaction distribution system.membus.trans_dist::BadAddressError 256 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 24896 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143238 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 512 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177708 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1302629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1286086 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30604608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 30650192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33314576 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 159 # Total snoops (count) -system.membus.snoop_fanout::samples 840768 # Request fanout histogram +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33314512 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 160 # Total snoops (count) +system.membus.snoop_fanout::samples 840765 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840768 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840765 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840768 # Request fanout histogram -system.membus.reqLayer0.occupancy 11147000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840765 # Request fanout histogram +system.membus.reqLayer0.occupancy 11148000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 348692458 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 350987320 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 375048955 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 374958750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 27286702 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 368038 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4714972 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2357166 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4714924 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2357142 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1129 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1129 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062235 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2062215 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 878682 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 963177 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 599628 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 879068 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 963447 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 600902 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 39 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302904 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302904 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 964165 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091197 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302901 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302901 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 964138 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091204 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 256 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 16272 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891480 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7105575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123348160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142745680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266093840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421214 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4208473 # Request fanout histogram +system.toL2Bus.trans_dist::InvalidateReq 16656 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891696 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4215380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7107076 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123363712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142746256 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266109968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421211 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4208443 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.000983 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.031334 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4204337 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4204307 99.90% 99.90% # Request fanout histogram system.toL2Bus.snoop_fanout::1 4136 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4208473 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1783329500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4208443 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1783289500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 99462 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 678448171 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 678414167 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 743541954 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 743545456 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |