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Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full')
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini266
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr16
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout10
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt12
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal2
5 files changed, 283 insertions, 23 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index a2fe4ebe1..e12da6bca 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -15,10 +15,12 @@ boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/work/gem5/dist/binaries/console
+console=/arm/projectscratch/randd/systems/dist/binaries/console
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux
+kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
@@ -28,11 +30,17 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-pal=/work/gem5/dist/binaries/ts_osfpal
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
+power_model=Null
+readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
symbolfile=
system_rev=1024
system_type=34
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -45,8 +53,13 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
delay=50000
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
@@ -68,6 +81,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -84,6 +98,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -105,13 +123,17 @@ addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -130,8 +152,13 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=32768
@@ -147,13 +174,17 @@ addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -172,8 +203,13 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=32768
@@ -202,6 +238,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -217,6 +254,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -269,6 +310,7 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
+default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -305,6 +347,10 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -342,11 +388,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu2.dtb]
type=AlphaTLB
@@ -702,7 +755,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -725,7 +778,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
@@ -744,9 +797,14 @@ sys=system
[system.iobus]
type=NoncoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=1
frontend_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
response_latency=2
use_default_range=false
width=16
@@ -760,13 +818,17 @@ addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=50
@@ -785,8 +847,13 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=1024
@@ -797,13 +864,17 @@ addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -822,20 +893,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=4194304
[system.membus]
type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -847,11 +929,16 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=0
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
@@ -862,6 +949,13 @@ update_data=false
warn_access=
pio=system.membus.default
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=DRAMCtrl
IDD0=0.075000
@@ -896,6 +990,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -907,7 +1002,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
@@ -949,7 +1048,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -964,9 +1063,15 @@ port=3456
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -994,11 +1099,16 @@ system=system
type=AlphaBackdoor
clk_domain=system.clk_domain
cpu=system.cpu0
+default_p_state=UNDEFINED
disk=system.simple_disk
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804682956800
pio_latency=100000
platform=system.tsunami
+power_model=Null
system=system
terminal=system.terminal
pio=system.iobus.master[24]
@@ -1006,9 +1116,14 @@ pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8803072344064
pio_latency=100000
+power_model=Null
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
@@ -1089,6 +1204,7 @@ SubsystemVendorID=0
VendorID=4107
clk_domain=system.clk_domain
config_latency=20000
+default_p_state=UNDEFINED
dma_data_free=false
dma_desc_free=false
dma_no_allocate=true
@@ -1100,10 +1216,14 @@ eventq_index=0
hardware_address=00:90:00:00:00:01
host=system.tsunami.pchip
intr_delay=10000000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
+power_model=Null
rss=false
rx_delay=1000000
rx_fifo_size=524288
@@ -1119,11 +1239,16 @@ pio=system.iobus.master[26]
[system.tsunami.fake_OROM]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8796093677568
pio_latency=100000
pio_size=393216
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1137,11 +1262,16 @@ pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848432
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1155,11 +1285,16 @@ pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848304
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1173,11 +1308,16 @@ pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848569
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1191,11 +1331,16 @@ pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848451
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1209,11 +1354,16 @@ pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848515
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1227,11 +1377,16 @@ pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848579
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1245,11 +1400,16 @@ pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848643
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1263,11 +1423,16 @@ pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848707
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1281,11 +1446,16 @@ pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848771
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1299,11 +1469,16 @@ pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848835
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1317,11 +1492,16 @@ pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848899
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1335,11 +1515,16 @@ pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615850617
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1353,11 +1538,16 @@ pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848891
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1371,11 +1561,16 @@ pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848816
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1389,11 +1584,16 @@ pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848696
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1407,11 +1607,16 @@ pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848936
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1425,11 +1630,16 @@ pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848680
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1443,11 +1653,16 @@ pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848944
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1461,10 +1676,15 @@ pio=system.iobus.master[6]
[system.tsunami.fb]
type=BadDevice
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
devicename=FrameBuffer
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848912
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[21]
@@ -1545,14 +1765,19 @@ VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=0
+default_p_state=UNDEFINED
disks=system.disk0 system.disk2
eventq_index=0
host=system.tsunami.pchip
io_shift=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=30000
+power_model=Null
system=system
dma=system.iobus.slave[1]
pio=system.iobus.master[25]
@@ -1560,10 +1785,15 @@ pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
frequency=976562500
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615847936
pio_latency=100000
+power_model=Null
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
@@ -1576,13 +1806,18 @@ clk_domain=system.clk_domain
conf_base=8804649402368
conf_device_bits=8
conf_size=16777216
+default_p_state=UNDEFINED
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pci_dma_base=0
pci_mem_base=8796093022208
pci_pio_base=8804615847936
pio_addr=8802535473152
pio_latency=100000
platform=system.tsunami
+power_model=Null
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
@@ -1590,10 +1825,15 @@ pio=system.iobus.master[1]
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=8804615848952
pio_latency=100000
platform=system.tsunami
+power_model=Null
system=system
terminal=system.terminal
pio=system.iobus.master[23]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
index 52d4acaec..966691295 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
@@ -1,6 +1,12 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: ClockedObject: Already in the requested power state, request ignored
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: Prefetch instructions in Alpha do not do anything
@@ -15,8 +21,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10194, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7524, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11199, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11377, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
index 001ba9e0a..7e3c6c6ec 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 10:28:58
-gem5 started Dec 4 2015 10:29:24
-gem5 executing on e104799-lin, pid 21387
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:24
+gem5 executing on e108600-lin, pid 39575
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index d2e8a2346..d7da6ec5c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.841599 # Nu
sim_ticks 1841599161000 # Number of ticks simulated
final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 307539 # Simulator instruction rate (inst/s)
-host_op_rate 307539 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8488565495 # Simulator tick rate (ticks/s)
-host_mem_usage 380848 # Number of bytes of host memory used
-host_seconds 216.95 # Real time elapsed on the host
+host_inst_rate 220916 # Simulator instruction rate (inst/s)
+host_op_rate 220916 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6097623299 # Simulator tick rate (ticks/s)
+host_mem_usage 332848 # Number of bytes of host memory used
+host_seconds 302.02 # Real time elapsed on the host
sim_insts 66720805 # Number of instructions simulated
sim_ops 66720805 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -1910,6 +1910,7 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320
system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33343552 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 157 # Total snoops (count)
+system.membus.snoopTraffic 9856 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 742227 # Request fanout histogram
system.membus.snoop_fanout::mean 0.001296 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.035978 # Request fanout histogram
@@ -1962,6 +1963,7 @@ system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1241
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142881728 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 267065664 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 338688 # Total snoops (count)
+system.toL2Bus.snoopTraffic 4852416 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 4114055 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.000998 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.031568 # Request fanout histogram
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
index cbce606f3..8a879f578 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
- 4096K Bcache detected; load hit latency 6 cycles, load miss latency 30 cycles
+ 4096K Bcache detected; load hit latency 6 cycles, load miss latency 32 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 19:27:28 +0000