diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
18 files changed, 996 insertions, 1009 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini index db58f5ad6..2c8d05298 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/work/gem5/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/work/gem5/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,9 +26,10 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/work/gem5/dist/binaries/ts_osfpal +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -146,6 +147,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -162,6 +164,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -569,6 +572,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -585,6 +589,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -618,6 +623,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -634,6 +640,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -649,12 +656,13 @@ size=4194304 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -662,6 +670,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -694,7 +709,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -717,7 +732,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -740,10 +755,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.tsunami.pciconfig.pio -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] @@ -752,6 +766,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=false @@ -768,7 +783,8 @@ system=system tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 -cpu_side=system.iobus.master[29] +writeback_clean=false +cpu_side=system.iobus.master[27] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -903,7 +919,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -916,7 +932,7 @@ port=3456 [system.tsunami] type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart eventq_index=0 intrctrl=system.intrctrl system=system @@ -1029,12 +1045,12 @@ dma_write_delay=0 dma_write_factor=0 eventq_index=0 hardware_address=00:90:00:00:00:01 +host=system.tsunami.pchip intr_delay=10000000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.tsunami rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -1044,9 +1060,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.master[28] dma=system.iobus.slave[2] -pio=system.iobus.master[27] +pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake @@ -1479,14 +1494,13 @@ config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 eventq_index=0 +host=system.tsunami.pchip io_shift=0 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.tsunami system=system -config=system.iobus.master[26] dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1506,25 +1520,20 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +conf_base=8804649402368 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 +pci_dma_base=0 +pci_mem_base=8796093022208 +pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 +platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.master[1] -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr index 518507880..518507880 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout index cc37eeb13..f8b3a5e40 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:12:51 -gem5 started Oct 29 2014 09:20:31 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor +gem5 compiled Dec 4 2015 10:28:58 +gem5 started Dec 4 2015 10:29:11 +gem5 executing on e104799-lin, pid 21295 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor + Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux +info: kernel located at: /work/gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1883224346500 because m5_exit instruction encountered +Exiting @ tick 1906048606500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index a07783bfc..c02ff892c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.906049 # Nu sim_ticks 1906048606500 # Number of ticks simulated final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 269376 # Simulator instruction rate (inst/s) -host_op_rate 269376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9144869235 # Simulator tick rate (ticks/s) -host_mem_usage 376080 # Number of bytes of host memory used -host_seconds 208.43 # Real time elapsed on the host +host_inst_rate 268534 # Simulator instruction rate (inst/s) +host_op_rate 268534 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9116285517 # Simulator tick rate (ticks/s) +host_mem_usage 332204 # Number of bytes of host memory used +host_seconds 209.08 # Real time elapsed on the host sim_insts 56145568 # Number of instructions simulated sim_ops 56145568 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -150,10 +150,10 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5600 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see @@ -197,20 +197,20 @@ system.physmem.wrQLenPdf::60 53 # Wh system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 519.603311 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.318586 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 407.156918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14830 23.03% 23.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11097 17.23% 40.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4950 7.69% 47.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3246 5.04% 52.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2531 3.93% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1970 3.06% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4174 6.48% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1358 2.11% 68.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20237 31.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 64400 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 519.546832 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.268868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 407.153797 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14837 23.04% 23.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11098 17.23% 40.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4944 7.68% 47.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3257 5.06% 53.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2526 3.92% 56.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1968 3.06% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4176 6.48% 66.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1357 2.11% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20237 31.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64400 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes @@ -260,12 +260,12 @@ system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Wr system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads -system.physmem.totQLat 2636864500 # Total ticks spent queuing -system.physmem.totMemAccLat 10223958250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2637486000 # Total ticks spent queuing +system.physmem.totMemAccLat 10224579750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6516.49 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6518.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25266.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25268.02 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s @@ -276,39 +276,39 @@ system.physmem.busUtilRead 0.11 # Da system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing -system.physmem.readRowHits 362818 # Number of row buffer hits during reads -system.physmem.writeRowHits 95583 # Number of row buffer hits during writes +system.physmem.readRowHits 362820 # Number of row buffer hits during reads +system.physmem.writeRowHits 95574 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes system.physmem.avgGap 3644923.65 # Average gap between requests system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 237542760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 129611625 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 237573000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 129628125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67952834145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1084018111500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278788448510 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.912661 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1803102997000 # Time in different power states +system.physmem_0.actBackEnergy 67955758245 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084015546500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278788854350 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.912874 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1803098707000 # Time in different power states system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39293158000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39297448000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249268320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136009500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 249291000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136021875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68401366290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1083624670500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278869710170 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.955290 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1802449451000 # Time in different power states +system.physmem_1.actBackEnergy 68412640320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1083614781000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278871129755 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.956034 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1802432810250 # Time in different power states system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 39946717750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 39963358500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 15009028 # Number of BP lookups system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted @@ -375,10 +375,10 @@ system.cpu.kern.ipl_good::21 133 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837271257000 96.39% 96.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1837271633000 96.39% 96.39% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 67985555000 3.57% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 67985179000 3.57% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -447,8 +447,8 @@ system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # nu system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 84511190 # Number of cycles that the object actually ticked -system.cpu.idleCycles 137195507 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 84511215 # Number of cycles that the object actually ticked +system.cpu.idleCycles 137195482 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1395430 # number of replacements system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks. @@ -487,16 +487,16 @@ system.cpu.dcache.demand_misses::cpu.data 1776836 # n system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses system.cpu.dcache.overall_misses::total 1776836 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974936500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 46974936500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956179000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33956179000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974912500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46974912500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956321000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33956321000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80931115500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80931115500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80931115500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80931115500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80931233500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80931233500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80931233500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80931233500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses) @@ -519,16 +519,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.117130 system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45547.881459 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45547.881459 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45547.947869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45547.947869 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -565,22 +565,22 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9624 system.cpu.dcache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817588500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817588500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272399000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272399000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817391500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817391500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272477000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272477000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217466000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217466000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089987500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61089987500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089987500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61089987500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1530266500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1530266500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089868500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61089868500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089868500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61089868500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529366500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529366500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162508500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3692775000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3692775000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691875000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691875000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119139 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119139 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049480 # mshr miss rate for WriteReq accesses @@ -591,28 +591,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090889 system.cpu.dcache.demand_mshr_miss_rate::total 0.090889 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.090889 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40785.018453 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40785.018453 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.508845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.508845 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40784.835087 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40784.835087 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.765083 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.765083 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220690.294202 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220690.294202 # average ReadReq mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990 # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224699.553200 # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224699.553200 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223020.594275 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223020.594275 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222966.239884 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222966.239884 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1460396 # number of replacements system.cpu.icache.tags.tagsinuse 508.105648 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18947784 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 18947783 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1460907 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.969877 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.969876 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 50119711500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 508.105648 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992394 # Average percentage of cache occupancy @@ -622,44 +622,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 103 system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21869953 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21869953 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18947787 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18947787 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18947787 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18947787 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18947787 # number of overall hits -system.cpu.icache.overall_hits::total 18947787 # number of overall hits +system.cpu.icache.tags.tag_accesses 21869952 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21869952 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18947786 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18947786 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18947786 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18947786 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18947786 # number of overall hits +system.cpu.icache.overall_hits::total 18947786 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1461083 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1461083 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1461083 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1461083 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1461083 # number of overall misses system.cpu.icache.overall_misses::total 1461083 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009217000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21009217000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21009217000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21009217000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21009217000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21009217000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20408870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20408870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20408870 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20408870 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20408870 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20408870 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21009954000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21009954000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21009954000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21009954000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21009954000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20408869 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20408869 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20408869 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20408869 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20408869 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20408869 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071591 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.071591 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.071591 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.071591 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.071591 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.071591 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.208436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14379.208436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14379.208436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14379.208436 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.712857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14379.712857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14379.712857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14379.712857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,34 +676,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1461083 system.cpu.icache.demand_mshr_misses::total 1461083 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1461083 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1461083 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548134000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19548134000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548134000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19548134000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548134000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19548134000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548871000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19548871000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548871000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19548871000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548871000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19548871000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071591 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.071591 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.071591 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.208436 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.208436 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.712857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.712857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 339568 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65260.797469 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 65260.797416 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4999517 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404730 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 12.352722 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 9687465000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251550 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395782 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251440 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395876 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150100 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.824680 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087347 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.083773 # Average percentage of cache occupancy @@ -751,18 +751,18 @@ system.cpu.l2cache.overall_misses::cpu.data 388866 # system.cpu.l2cache.overall_misses::total 405190 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 404000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 404000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837528000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14837528000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2141943000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2141943000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680651000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680651000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2141943000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48518179000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50660122000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2141943000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48518179000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50660122000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837606000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14837606000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2142680000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2142680000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680454000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680454000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2142680000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48518060000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50660740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2142680000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48518060000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50660740000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 838232 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 838232 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1459802 # number of WritebackClean accesses(hits+misses) @@ -797,18 +797,18 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.278565 system.cpu.l2cache.overall_miss_rate::total 0.141825 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.838058 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.838058 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131259.495222 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131259.495222 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.035572 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.035572 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125029.591056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125029.591056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -841,24 +841,24 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13670938000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13670938000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978703000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978703000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960659500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960659500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978703000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631597500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46610300500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978703000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631597500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46610300500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443571000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443571000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13671016000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13671016000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1979440000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1979440000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960462500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960462500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1979440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631478500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46610918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1979440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631478500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46610918500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442671000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442671000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3495402500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3495402500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494502500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494502500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses @@ -875,24 +875,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565 system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544 # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -958,40 +958,34 @@ system.iobus.trans_dist::ReadResp 7107 # Tr system.iobus.trans_dist::WriteReq 51176 # Transaction distribution system.iobus.trans_dist::WriteResp 51176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5110 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 33116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116566 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 44381 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 386000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 784500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1005,16 +999,10 @@ system.iobus.reqLayer24.occupancy 2308500 # La system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 224500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 98500 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215092991 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 142500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215092991 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 31500 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) @@ -1161,7 +1149,7 @@ system.membus.reqLayer1.occupancy 1319381154 # La system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160247074 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160244574 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal index 455709c02..2c979b67f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 08ac5b1cf..c1955556a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/work/gem5/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/work/gem5/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,9 +26,10 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/work/gem5/dist/binaries/ts_osfpal +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -171,6 +172,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -187,6 +189,7 @@ system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -518,6 +521,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -534,6 +538,7 @@ system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -676,6 +681,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -692,6 +698,7 @@ system=system tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] @@ -1023,6 +1030,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -1039,6 +1047,7 @@ system=system tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] @@ -1098,7 +1107,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -1121,7 +1130,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -1144,10 +1153,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.tsunami.pciconfig.pio -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] @@ -1156,6 +1164,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=false @@ -1172,7 +1181,8 @@ system=system tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 -cpu_side=system.iobus.master[29] +writeback_clean=false +cpu_side=system.iobus.master[27] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -1191,6 +1201,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -1207,6 +1218,7 @@ system=system tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -1342,7 +1354,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1355,12 +1367,13 @@ port=3456 [system.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -1368,9 +1381,16 @@ width=32 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side +[system.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.tsunami] type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart eventq_index=0 intrctrl=system.intrctrl system=system @@ -1483,12 +1503,12 @@ dma_write_delay=0 dma_write_factor=0 eventq_index=0 hardware_address=00:90:00:00:00:01 +host=system.tsunami.pchip intr_delay=10000000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.tsunami rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -1498,9 +1518,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.master[28] dma=system.iobus.slave[2] -pio=system.iobus.master[27] +pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake @@ -1933,14 +1952,13 @@ config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 eventq_index=0 +host=system.tsunami.pchip io_shift=0 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.tsunami system=system -config=system.iobus.master[26] dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1960,25 +1978,20 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +conf_base=8804649402368 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 +pci_dma_base=0 +pci_mem_base=8796093022208 +pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 +platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.master[1] -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 7f9e2b29d..f71ac7b91 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 09:01:06 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Dec 4 2015 10:28:58 +gem5 started Dec 4 2015 10:42:11 +gem5 executing on e104799-lin, pid 22878 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /work/gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 133655000 -Exiting @ tick 1904437574000 because m5_exit instruction encountered +info: Launching CPU 1 @ 179187500 +Exiting @ tick 1922761887500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 091040252..123211008 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.922762 # Nu sim_ticks 1922761887500 # Number of ticks simulated final_tick 1922761887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132982 # Simulator instruction rate (inst/s) -host_op_rate 132982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4507220686 # Simulator tick rate (ticks/s) -host_mem_usage 384024 # Number of bytes of host memory used -host_seconds 426.60 # Real time elapsed on the host +host_inst_rate 136693 # Simulator instruction rate (inst/s) +host_op_rate 136693 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4632993573 # Simulator tick rate (ticks/s) +host_mem_usage 339884 # Number of bytes of host memory used +host_seconds 415.02 # Real time elapsed on the host sim_insts 56729467 # Number of instructions simulated sim_ops 56729467 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -111,8 +111,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 123171 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 317967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37910 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29466 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 24871 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see @@ -168,14 +168,14 @@ system.physmem.wrQLenPdf::21 6400 # Wh system.physmem.wrQLenPdf::22 6805 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 8203 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 8579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8953 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 9138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 8272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 8747 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 6829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6099 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 325 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 232 # What write queue length does an incoming req see @@ -207,20 +207,20 @@ system.physmem.wrQLenPdf::60 52 # Wh system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 45 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 522.630582 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.337054 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 410.684018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14917 22.83% 22.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11339 17.36% 40.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5448 8.34% 48.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 65324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 522.654583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.374945 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.670236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14914 22.83% 22.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11338 17.36% 40.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5449 8.34% 48.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2879 4.41% 52.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2603 3.98% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1650 2.53% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3828 5.86% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2604 3.99% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1649 2.52% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3829 5.86% 65.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1203 1.84% 67.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21460 32.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21459 32.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65324 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5559 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 73.810757 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 2831.423020 # Reads before turning the bus around for writes @@ -271,12 +271,12 @@ system.physmem.wrPerTurnAround::220-223 1 0.02% 99.96% # Wr system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5559 # Writes before turning the bus around for reads -system.physmem.totQLat 4492977750 # Total ticks spent queuing -system.physmem.totMemAccLat 12186571500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4493146250 # Total ticks spent queuing +system.physmem.totMemAccLat 12186740000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2051625000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10949.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10950.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29699.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29700.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.66 # Average system read bandwidth in MiByte/s @@ -287,39 +287,39 @@ system.physmem.busUtilRead 0.11 # Da system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.48 # Average write queue length when enqueuing -system.physmem.readRowHits 369433 # Number of row buffer hits during reads -system.physmem.writeRowHits 98707 # Number of row buffer hits during writes +system.physmem.readRowHits 369435 # Number of row buffer hits during reads +system.physmem.writeRowHits 98708 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.14 # Row buffer hit rate for writes system.physmem.avgGap 3603301.16 # Average gap between requests system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247242240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134904000 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 247227120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134895750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1602939000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 400671360 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63449600445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097998572000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289419261125 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.608464 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1826410636250 # Time in different power states +system.physmem_0.actBackEnergy 63448746300 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1097999321250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289419132860 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.608398 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1826411929500 # Time in different power states system.physmem_0.memoryStateTime::REF 64205180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32144391250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32143098000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246629880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134569875 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 246622320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134565750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1597596000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 397288800 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62800369875 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1098568064250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289329850760 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.561968 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1827364141250 # Time in different power states +system.physmem_1.actBackEnergy 62799950070 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1098568432500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289329787520 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.561935 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1827364757000 # Time in different power states system.physmem_1.memoryStateTime::REF 64205180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31190872500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31190256750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu0.branchPred.lookups 16164803 # Number of BP lookups system.cpu0.branchPred.condPredicted 14134057 # Number of conditional branches predicted @@ -366,11 +366,11 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.numCycles 147492353 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26474453 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.icacheStallCycles 26474452 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 70295181 # Number of instructions fetch has processed system.cpu0.fetch.Branches 16164803 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 6131250 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 112661982 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.Cycles 112660359 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 1056864 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 660 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 29689 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -378,12 +378,12 @@ system.cpu0.fetch.PendingTrapStallCycles 929577 # Nu system.cpu0.fetch.PendingQuiesceStallCycles 461648 # Number of stall cycles due to pending quiesce instructions system.cpu0.fetch.IcacheWaitRetryStallCycles 350 # Number of stall cycles due to full MSHR system.cpu0.fetch.CacheLines 8123308 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 229144 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 141086791 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.498241 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.734215 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 141085167 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.498246 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.734224 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 127943316 90.68% 90.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 127941692 90.68% 90.68% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 834789 0.59% 91.28% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 1813592 1.29% 92.56% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 779670 0.55% 93.11% # Number of instructions fetched each cycle (Total) @@ -395,35 +395,35 @@ system.cpu0.fetch.rateDist::8 5070041 3.59% 100.00% # Nu system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 141086791 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 141085167 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.109598 # Number of branch fetches per cycle system.cpu0.fetch.rate 0.476602 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21397284 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108971969 # Number of cycles decode is blocked +system.cpu0.decode.IdleCycles 21397283 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108970346 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 8457985 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 1766417 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 493135 # Number of cycles decode is squashing system.cpu0.decode.BranchResolved 516601 # Number of times decode resolved a branch system.cpu0.decode.BranchMispred 35757 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61523411 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 61523415 # Number of instructions handled by decode system.cpu0.decode.SquashedInsts 108836 # Number of squashed instructions handled by decode system.cpu0.rename.SquashCycles 493135 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22231623 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 77943277 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19950150 # count of cycles rename stalled for serializing inst +system.cpu0.rename.IdleCycles 22231622 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 77943613 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19948481 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 9304003 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11164601 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59421423 # Number of instructions processed by rename +system.cpu0.rename.UnblockCycles 11164311 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59421431 # Number of instructions processed by rename system.cpu0.rename.ROBFullEvents 199471 # Number of times rename has blocked due to ROB full system.cpu0.rename.IQFullEvents 2023547 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 224739 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7186522 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39708138 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72284773 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72145342 # Number of integer rename lookups +system.cpu0.rename.LQFullEvents 224227 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7186744 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39708144 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72284783 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72145352 # Number of integer rename lookups system.cpu0.rename.fp_rename_lookups 129802 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 34979364 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4728766 # Number of HB maps that are undone due to squashing +system.cpu0.rename.UndoneMaps 4728772 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 1463848 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 211077 # count of temporary serializing insts renamed system.cpu0.rename.skidInsts 12544775 # count of insts added to the skid buffer @@ -431,30 +431,30 @@ system.cpu0.memDep0.insertedLoads 9257817 # Nu system.cpu0.memDep0.insertedStores 6153108 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 1360057 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 1005705 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53010072 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsAdded 53010076 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 1876155 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52220775 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 52220777 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 51551 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6501427 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2875305 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedInstsExamined 6501431 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2875308 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 1291728 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 141086791 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.370132 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.087511 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 141085167 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.370137 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.087516 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 119618317 84.78% 84.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9300566 6.59% 91.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3865351 2.74% 94.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 119616695 84.78% 84.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9300562 6.59% 91.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3865352 2.74% 94.12% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::3 2730572 1.94% 96.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2821391 2.00% 98.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1375833 0.98% 99.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 902269 0.64% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2821393 2.00% 98.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1375831 0.98% 99.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 902270 0.64% 99.67% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 360488 0.26% 99.92% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 112004 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 141086791 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 141085167 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 182068 18.38% 18.38% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 2 0.00% 18.38% # attempts to use FU when none available @@ -490,7 +490,7 @@ system.cpu0.iq.fu_full::MemWrite 337015 34.02% 100.00% # at system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35835166 68.62% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35835168 68.62% 68.63% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 56519 0.11% 68.74% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 28571 0.05% 68.79% # Type of FU issued @@ -523,17 +523,17 @@ system.cpu0.iq.FU_type_0::MemRead 9523186 18.24% 87.03% # Ty system.cpu0.iq.FU_type_0::MemWrite 5952100 11.40% 98.43% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 819570 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52220775 # Type of FU issued +system.cpu0.iq.FU_type_0::total 52220777 # Type of FU issued system.cpu0.iq.rate 0.354058 # Inst issue rate system.cpu0.iq.fu_busy_cnt 990706 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.018971 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 245999962 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61137242 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_reads 245998342 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61137250 # Number of integer instruction queue writes system.cpu0.iq.int_inst_queue_wakeup_accesses 50831283 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 570635 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 267757 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 262095 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52900144 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 52900146 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 307557 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 581308 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -544,13 +544,13 @@ system.cpu0.iew.lsq.thread0.squashedStores 500436 # system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 18736 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 408208 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 408207 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 493135 # Number of cycles IEW is squashing system.cpu0.iew.iewBlockCycles 74418027 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 1058724 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58259516 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 116557 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispatchedInsts 58259520 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 116565 # Number of squashed instructions skipped by dispatch system.cpu0.iew.iewDispLoadInsts 9257817 # Number of dispatched load instructions system.cpu0.iew.iewDispStoreInsts 6153108 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 1657861 # Number of dispatched non-speculative instructions @@ -562,7 +562,7 @@ system.cpu0.iew.predictedNotTakenIncorrect 351909 # system.cpu0.iew.branchMispredicts 505215 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 51717296 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 9230924 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 503478 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecSquashedInsts 503480 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 3373289 # number of nop insts executed system.cpu0.iew.exec_refs 15132335 # number of memory reference insts executed @@ -571,22 +571,22 @@ system.cpu0.iew.exec_stores 5901411 # Nu system.cpu0.iew.exec_rate 0.350644 # Inst execution rate system.cpu0.iew.wb_sent 51207379 # cumulative count of insts sent to commit system.cpu0.iew.wb_count 51093378 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26334207 # num instructions producing a value -system.cpu0.iew.wb_consumers 36473944 # num instructions consuming a value +system.cpu0.iew.wb_producers 26334208 # num instructions producing a value +system.cpu0.iew.wb_consumers 36473947 # num instructions consuming a value system.cpu0.iew.wb_rate 0.346414 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.722001 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 6824839 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 6824843 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 584427 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 463110 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 139882457 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.366962 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.256012 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 139880833 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.366966 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.256019 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 121750983 87.04% 87.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7187616 5.14% 92.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 121749360 87.04% 87.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7187615 5.14% 92.18% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::2 3944064 2.82% 95.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2051217 1.47% 96.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1611428 1.15% 97.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2051216 1.47% 96.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1611429 1.15% 97.61% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::5 577022 0.41% 98.03% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 437359 0.31% 98.34% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::7 434985 0.31% 98.65% # Number of insts commited each cycle @@ -594,7 +594,7 @@ system.cpu0.commit.committed_per_cycle::8 1887783 1.35% 100.00% # N system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 139882457 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 139880833 # Number of insts commited each cycle system.cpu0.commit.committedInsts 51331530 # Number of instructions committed system.cpu0.commit.committedOps 51331530 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed @@ -641,10 +641,10 @@ system.cpu0.commit.op_class_0::IprAccess 819569 1.60% 100.00% # Cl system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::total 51331530 # Class of committed instruction system.cpu0.commit.bw_lim_events 1887783 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 195950193 # The number of ROB reads -system.cpu0.rob.rob_writes 117511428 # The number of ROB writes +system.cpu0.rob.rob_reads 195948573 # The number of ROB reads +system.cpu0.rob.rob_writes 117511436 # The number of ROB writes system.cpu0.timesIdled 525574 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6405562 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 6407186 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 3698031423 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.committedInsts 48384795 # Number of Instructions Simulated system.cpu0.committedOps 48384795 # Number of Ops (including micro ops) Simulated @@ -659,12 +659,12 @@ system.cpu0.fp_regfile_writes 130249 # nu system.cpu0.misc_regfile_reads 1711265 # number of misc regfile reads system.cpu0.misc_regfile_writes 819270 # number of misc regfile writes system.cpu0.dcache.tags.replacements 1282737 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.160384 # Cycle average of tags in use +system.cpu0.dcache.tags.tagsinuse 506.160385 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 10524244 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 1283249 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 8.201249 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.160384 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.160385 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988595 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988595 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -698,18 +698,18 @@ system.cpu0.dcache.demand_misses::cpu0.data 3363608 # system.cpu0.dcache.demand_misses::total 3363608 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 3363608 # number of overall misses system.cpu0.dcache.overall_misses::total 3363608 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54837998000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54837998000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114303059042 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114303059042 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54836064000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54836064000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114300477543 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114300477543 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389087500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 389087500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45510000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 45510000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 169141057042 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 169141057042 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 169141057042 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 169141057042 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 169136541543 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 169136541543 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 169136541543 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 169136541543 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 8078505 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8078505 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5447584 # number of WriteReq accesses(hits+misses) @@ -734,23 +734,23 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248676 system.cpu0.dcache.demand_miss_rate::total 0.248676 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248676 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.248676 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34387.118782 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34387.118782 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64618.778654 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64618.778654 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34385.906034 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34385.906034 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64617.319259 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64617.319259 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50285.603151 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50285.603151 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50285.603151 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50285.603151 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6995611 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50284.260694 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50284.260694 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50284.260694 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50284.260694 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6995201 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 14546 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 119540 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119539 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 103 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.521089 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.518149 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 141.223301 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed @@ -784,24 +784,24 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10126 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10126 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17171 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17171 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43466083500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43466083500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18236016784 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18236016784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43465523500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43465523500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18235926784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18235926784 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 187455000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 187455000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42654000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42654000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61702100284 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61702100284 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61702100284 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 61702100284 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563410000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563410000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61701450284 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61701450284 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61701450284 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61701450284 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1562510000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1562510000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2299016000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2299016000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3862426000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3862426000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3861526000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3861526000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125677 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125677 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048825 # mshr miss rate for WriteReq accesses @@ -814,24 +814,24 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094725 system.cpu0.dcache.demand_mshr_miss_rate::total 0.094725 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.094725 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.790900 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.790900 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.382401 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.382401 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.239329 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.239329 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.044026 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.044026 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48157.360945 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48157.360945 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48157.360945 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48157.360945 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221917.672108 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221917.672108 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48156.853632 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48156.853632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48156.853632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48156.853632 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221789.921930 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221789.921930 # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851 # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224938.908625 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224938.908625 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224886.494671 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224886.494671 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 908501 # number of replacements system.cpu0.icache.tags.tagsinuse 508.069795 # Cycle average of tags in use @@ -861,12 +861,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 954611 # system.cpu0.icache.demand_misses::total 954611 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 954611 # number of overall misses system.cpu0.icache.overall_misses::total 954611 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14636609987 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14636609987 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14636609987 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14636609987 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14636609987 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14636609987 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14637521487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14637521487 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14637521487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14637521487 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14637521487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14637521487 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 8123307 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 8123307 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 8123307 # number of demand (read+write) accesses @@ -879,12 +879,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117515 system.cpu0.icache.demand_miss_rate::total 0.117515 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117515 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.117515 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15332.538581 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15332.538581 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15332.538581 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15332.538581 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15332.538581 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15332.538581 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15333.493420 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15333.493420 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15333.493420 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15333.493420 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15333.493420 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15333.493420 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 8572 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 278 # number of cycles access was blocked @@ -907,24 +907,24 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 909320 system.cpu0.icache.demand_mshr_misses::total 909320 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 909320 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 909320 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12934939493 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12934939493 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12934939493 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12934939493 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12934939493 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12934939493 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12935759993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12935759993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12935759993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12935759993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12935759993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12935759993 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111940 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.111940 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.111940 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14224.848780 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14224.848780 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14224.848780 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14225.751103 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14225.751103 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14225.751103 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.branchPred.lookups 3578846 # Number of BP lookups system.cpu1.branchPred.condPredicted 3133511 # Number of conditional branches predicted @@ -1263,12 +1263,12 @@ system.cpu1.fp_regfile_writes 51516 # nu system.cpu1.misc_regfile_reads 503472 # number of misc regfile reads system.cpu1.misc_regfile_writes 210349 # number of misc regfile writes system.cpu1.dcache.tags.replacements 98962 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.970751 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 486.970752 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 2466427 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 99271 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 24.845393 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 1048837181500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.970751 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.970752 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951115 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.951115 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 309 # Occupied blocks per task id @@ -1543,40 +1543,34 @@ system.iobus.trans_dist::ReadResp 7371 # Tr system.iobus.trans_dist::WriteReq 54609 # Transaction distribution system.iobus.trans_dist::WriteResp 54609 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 40504 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 123960 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 73842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2735474 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 12353500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 448000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 827500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1590,16 +1584,10 @@ system.iobus.reqLayer24.occupancy 2829000 # La system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 5954500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 217500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 87000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 87000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215061495 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 131500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215061495 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 27447000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) @@ -1702,14 +1690,14 @@ system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955 system.iocache.overall_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 345304 # number of replacements -system.l2c.tags.tagsinuse 65190.216948 # Cycle average of tags in use +system.l2c.tags.tagsinuse 65190.216881 # Cycle average of tags in use system.l2c.tags.total_refs 3990482 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 410468 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 9.721786 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 11177481000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53120.456427 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5260.305215 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6531.960123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 53120.456317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5260.305264 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6531.960119 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 208.754945 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 68.740237 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.810554 # Average percentage of cache occupancy @@ -1787,25 +1775,25 @@ system.l2c.UpgradeReq_miss_latency::total 21371000 # n system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2842500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 568500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 3411000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 16040827500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 16040737500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 1166717500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 17207545000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1816563500 # number of ReadCleanReq miss cycles +system.l2c.ReadExReq_miss_latency::total 17207455000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1817383500 # number of ReadCleanReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu1.inst 219865000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 2036428500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 33893464500 # number of ReadSharedReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 2037248500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 33892904500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 116817000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 34010281500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1816563500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 49934292000 # number of demand (read+write) miss cycles +system.l2c.ReadSharedReq_miss_latency::total 34009721500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1817383500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 49933642000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 219865000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 1283534500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 53254255000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1816563500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 49934292000 # number of overall miss cycles +system.l2c.demand_miss_latency::total 53254425000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1817383500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 49933642000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 219865000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 1283534500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 53254255000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 53254425000 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 820126 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 820126 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 859282 # number of WritebackClean accesses(hits+misses) @@ -1866,25 +1854,25 @@ system.l2c.UpgradeReq_avg_miss_latency::total 5500.900901 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6767.857143 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1289.115646 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 3961.672474 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139638.451695 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139637.668228 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 159170.190996 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 140809.998036 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133649.462919 # average ReadCleanReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 140809.261563 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133709.792525 # average ReadCleanReq miss latency system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135052.211302 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 133799.507227 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124162.800026 # average ReadSharedReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 133853.383706 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124160.748564 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140913.148372 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 124213.515093 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 133649.462919 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 128746.401960 # average overall miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 124211.469842 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 133709.792525 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 128744.726054 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 135052.211302 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 157315.173428 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 129500.241958 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 133649.462919 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 128746.401960 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 129500.655353 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 133709.792525 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 128744.726054 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 135052.211302 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 157315.173428 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 129500.241958 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 129500.655353 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1946,34 +1934,34 @@ system.l2c.UpgradeReq_mshr_miss_latency::total 278688500 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29951500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 31656500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 61608000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14892087500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14891997500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1093417500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 15985505000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1680522000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 15985415000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1681342000 # number of ReadCleanReq MSHR miss cycles system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 201578500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1882100500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31173569000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1882920500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31173009000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 108527000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 31282096000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1680522000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 46065656500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 31281536000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1681342000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 46065006500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 201578500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 1201944500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 49149701500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1680522000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 46065656500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 49149871500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1681342000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 46065006500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 201578500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 1201944500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 49149701500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1475287500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::total 49149871500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1474387500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28274500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1503562000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1502662000 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2182363000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 649671500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 2832034500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3657650500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3656750500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 677946000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4335596500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4334696500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941457 # mshr miss rate for UpgradeReq accesses @@ -2007,34 +1995,34 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129638.451695 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129637.668228 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.998036 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average ReadCleanReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.261563 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average ReadCleanReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123814.255641 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114198.936903 # average ReadSharedReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123868.199461 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114196.885440 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114249.542558 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118771.835761 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114247.497306 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118770.159856 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 119524.577467 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118771.835761 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119524.990881 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118770.159856 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 119524.577467 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209409.155429 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::total 119524.990881 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209281.405252 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208973.175817 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208848.088951 # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213013.249083 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212960.835129 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214082.386925 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214037.946869 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7195 # Transaction distribution system.membus.trans_dist::ReadResp 296301 # Transaction distribution @@ -2082,7 +2070,7 @@ system.membus.reqLayer1.occupancy 1357207403 # La system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 98500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2187694355 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2187691105 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 69834733 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -2190,11 +2178,11 @@ system.cpu0.kern.ipl_good::22 1928 1.48% 50.79% # nu system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 63870 49.07% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 130171 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865607975500 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1865608787500 97.03% 97.03% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 63996500 0.00% 97.03% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 577908500 0.03% 97.06% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 88293000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56422873000 2.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56422061000 2.93% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1922761046500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index 1425d639e..195c1d872 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 2be1ffca4..aa0a7c43b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/work/gem5/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/work/gem5/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,9 +26,10 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/work/gem5/dist/binaries/ts_osfpal +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -171,6 +172,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -187,6 +189,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -518,6 +521,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -534,6 +538,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -567,6 +572,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -583,6 +589,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -598,12 +605,13 @@ size=4194304 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -611,6 +619,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -643,7 +658,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -666,7 +681,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -689,10 +704,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.tsunami.pciconfig.pio -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] @@ -701,6 +715,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=false @@ -717,7 +732,8 @@ system=system tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 -cpu_side=system.iobus.master[29] +writeback_clean=false +cpu_side=system.iobus.master[27] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -852,7 +868,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -865,7 +881,7 @@ port=3456 [system.tsunami] type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart eventq_index=0 intrctrl=system.intrctrl system=system @@ -978,12 +994,12 @@ dma_write_delay=0 dma_write_factor=0 eventq_index=0 hardware_address=00:90:00:00:00:01 +host=system.tsunami.pchip intr_delay=10000000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.tsunami rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -993,9 +1009,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.master[28] dma=system.iobus.slave[2] -pio=system.iobus.master[27] +pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake @@ -1428,14 +1443,13 @@ config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 eventq_index=0 +host=system.tsunami.pchip io_shift=0 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.tsunami system=system -config=system.iobus.master[26] dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1455,25 +1469,20 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +conf_base=8804649402368 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 +pci_dma_base=0 +pci_mem_base=8796093022208 +pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 +platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.master[1] -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 25160cf8e..a50933284 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:27:15 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Dec 4 2015 10:28:58 +gem5 started Dec 4 2015 10:48:09 +gem5 executing on e104799-lin, pid 23716 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /work/gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1861005569500 because m5_exit instruction encountered +Exiting @ tick 1875760362000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index a3cafb881..f6eb98841 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.875760 # Nu sim_ticks 1875760362000 # Number of ticks simulated final_tick 1875760362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133605 # Simulator instruction rate (inst/s) -host_op_rate 133605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4730094094 # Simulator tick rate (ticks/s) -host_mem_usage 378388 # Number of bytes of host memory used -host_seconds 396.56 # Real time elapsed on the host +host_inst_rate 137394 # Simulator instruction rate (inst/s) +host_op_rate 137394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4864266040 # Simulator tick rate (ticks/s) +host_mem_usage 335280 # Number of bytes of host memory used +host_seconds 385.62 # Real time elapsed on the host sim_insts 52982087 # Number of instructions simulated sim_ops 52982087 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,10 +101,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 117574 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 315451 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 35937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23972 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -154,16 +154,16 @@ system.physmem.wrQLenPdf::17 3242 # Wh system.physmem.wrQLenPdf::18 4193 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5460 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7856 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 8316 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 9450 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 8577 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 8739 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 7869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6430 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6478 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 396 # What write queue length does an incoming req see @@ -197,23 +197,23 @@ system.physmem.wrQLenPdf::60 43 # Wh system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.237934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 330.496904 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 411.905259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13738 22.09% 22.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10541 16.95% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 62200 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.255177 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 330.514254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 411.900658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13736 22.08% 22.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10542 16.95% 39.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 4957 7.97% 47.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2730 4.39% 51.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2467 3.97% 55.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1593 2.56% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3726 5.99% 63.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1160 1.86% 65.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21290 34.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2726 4.38% 51.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2468 3.97% 55.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1593 2.56% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3731 6.00% 63.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1159 1.86% 65.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21288 34.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62200 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5203 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 77.574092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2240.859567 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2240.859569 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-4095 5198 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes @@ -262,12 +262,12 @@ system.physmem.wrPerTurnAround::192-195 1 0.02% 99.90% # Wr system.physmem.wrPerTurnAround::196-199 2 0.04% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5203 # Writes before turning the bus around for reads -system.physmem.totQLat 4177241750 # Total ticks spent queuing -system.physmem.totMemAccLat 11745266750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4177261250 # Total ticks spent queuing +system.physmem.totMemAccLat 11745286250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2018140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10349.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10349.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29099.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29099.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s @@ -279,44 +279,44 @@ system.physmem.busUtilWrite 0.03 # Da system.physmem.avgRdQLen 2.11 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing system.physmem.readRowHits 363742 # Number of row buffer hits during reads -system.physmem.writeRowHits 95234 # Number of row buffer hits during writes +system.physmem.writeRowHits 95236 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate 81.00 # Row buffer hit rate for writes system.physmem.avgGap 3598032.64 # Average gap between requests system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 232553160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126889125 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 232485120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126852000 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1577284800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 378496800 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61473435525 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1071528687000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1257832501770 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.574130 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1782381530500 # Time in different power states +system.physmem_0.actBackEnergy 61464969315 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1071536113500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1257831356895 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.573520 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1782393910500 # Time in different power states system.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30737512000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30725132000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 237693960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129694125 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 237746880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129723000 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1570966800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 383233680 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61441070355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1071557085750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1257834900030 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.575404 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1782427454500 # Time in different power states +system.physmem_1.actBackEnergy 61443954270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1071554556000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1257835335990 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.575636 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1782423204750 # Time in different power states system.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30691601750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30695851500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17943789 # Number of BP lookups -system.cpu.branchPred.condPredicted 15652252 # Number of conditional branches predicted +system.cpu.branchPred.lookups 17943792 # Number of BP lookups +system.cpu.branchPred.condPredicted 15652255 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 367731 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11526734 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5853564 # Number of BTB hits +system.cpu.branchPred.BTBLookups 11526736 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5853565 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 50.782503 # BTB Hit Percentage system.cpu.branchPred.usedRAS 912127 # Number of times the RAS was used to get a target. @@ -357,98 +357,98 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.numCycles 154312476 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29589684 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78040473 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17943789 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6765691 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115537778 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 29589797 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78040481 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17943792 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6765692 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115536731 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1228012 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 1868 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 28793 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1263154 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 470523 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8990852 # Number of cache lines fetched +system.cpu.fetch.CacheLines 8990853 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 270749 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 147506364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.529065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.785295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 147505430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.529069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.785300 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132982346 90.15% 90.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132981412 90.15% 90.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 927735 0.63% 90.78% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1956667 1.33% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 905254 0.61% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2772061 1.88% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 613974 0.42% 95.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 905252 0.61% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772062 1.88% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 613973 0.42% 95.02% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 725766 0.49% 95.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009556 0.68% 96.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5613005 3.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009557 0.68% 96.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5613006 3.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 147506364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 147505430 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.116282 # Number of branch fetches per cycle system.cpu.fetch.rate 0.505730 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23997501 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 111590886 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9436404 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1909016 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 23997616 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 111589834 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9436408 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1909015 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 572556 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 581578 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 41802 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68051611 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 68051619 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 132447 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 572556 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24921357 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78408678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21682628 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10334897 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11586246 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65629261 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 24921470 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78409233 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21681516 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10334902 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11585751 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65629269 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 204540 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2094496 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 230878 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7314004 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43742271 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79592757 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79412100 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 2094492 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 230558 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7313834 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43742274 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79592762 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79412105 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 168205 # Number of floating rename lookups system.cpu.rename.CommittedMaps 38181578 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5560685 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5560688 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1689598 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 239417 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13566674 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 13566650 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 10375081 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 6952014 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1510108 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1095838 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58467931 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2138048 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57495227 # Number of instructions issued +system.cpu.iq.iqInstsAdded 58467936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2138049 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57495232 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 57340 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7623887 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 7623893 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3407756 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1476848 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 147506364 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.389781 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.113625 # Number of insts issued each cycle +system.cpu.iq.iqSquashedNonSpecRemoved 1476849 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147505430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.389784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.113628 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 123908569 84.00% 84.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10178941 6.90% 90.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4283785 2.90% 93.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3020720 2.05% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3080791 2.09% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1492273 1.01% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1011784 0.69% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 404685 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124816 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 123907632 84.00% 84.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10178942 6.90% 90.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4283791 2.90% 93.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3020718 2.05% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3080788 2.09% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1492274 1.01% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011781 0.69% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404686 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124818 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 147506364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147505430 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210138 18.65% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210139 18.65% 18.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 18.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 18.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.65% # attempts to use FU when none available @@ -477,12 +477,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 541379 48.04% 66.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375311 33.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 541380 48.04% 66.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375310 33.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7282 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39050505 67.92% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39050510 67.92% 67.93% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 61871 0.11% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued @@ -515,17 +515,17 @@ system.cpu.iq.FU_type_0::MemRead 10660993 18.54% 86.66% # Ty system.cpu.iq.FU_type_0::MemWrite 6723341 11.69% 98.35% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 949046 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57495227 # Type of FU issued +system.cpu.iq.FU_type_0::total 57495232 # Type of FU issued system.cpu.iq.rate 0.372590 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1126828 # FU busy when requested +system.cpu.iq.fu_busy_cnt 1126829 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019599 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262968198 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67912529 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55849103 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 262967275 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67912541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55849108 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 712787 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 336322 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 328951 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58232052 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 58232058 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 382721 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 635480 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -536,57 +536,57 @@ system.cpu.iew.lsq.thread0.squashedStores 573763 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 460620 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 460617 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 572556 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74664170 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1189821 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64295080 # Number of instructions dispatched to IQ +system.cpu.iew.iewBlockCycles 74664181 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1190404 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64295088 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 139940 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 10375081 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 6952014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890560 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43853 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 943025 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispNonSpecInsts 1890561 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43857 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 943603 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 177030 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 409389 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 586419 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56909008 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 56909013 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 10319700 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 586218 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3689101 # number of nop insts executed +system.cpu.iew.exec_nop 3689103 # number of nop insts executed system.cpu.iew.exec_refs 16987647 # number of memory reference insts executed -system.cpu.iew.exec_branches 8974026 # Number of branches executed +system.cpu.iew.exec_branches 8974028 # Number of branches executed system.cpu.iew.exec_stores 6667947 # Number of stores executed system.cpu.iew.exec_rate 0.368791 # Inst execution rate -system.cpu.iew.wb_sent 56315336 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56178054 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28756989 # num instructions producing a value -system.cpu.iew.wb_consumers 39942344 # num instructions consuming a value +system.cpu.iew.wb_sent 56315341 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56178059 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28756993 # num instructions producing a value +system.cpu.iew.wb_consumers 39942343 # num instructions consuming a value system.cpu.iew.wb_rate 0.364054 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719962 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8005033 # The number of squashed insts skipped by commit +system.cpu.iew.wb_fanout 0.719963 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8005041 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 661200 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 537292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146103821 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.384473 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.286210 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 146102886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.384475 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.286214 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 126321778 86.46% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7855301 5.38% 91.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4275066 2.93% 94.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2236699 1.53% 96.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1745226 1.19% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615725 0.42% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 478401 0.33% 98.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 477554 0.33% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2098071 1.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 126320849 86.46% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7855297 5.38% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4275062 2.93% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2236701 1.53% 96.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1745224 1.19% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615726 0.42% 97.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 478400 0.33% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 477555 0.33% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2098072 1.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146103821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 146102886 # Number of insts commited each cycle system.cpu.commit.committedInsts 56172911 # Number of instructions committed system.cpu.commit.committedOps 56172911 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -632,11 +632,11 @@ system.cpu.commit.op_class_0::MemWrite 6384206 11.37% 98.31% # Cl system.cpu.commit.op_class_0::IprAccess 949045 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 56172911 # Class of committed instruction -system.cpu.commit.bw_lim_events 2098071 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 207934044 # The number of ROB reads -system.cpu.rob.rob_writes 129754094 # The number of ROB writes -system.cpu.timesIdled 581359 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6806112 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 2098072 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 207933116 # The number of ROB reads +system.cpu.rob.rob_writes 129754111 # The number of ROB writes +system.cpu.timesIdled 581360 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6807046 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 3597208249 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 52982087 # Number of Instructions Simulated system.cpu.committedOps 52982087 # Number of Ops (including micro ops) Simulated @@ -644,8 +644,8 @@ system.cpu.cpi 2.912541 # CP system.cpu.cpi_total 2.912541 # CPI: Total CPI of All Threads system.cpu.ipc 0.343343 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.343343 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74569026 # number of integer regfile reads -system.cpu.int_regfile_writes 40527111 # number of integer regfile writes +system.cpu.int_regfile_reads 74569031 # number of integer regfile reads +system.cpu.int_regfile_writes 40527114 # number of integer regfile writes system.cpu.fp_regfile_reads 166982 # number of floating regfile reads system.cpu.fp_regfile_writes 167538 # number of floating regfile writes system.cpu.misc_regfile_reads 1985520 # number of misc regfile reads @@ -690,18 +690,18 @@ system.cpu.dcache.demand_misses::cpu.data 3754990 # n system.cpu.dcache.demand_misses::total 3754990 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3754990 # number of overall misses system.cpu.dcache.overall_misses::total 3754990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57215692000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57215692000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116805325608 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116805325608 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57215969500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57215969500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116801916611 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116801916611 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447608000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 447608000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 892500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 892500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 174021017608 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 174021017608 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 174021017608 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 174021017608 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 174017886111 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 174017886111 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 174017886111 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 174017886111 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 9036240 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9036240 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6147794 # number of WriteReq accesses(hits+misses) @@ -726,23 +726,23 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.247299 system.cpu.dcache.demand_miss_rate::total 0.247299 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.247299 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.247299 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.802822 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.802822 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59669.079344 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59669.079344 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.957208 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.957208 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59667.337885 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59667.337885 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46343.936364 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46343.936364 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7142845 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.102408 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46343.102408 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.102408 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46343.102408 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7142391 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 5288 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 134029 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 134027 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.293280 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.290688 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 188.857143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,24 +776,24 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44560858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 44560858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18438060220 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18438060220 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44560579000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 44560579000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18438109720 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18438109720 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229318500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229318500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 863500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 863500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62998918220 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62998918220 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62998918220 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62998918220 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529906000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529906000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62998688720 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62998688720 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62998688720 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62998688720 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529006000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529006000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154205500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154205500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3684111500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3684111500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683211500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683211500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121050 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121050 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047283 # mshr miss rate for WriteReq accesses @@ -806,30 +806,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091183 system.cpu.dcache.demand_mshr_miss_rate::total 0.091183 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091183 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.264433 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.264433 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.819873 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.819873 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.009367 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.009367 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.990158 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.990158 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12727.895876 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12727.895876 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29775.862069 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29775.862069 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.287591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.287591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.287591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.287591 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220765.656566 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220765.656566 # average ReadReq mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.121830 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.121830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.121830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.121830 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220635.786436 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220635.786436 # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224443.165243 # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224443.165243 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222901.228219 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222901.228219 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222846.775169 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222846.775169 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1036098 # number of replacements +system.cpu.icache.tags.replacements 1036100 # number of replacements system.cpu.icache.tags.tagsinuse 507.835115 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7900594 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1036606 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.621598 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 7900592 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1036608 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.621581 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 507.835115 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy @@ -839,44 +839,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 72 system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10027828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10027828 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7900595 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7900595 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7900595 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7900595 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7900595 # number of overall hits -system.cpu.icache.overall_hits::total 7900595 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1090254 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1090254 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1090254 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1090254 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1090254 # number of overall misses -system.cpu.icache.overall_misses::total 1090254 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16373491482 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16373491482 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16373491482 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16373491482 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16373491482 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16373491482 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8990849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8990849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8990849 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8990849 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8990849 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8990849 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 10027831 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10027831 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7900593 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7900593 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7900593 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7900593 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7900593 # number of overall hits +system.cpu.icache.overall_hits::total 7900593 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1090257 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1090257 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1090257 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1090257 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1090257 # number of overall misses +system.cpu.icache.overall_misses::total 1090257 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16373914482 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16373914482 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16373914482 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16373914482 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16373914482 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16373914482 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8990850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8990850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8990850 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8990850 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8990850 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8990850 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121263 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.121263 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.121263 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.121263 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.121263 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.121263 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.052199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15018.052199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.052199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15018.052199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.052199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15018.052199 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.398856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15018.398856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.398856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15018.398856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.398856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15018.398856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 11165 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 304 # number of cycles access was blocked @@ -885,48 +885,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 36.726974 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1036098 # number of writebacks -system.cpu.icache.writebacks::total 1036098 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53275 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53275 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53275 # 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number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115337 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.115337 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.115337 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.680280 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.680280 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.922470 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.922470 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.922470 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.922470 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.922470 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.922470 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 338547 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65279.196063 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4167773 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65279.195987 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4167777 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 403714 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.323578 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.323588 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 9186443000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53290.316378 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5240.255410 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6748.624275 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 53290.316261 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5240.255495 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6748.624231 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.813146 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.079960 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.102976 # Average percentage of cache occupancy @@ -938,28 +938,28 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3334 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2423 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55435 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39707239 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39707239 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 39707271 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39707271 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 841132 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 841132 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1035547 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1035547 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1035549 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1035549 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 185951 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 185951 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1021689 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1021689 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1021691 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1021691 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827089 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 827089 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1021689 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1021691 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1013040 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2034729 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1021689 # number of overall hits +system.cpu.l2cache.demand_hits::total 2034731 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1021691 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1013040 # number of overall hits -system.cpu.l2cache.overall_hits::total 2034729 # number of overall hits +system.cpu.l2cache.overall_hits::total 2034731 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 101 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 101 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 7 # number of SCUpgradeReq misses @@ -980,38 +980,38 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 815500 system.cpu.l2cache.UpgradeReq_miss_latency::total 815500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 243500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 243500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16101364500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16101364500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2016473000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2016473000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34005457500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 34005457500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2016473000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 50106822000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 52123295000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2016473000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 50106822000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 52123295000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16101413500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16101413500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2016727500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2016727500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34005178500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 34005178500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2016727500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 50106592000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 52123319500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2016727500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 50106592000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 52123319500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 841132 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 841132 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1035547 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1035547 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1035549 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1035549 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 130 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 29 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 301462 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 301462 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1036663 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1036663 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1036665 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1036665 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1100949 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 1100949 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1036663 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1036665 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1402411 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2439074 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1036663 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2439076 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1036665 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1402411 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2439074 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2439076 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.776923 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.776923 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.241379 # miss rate for SCUpgradeReq accesses @@ -1032,18 +1032,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8074.257426 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8074.257426 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139392.477773 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139392.477773 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134664.952584 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134664.952584 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124170.954137 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124170.954137 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134664.952584 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128686.579124 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 128907.974626 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134664.952584 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128686.579124 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 128907.974626 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139392.901975 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139392.901975 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134681.948711 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134681.948711 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124169.935368 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124169.935368 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134681.948711 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128685.988427 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 128908.035217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134681.948711 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128685.988427 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 128908.035217 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1086,24 +1086,24 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7246500 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7246500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 500000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 500000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14946254500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14946254500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1866612000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1866612000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31277372000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31277372000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1866612000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46223626500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 48090238500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1866612000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46223626500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 48090238500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443206500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443206500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14946303500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14946303500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1866866500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1866866500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31277093000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31277093000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1866866500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46223396500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 48090263000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1866866500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46223396500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 48090263000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442306500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442306500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043789000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043789000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486995500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486995500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486095500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486095500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.776923 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.776923 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.241379 # mshr miss rate for SCUpgradeReq accesses @@ -1124,72 +1124,72 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71747.524752 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71747.524752 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71428.571429 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71428.571429 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.477773 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.477773 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124665.197355 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124665.197355 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114209.347842 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114209.347842 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208254.906205 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208254.906205 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.901975 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.901975 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124682.194617 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124682.194617 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114208.329073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114208.329073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124682.194617 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118712.992236 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118934.033892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124682.194617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118712.992236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118934.033892 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208125.036075 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208125.036075 # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802 # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210975.042352 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210975.042352 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210920.589303 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210920.589303 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4877464 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2438379 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4877468 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2438381 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2144933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2144935 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 958726 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1035547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1035549 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 821965 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 301462 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 301462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1036979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1036981 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101122 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3109189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3109195 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4238791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7347980 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132621440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7347986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132621696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143635700 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 276257140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 276257396 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 422449 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2878054 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2878056 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.001305 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.036107 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2874297 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2874299 99.87% 99.87% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3757 0.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2878054 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4329025000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2878056 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4329029000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1556715501 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1556718501 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2115441305 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2115441804 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1208,40 +1208,34 @@ system.iobus.trans_dist::ReadResp 7103 # Tr system.iobus.trans_dist::WriteReq 51150 # Transaction distribution system.iobus.trans_dist::WriteResp 51150 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 444000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 826000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1255,16 +1249,10 @@ system.iobus.reqLayer24.occupancy 2178000 # La system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 5944500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 219000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 88000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215036503 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 132500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215036503 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) @@ -1408,11 +1396,11 @@ system.membus.snoop_fanout::max_value 1 # Re system.membus.snoop_fanout::total 842165 # Request fanout histogram system.membus.reqLayer0.occupancy 28939500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314315898 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314314398 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139099889 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139101639 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 69817453 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1460,10 +1448,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818035067000 96.92% 96.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1818035845500 96.92% 96.92% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 64907500 0.00% 96.93% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 561478000 0.03% 96.96% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57098083500 3.04% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57097305000 3.04% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1875759536000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal index 455709c02..2c979b67f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index df18f1206..a2fe4ebe1 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/work/gem5/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/work/gem5/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,9 +26,10 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/work/gem5/dist/binaries/ts_osfpal +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -103,6 +104,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -119,6 +121,7 @@ system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -143,6 +146,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -159,6 +163,7 @@ system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -204,7 +209,7 @@ dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 -interrupts=Null +interrupts= isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 @@ -283,7 +288,7 @@ iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -interrupts=Null +interrupts= isa=system.cpu2.isa issueToExecuteDelay=1 issueWidth=8 @@ -697,7 +702,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -720,7 +725,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -743,10 +748,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.tsunami.pciconfig.pio -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] @@ -755,6 +759,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=false @@ -771,7 +776,8 @@ system=system tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 -cpu_side=system.iobus.master[29] +writeback_clean=false +cpu_side=system.iobus.master[27] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -790,6 +796,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -806,6 +813,7 @@ system=system tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -941,7 +949,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -954,12 +962,13 @@ port=3456 [system.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -967,9 +976,16 @@ width=32 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side +[system.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.tsunami] type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart eventq_index=0 intrctrl=system.intrctrl system=system @@ -1082,12 +1098,12 @@ dma_write_delay=0 dma_write_factor=0 eventq_index=0 hardware_address=00:90:00:00:00:01 +host=system.tsunami.pchip intr_delay=10000000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.tsunami rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -1097,9 +1113,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.master[28] dma=system.iobus.slave[2] -pio=system.iobus.master[27] +pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake @@ -1532,14 +1547,13 @@ config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 eventq_index=0 +host=system.tsunami.pchip io_shift=0 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.tsunami system=system -config=system.iobus.master[26] dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1559,25 +1573,20 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +conf_base=8804649402368 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 +pci_dma_base=0 +pci_mem_base=8796093022208 +pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 +platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.master[1] -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr index 1b889d7a1..52d4acaec 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr @@ -43,11 +43,3 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11394, Bank: 3 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index 930df34c1..001ba9e0a 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 20:54:01 -gem5 started Sep 14 2015 20:54:31 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full +gem5 compiled Dec 4 2015 10:28:58 +gem5 started Dec 4 2015 10:29:24 +gem5 executing on e104799-lin, pid 21387 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 771db86aa..190a0b7d0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.843590 # Nu sim_ticks 1843589966000 # Number of ticks simulated final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220463 # Simulator instruction rate (inst/s) -host_op_rate 220463 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5656183181 # Simulator tick rate (ticks/s) -host_mem_usage 378132 # Number of bytes of host memory used -host_seconds 325.94 # Real time elapsed on the host +host_inst_rate 221527 # Simulator instruction rate (inst/s) +host_op_rate 221527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5683484333 # Simulator tick rate (ticks/s) +host_mem_usage 334252 # Number of bytes of host memory used +host_seconds 324.38 # Real time elapsed on the host sim_insts 71858146 # Number of instructions simulated sim_ops 71858146 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1366,40 +1366,34 @@ system.iobus.trans_dist::ReadResp 7317 # Tr system.iobus.trans_dist::WriteReq 51364 # Transaction distribution system.iobus.trans_dist::WriteResp 51364 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5196 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 33912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 117362 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 45584 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 2564500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 116500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 118500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 55500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) @@ -1407,10 +1401,8 @@ system.iobus.reqLayer23.occupancy 6287500 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 2121000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 84230549 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 84230549 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 16458000 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal index 8a879f578..cbce606f3 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 6 cycles, load miss latency 32 cycles +
4096K Bcache detected; load hit latency 6 cycles, load miss latency 30 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 |