diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3002 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 232 |
2 files changed, 1621 insertions, 1613 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 0876dc614..a9e8e7d4a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903548 # Number of seconds simulated -sim_ticks 1903548166500 # Number of ticks simulated -final_tick 1903548166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.902683 # Number of seconds simulated +sim_ticks 1902682770000 # Number of ticks simulated +final_tick 1902682770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123505 # Simulator instruction rate (inst/s) -host_op_rate 123505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4187441182 # Simulator tick rate (ticks/s) -host_mem_usage 303204 # Number of bytes of host memory used -host_seconds 454.59 # Real time elapsed on the host -sim_insts 56143492 # Number of instructions simulated -sim_ops 56143492 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 879488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24796480 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 101696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 559552 # Number of bytes read from this memory -system.physmem.bytes_read::total 28986880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 879488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 101696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7925376 # Number of bytes written to this memory -system.physmem.bytes_written::total 7925376 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387445 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1589 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8743 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123834 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 462026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13026453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 293952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15227815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 462026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4163475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4163475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4163475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 462026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13026453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 293952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19391291 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 346033 # number of replacements -system.l2c.tagsinuse 65330.743124 # Cycle average of tags in use -system.l2c.total_refs 2608063 # Total number of references to valid blocks. -system.l2c.sampled_refs 411178 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.342905 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6380526000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53708.225390 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5276.213951 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6113.589929 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 198.792297 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 33.921558 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.819522 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080509 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093286 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003033 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000518 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996868 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 970913 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 780748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 107670 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 39067 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1898398 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 832636 # number of Writeback hits -system.l2c.Writeback_hits::total 832636 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 238 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits +host_inst_rate 192931 # Simulator instruction rate (inst/s) +host_op_rate 192931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6436506827 # Simulator tick rate (ticks/s) +host_mem_usage 296908 # Number of bytes of host memory used +host_seconds 295.61 # Real time elapsed on the host +sim_insts 57032045 # Number of instructions simulated +sim_ops 57032045 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 906816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24518592 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 73984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 789824 # Number of bytes read from this memory +system.physmem.bytes_read::total 28940032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 906816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 73984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7895360 # Number of bytes written to this memory +system.physmem.bytes_written::total 7895360 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 383103 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1156 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12341 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452188 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123365 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 476599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12886327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1393199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 38884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 415111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15210119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 476599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 38884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4149593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4149593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4149593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 476599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12886327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1393199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 38884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 415111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359713 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 345291 # number of replacements +system.l2c.tagsinuse 65280.360301 # Cycle average of tags in use +system.l2c.total_refs 2575351 # Total number of references to valid blocks. +system.l2c.sampled_refs 410382 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.275497 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6143524000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53635.672684 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5378.326569 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6042.958234 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 144.667579 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 78.735234 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.818415 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.082067 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.092208 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002207 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001201 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996099 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 798441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 696934 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 292090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 99595 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1887060 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 812223 # number of Writeback hits +system.l2c.Writeback_hits::total 812223 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 566 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 168538 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 13567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 182105 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 970913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 949286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 107670 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 52634 # number of demand (read+write) hits -system.l2c.demand_hits::total 2080503 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 970913 # number of overall hits -system.l2c.overall_hits::cpu0.data 949286 # number of overall hits -system.l2c.overall_hits::cpu1.inst 107670 # number of overall hits -system.l2c.overall_hits::cpu1.data 52634 # number of overall hits -system.l2c.overall_hits::total 2080503 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13744 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272909 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1606 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 887 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289146 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2478 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 531 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 43 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 77 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 120 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114968 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7955 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122923 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13744 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387877 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1606 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8842 # number of demand (read+write) misses -system.l2c.demand_misses::total 412069 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13744 # number of overall misses -system.l2c.overall_misses::cpu0.data 387877 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1606 # number of overall misses -system.l2c.overall_misses::cpu1.data 8842 # number of overall misses -system.l2c.overall_misses::total 412069 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 731783998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14210594000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 85626000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 48439997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15076443995 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2486000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1250500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 3736500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 522000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 678500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6190320497 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 441967499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6632287996 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 731783998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20400914497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 85626000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 490407496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21708731991 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 731783998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20400914497 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 85626000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 490407496 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21708731991 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 984657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1053657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 109276 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 39954 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2187544 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 832636 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832636 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2662 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 585 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3247 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 70 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 106 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 176 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 283506 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 21522 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305028 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 984657 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1337163 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 109276 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61476 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2492572 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 984657 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1337163 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 109276 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61476 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2492572 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013958 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259011 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022201 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.132178 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.930879 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.907692 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.926702 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.614286 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726415 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.681818 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.405522 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.369622 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.402989 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013958 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290075 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014697 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.143828 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165319 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013958 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290075 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014697 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.143828 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165319 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53243.888097 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52070.814814 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53316.313823 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 54611.045096 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52141.285008 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.228410 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2354.990584 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1241.774676 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12139.534884 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2032.467532 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5654.166667 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53843.856525 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55558.453677 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53954.817211 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52596.350124 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 53316.313823 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 55463.412803 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52682.274063 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52596.350124 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 53316.313823 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 55463.412803 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52682.274063 # average overall miss latency +system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 135544 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 39704 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 175248 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 798441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 832478 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 292090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 139299 # number of demand (read+write) hits +system.l2c.demand_hits::total 2062308 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 798441 # number of overall hits +system.l2c.overall_hits::cpu0.data 832478 # number of overall hits +system.l2c.overall_hits::cpu1.inst 292090 # number of overall hits +system.l2c.overall_hits::cpu1.data 139299 # number of overall hits +system.l2c.overall_hits::total 2062308 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 14171 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272326 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1173 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1502 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289172 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2767 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1411 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4178 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 606 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 630 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1236 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 111402 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 10975 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122377 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 14171 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 383728 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1173 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12477 # number of demand (read+write) misses +system.l2c.demand_misses::total 411549 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 14171 # number of overall misses +system.l2c.overall_misses::cpu0.data 383728 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1173 # number of overall misses +system.l2c.overall_misses::cpu1.data 12477 # number of overall misses +system.l2c.overall_misses::total 411549 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 755985500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14184372500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 62331000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 81509998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15084198998 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1749500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 16214497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 17963997 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2002500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 367000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2369500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6034072500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 609639000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6643711500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 755985500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20218445000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 62331000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 691148998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21727910498 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 755985500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20218445000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 62331000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 691148998 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21727910498 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 812612 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 969260 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 293263 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 101097 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2176232 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 812223 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 812223 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2936 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1808 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4744 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 652 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 659 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1311 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 246946 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 50679 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 297625 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 812612 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1216206 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 293263 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 151776 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2473857 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 812612 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1216206 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 293263 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 151776 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2473857 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.017439 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.280963 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.014857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132877 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942439 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780420 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880691 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.929448 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.955994 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.942792 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.451119 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.216559 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.411178 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.017439 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.315512 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.082207 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166359 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.017439 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.315512 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.082207 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166359 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53347.364336 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52086.001704 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53138.107417 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 54267.641811 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52163.414847 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 632.273220 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11491.493267 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4299.664193 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3304.455446 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.539683 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1917.071197 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54164.848926 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55547.972665 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54288.890069 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53347.364336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52689.522266 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53138.107417 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 55393.844514 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52795.439906 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53347.364336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52689.522266 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53138.107417 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 55393.844514 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52795.439906 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,8 +221,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 82314 # number of writebacks -system.l2c.writebacks::total 82314 # number of writebacks +system.l2c.writebacks::writebacks 81845 # number of writebacks +system.l2c.writebacks::total 81845 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits @@ -232,111 +232,111 @@ system.l2c.demand_mshr_hits::total 18 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13743 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 272909 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1589 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 887 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289128 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2478 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 531 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3009 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 43 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 77 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 120 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114968 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7955 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122923 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13743 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387877 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1589 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8842 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 412051 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13743 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387877 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1589 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8842 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 412051 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 563800998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10943970500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 65437000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 37722500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11610930998 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 99235500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 21259000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 120494500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1720000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3080000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 4800000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4801585997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 345787499 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5147373496 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 563800998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15745556497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 65437000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 383509999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16758304494 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 563800998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15745556497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 65437000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 383509999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16758304494 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363601000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23660000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1387261000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1941911500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 514448500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2456360000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3305512500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538108500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3843621000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259011 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022201 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.132170 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.930879 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.907692 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.926702 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.614286 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.726415 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.681818 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.405522 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.369622 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.402989 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165312 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165312 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40101.171086 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42528.184893 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40158.445388 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40046.610169 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40035.781544 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40044.699236 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41764.543151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43467.944563 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41874.779301 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 14170 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272326 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1156 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1502 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289154 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2767 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1411 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4178 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 606 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 630 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1236 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 111402 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 10975 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122377 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 14170 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 383728 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1156 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 12477 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411531 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 14170 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 383728 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1156 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 12477 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411531 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 582633500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10923275000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 47336500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 63194498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11616439498 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 110819971 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56511497 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 167331468 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 24296484 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25202500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 49498984 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4677812000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 476518500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5154330500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 582633500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15601087000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 47336500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 539712998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16770769998 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 582633500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15601087000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 47336500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 539712998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16770769998 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1358127000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28700000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1386827000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2042144000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647379000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2689523000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3400271000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 676079000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4076350000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.280963 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.014857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132869 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942439 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780420 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.880691 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.929448 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955994 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.942792 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.451119 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.216559 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.411178 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.315512 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.082207 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166352 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.315512 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.082207 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166352 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40111.025021 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42073.567244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40173.884843 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40050.585833 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.671155 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40050.614648 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40093.207921 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40003.968254 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.721683 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41990.377193 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43418.542141 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42118.457717 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40656.629175 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43256.632043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40752.142604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40656.629175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43256.632043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40752.142604 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -347,39 +347,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.468369 # Cycle average of tags in use +system.iocache.replacements 41697 # number of replacements +system.iocache.tagsinuse 0.492574 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1712293009000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.468369 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029273 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029273 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.warmup_cycle 1709348959000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.492574 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030786 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030786 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21012998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21012998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11487114806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11487114806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11508127804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11508127804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11508127804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11508127804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21127998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21127998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11486516806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11486516806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11507644804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11507644804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11507644804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11507644804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119392.034091 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276451.550010 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 276451.550010 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 275789.105732 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 275789.105732 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 201643000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119367.220339 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119367.220339 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276437.158404 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 276437.158404 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275770.921997 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275770.921997 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 200533 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24752 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24673 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8146.533613 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.127629 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11860000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11860000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9326257976 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9326257976 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9338117976 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9338117976 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9338117976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9338117976 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11923998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11923998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9325812806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9325812806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9337736804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9337736804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9337736804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9337736804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67367.220339 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67367.220339 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224437.158404 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224437.158404 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9377828 # DTB read hits -system.cpu0.dtb.read_misses 33360 # DTB read misses -system.cpu0.dtb.read_acv 521 # DTB read access violations -system.cpu0.dtb.read_accesses 633373 # DTB read accesses -system.cpu0.dtb.write_hits 6221809 # DTB write hits -system.cpu0.dtb.write_misses 7167 # DTB write misses -system.cpu0.dtb.write_acv 341 # DTB write access violations -system.cpu0.dtb.write_accesses 216042 # DTB write accesses -system.cpu0.dtb.data_hits 15599637 # DTB hits -system.cpu0.dtb.data_misses 40527 # DTB misses -system.cpu0.dtb.data_acv 862 # DTB access violations -system.cpu0.dtb.data_accesses 849415 # DTB accesses -system.cpu0.itb.fetch_hits 1073423 # ITB hits -system.cpu0.itb.fetch_misses 26403 # ITB misses -system.cpu0.itb.fetch_acv 1051 # ITB acv -system.cpu0.itb.fetch_accesses 1099826 # ITB accesses +system.cpu0.dtb.read_hits 8304100 # DTB read hits +system.cpu0.dtb.read_misses 28307 # DTB read misses +system.cpu0.dtb.read_acv 549 # DTB read access violations +system.cpu0.dtb.read_accesses 542239 # DTB read accesses +system.cpu0.dtb.write_hits 5411904 # DTB write hits +system.cpu0.dtb.write_misses 5987 # DTB write misses +system.cpu0.dtb.write_acv 347 # DTB write access violations +system.cpu0.dtb.write_accesses 182798 # DTB write accesses +system.cpu0.dtb.data_hits 13716004 # DTB hits +system.cpu0.dtb.data_misses 34294 # DTB misses +system.cpu0.dtb.data_acv 896 # DTB access violations +system.cpu0.dtb.data_accesses 725037 # DTB accesses +system.cpu0.itb.fetch_hits 908718 # ITB hits +system.cpu0.itb.fetch_misses 19910 # ITB misses +system.cpu0.itb.fetch_acv 927 # ITB acv +system.cpu0.itb.fetch_accesses 928628 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,277 +483,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 120667689 # number of cpu cycles simulated +system.cpu0.numCycles 102599658 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13362893 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11185412 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 402804 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9622475 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5627170 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11825647 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9917652 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 342692 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8240217 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5044056 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 884758 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37477 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 30221705 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 67571030 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13362893 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6511928 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12734942 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1928304 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 41309111 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 28714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 205220 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 305503 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8304621 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 277902 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 86063714 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.785128 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.113854 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 768623 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31919 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 23566044 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60418395 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11825647 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5812679 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11434253 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1624928 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 35275815 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31363 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 170412 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 309547 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7444211 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 224420 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 71849758 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.840899 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.174060 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 73328772 85.20% 85.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 837915 0.97% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1666262 1.94% 88.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 768356 0.89% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2658731 3.09% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 585060 0.68% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 622966 0.72% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 967713 1.12% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4627939 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 60415505 84.09% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 744936 1.04% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1526054 2.12% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 669496 0.93% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2482176 3.45% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 513952 0.72% 92.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 559997 0.78% 93.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 746719 1.04% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4190923 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 86063714 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.110741 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559976 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 31149327 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 41124977 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11584676 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 985581 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1219152 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 571369 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 39493 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 66407813 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 120728 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1219152 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 32233219 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 16872016 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 20344281 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10880828 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4514216 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62880643 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6942 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 700700 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1661735 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 42005938 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 76144064 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 75702119 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 441945 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36517182 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5488748 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1574453 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 239002 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12018911 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9888186 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6523659 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1201517 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 824194 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55665948 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1995313 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54317533 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 112244 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6696159 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3338542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1358752 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 86063714 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.631132 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.280124 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 71849758 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.115260 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.588875 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24832568 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34702410 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10423010 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 862232 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1029537 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 502827 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32976 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 59359454 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 95150 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1029537 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25748676 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14416729 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17004300 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9792924 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3857590 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56337606 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6610 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 598180 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1362975 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 37819724 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 68629747 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 68286150 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 343597 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33121112 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4698612 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1343902 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201432 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10333121 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8734327 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5677673 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1105299 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 704273 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50005822 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1695696 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 48865145 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 103608 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5731519 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2860845 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1151664 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 71849758 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680102 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.326568 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 61486843 71.44% 71.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 11432526 13.28% 84.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5063556 5.88% 90.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3287093 3.82% 94.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2517985 2.93% 97.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1255115 1.46% 98.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 648079 0.75% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 319509 0.37% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53008 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50068220 69.68% 69.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9955153 13.86% 83.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4454682 6.20% 89.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2911875 4.05% 93.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2358569 3.28% 97.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1157257 1.61% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 610758 0.85% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 286058 0.40% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 47186 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 86063714 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 71849758 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 73354 10.53% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 330176 47.38% 57.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 293358 42.10% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 80509 12.84% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 294043 46.91% 59.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 252280 40.25% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3296 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37287239 68.65% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60152 0.11% 68.76% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.76% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15662 0.03% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1646 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9781142 18.01% 86.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6293081 11.59% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 875315 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2557 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33918404 69.41% 69.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54116 0.11% 69.53% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 12070 0.02% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8648673 17.70% 87.25% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5478002 11.21% 98.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 750056 1.53% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54317533 # Type of FU issued -system.cpu0.iq.rate 0.450141 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 696889 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012830 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 194880881 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 64065914 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53156794 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 627031 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 303977 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294706 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 54682626 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 328500 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 571695 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 48865145 # Type of FU issued +system.cpu0.iq.rate 0.476270 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 626833 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012828 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 169818867 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57206555 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 47890608 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 491622 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 238128 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232129 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 49232078 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 257343 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 523556 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1271953 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2828 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12731 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 517788 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1075506 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2442 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11895 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 454594 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18545 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 107284 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 86028 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1219152 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 12163042 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 861940 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61112544 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 659342 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9888186 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6523659 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1757966 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 617572 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 9941 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12731 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 210191 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 389993 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 600184 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 53834482 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9436308 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 483050 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1029537 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10326104 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 769928 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54791843 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 549393 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8734327 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5677673 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1493453 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 559696 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5669 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11895 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 183351 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 329192 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 512543 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 48451300 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8354077 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 413845 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3451283 # number of nop insts executed -system.cpu0.iew.exec_refs 15679571 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8587439 # Number of branches executed -system.cpu0.iew.exec_stores 6243263 # Number of stores executed -system.cpu0.iew.exec_rate 0.446138 # Inst execution rate -system.cpu0.iew.wb_sent 53546468 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53451500 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26356174 # num instructions producing a value -system.cpu0.iew.wb_consumers 35593959 # num instructions consuming a value +system.cpu0.iew.exec_nop 3090325 # number of nop insts executed +system.cpu0.iew.exec_refs 13784796 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7754310 # Number of branches executed +system.cpu0.iew.exec_stores 5430719 # Number of stores executed +system.cpu0.iew.exec_rate 0.472236 # Inst execution rate +system.cpu0.iew.wb_sent 48208648 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48122737 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24107105 # num instructions producing a value +system.cpu0.iew.wb_consumers 32426814 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.442964 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.740468 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.469034 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743431 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7303960 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 636561 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 562819 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 84844562 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.633202 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.547709 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6216029 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 544032 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 479899 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 70820221 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.684637 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.594318 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 64556270 76.09% 76.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8510919 10.03% 86.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4635841 5.46% 91.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2494817 2.94% 94.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1390539 1.64% 96.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 576056 0.68% 96.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 484846 0.57% 97.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 456978 0.54% 97.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1738296 2.05% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 52470926 74.09% 74.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7676401 10.84% 84.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4235846 5.98% 90.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2227139 3.14% 94.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1283042 1.81% 95.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 528527 0.75% 96.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 441494 0.62% 97.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 421867 0.60% 97.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1534979 2.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 84844562 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53723778 # Number of instructions committed -system.cpu0.commit.committedOps 53723778 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 70820221 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48486178 # Number of instructions committed +system.cpu0.commit.committedOps 48486178 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14622104 # Number of memory references committed -system.cpu0.commit.loads 8616233 # Number of loads committed -system.cpu0.commit.membars 216543 # Number of memory barriers committed -system.cpu0.commit.branches 8113778 # Number of branches committed -system.cpu0.commit.fp_insts 292474 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49705714 # Number of committed integer instructions. -system.cpu0.commit.function_calls 703203 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1738296 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12881900 # Number of memory references committed +system.cpu0.commit.loads 7658821 # Number of loads committed +system.cpu0.commit.membars 183715 # Number of memory barriers committed +system.cpu0.commit.branches 7346956 # Number of branches committed +system.cpu0.commit.fp_insts 229898 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 44900899 # Number of committed integer instructions. +system.cpu0.commit.function_calls 613493 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1534979 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 143945633 # The number of ROB reads -system.cpu0.rob.rob_writes 123274808 # The number of ROB writes -system.cpu0.timesIdled 1363780 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 34603975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3686422279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50608732 # Number of Instructions Simulated -system.cpu0.committedOps 50608732 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 50608732 # Number of Instructions Simulated -system.cpu0.cpi 2.384325 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.384325 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.419406 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.419406 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 70600527 # number of integer regfile reads -system.cpu0.int_regfile_writes 38607300 # number of integer regfile writes -system.cpu0.fp_regfile_reads 144193 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146198 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1863622 # number of misc regfile reads -system.cpu0.misc_regfile_writes 886886 # number of misc regfile writes +system.cpu0.rob.rob_reads 123809295 # The number of ROB reads +system.cpu0.rob.rob_writes 110434143 # The number of ROB writes +system.cpu0.timesIdled 1033297 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 30749900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702120338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 45684021 # Number of Instructions Simulated +system.cpu0.committedOps 45684021 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 45684021 # Number of Instructions Simulated +system.cpu0.cpi 2.245854 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.245854 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.445265 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.445265 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 63838240 # number of integer regfile reads +system.cpu0.int_regfile_writes 34928793 # number of integer regfile writes +system.cpu0.fp_regfile_reads 112215 # number of floating regfile reads +system.cpu0.fp_regfile_writes 113746 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1561574 # number of misc regfile reads +system.cpu0.misc_regfile_writes 757779 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -785,245 +785,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 984085 # number of replacements -system.cpu0.icache.tagsinuse 509.993322 # Cycle average of tags in use -system.cpu0.icache.total_refs 7264923 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984594 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.378598 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23948219000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.993322 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996081 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996081 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7264923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7264923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7264923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7264923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7264923 # number of overall hits -system.cpu0.icache.overall_hits::total 7264923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1039697 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1039697 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1039697 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1039697 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1039697 # number of overall misses -system.cpu0.icache.overall_misses::total 1039697 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16868456488 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16868456488 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16868456488 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16868456488 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16868456488 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16868456488 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8304620 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8304620 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8304620 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8304620 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8304620 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8304620 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125195 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125195 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125195 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125195 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125195 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125195 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16224.396616 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16224.396616 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16224.396616 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1612994 # number of cycles access was blocked +system.cpu0.icache.replacements 812060 # number of replacements +system.cpu0.icache.tagsinuse 510.054551 # Cycle average of tags in use +system.cpu0.icache.total_refs 6590229 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 812572 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.110332 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23200943000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.054551 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996200 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996200 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6590229 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6590229 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6590229 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6590229 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6590229 # number of overall hits +system.cpu0.icache.overall_hits::total 6590229 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 853981 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 853981 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 853981 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 853981 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 853981 # number of overall misses +system.cpu0.icache.overall_misses::total 853981 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11857055495 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11857055495 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11857055495 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11857055495 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11857055495 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11857055495 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7444210 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7444210 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7444210 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7444210 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7444210 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7444210 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114717 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.114717 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114717 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.114717 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114717 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.114717 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13884.448828 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13884.448828 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13884.448828 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13884.448828 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2511 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 9432.713450 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.771654 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54925 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54925 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54925 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54925 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54925 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54925 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 984772 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 984772 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 984772 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13041683494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13041683494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13041683494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13041683494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13041683494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13041683494 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.118581 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.118581 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13243.353278 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41272 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 41272 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41272 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 41272 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41272 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 41272 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 812709 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 812709 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 812709 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 812709 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 812709 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 812709 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9799988995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9799988995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9799988995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9799988995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9799988995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9799988995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109173 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.109173 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.109173 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12058.423119 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1341345 # number of replacements -system.cpu0.dcache.tagsinuse 506.494858 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11161433 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341857 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.317900 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 23750000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.494858 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989248 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989248 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6822568 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6822568 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3942957 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3942957 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181355 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 181355 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208341 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208341 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10765525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10765525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10765525 # number of overall hits -system.cpu0.dcache.overall_hits::total 10765525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1719034 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1719034 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1839372 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1839372 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22429 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22429 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 711 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 711 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3558406 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3558406 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3558406 # number of overall misses -system.cpu0.dcache.overall_misses::total 3558406 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46470872000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 46470872000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71479264510 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71479264510 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 406558000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 406558000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6746500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 6746500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117950136510 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117950136510 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117950136510 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117950136510 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8541602 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8541602 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5782329 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5782329 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203784 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203784 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209052 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209052 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14323931 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14323931 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14323931 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14323931 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.201254 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.201254 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318102 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.318102 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003401 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003401 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248424 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248424 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248424 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248424 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27033.131398 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27033.131398 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38860.689686 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38860.689686 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18126.443444 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18126.443444 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9488.748242 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9488.748242 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33146.902436 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33146.902436 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 754476476 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 245500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 70452 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10709.085278 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27277.777778 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 1218511 # number of replacements +system.cpu0.dcache.tagsinuse 505.616339 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9815926 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1218945 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.052805 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 23286000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.616339 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987532 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987532 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6063177 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6063177 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3417347 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3417347 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151987 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 151987 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174443 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 174443 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9480524 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9480524 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9480524 # number of overall hits +system.cpu0.dcache.overall_hits::total 9480524 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1492446 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1492446 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1612731 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1612731 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19429 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19429 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4062 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4062 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3105177 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3105177 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3105177 # number of overall misses +system.cpu0.dcache.overall_misses::total 3105177 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34499425000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34499425000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55944257946 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 55944257946 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 264930500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 264930500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47614500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 47614500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 90443682946 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 90443682946 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 90443682946 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 90443682946 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7555623 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7555623 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5030078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5030078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 171416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 171416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178505 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 178505 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12585701 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12585701 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12585701 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12585701 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197528 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197528 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113344 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113344 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.022756 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.022756 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246723 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.246723 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.246723 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.246723 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23116.028989 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23116.028989 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34689.144033 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34689.144033 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13635.827886 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13635.827886 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11721.935007 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11721.935007 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 29126.739940 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 29126.739940 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1403245 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 435 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 52795 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.579127 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 62.142857 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 796119 # number of writebacks -system.cpu0.dcache.writebacks::total 796119 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 675047 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 675047 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1552745 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1552745 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5057 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5057 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2227792 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2227792 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2227792 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2227792 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043987 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1043987 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 286627 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 286627 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17372 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17372 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 711 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 711 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330614 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1330614 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330614 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1330614 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27461612037 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27461612037 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9493856805 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9493856805 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 250184001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 250184001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4525001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4525001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36955468842 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36955468842 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36955468842 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36955468842 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1456541500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1456541500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2062903998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2062903998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3519445498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3519445498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049569 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049569 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085247 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085247 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003401 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003401 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092894 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092894 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26304.553636 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26304.553636 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33122.688389 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33122.688389 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14401.565796 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14401.565796 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6364.277075 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6364.277075 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 710192 # number of writebacks +system.cpu0.dcache.writebacks::total 710192 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 524907 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 524907 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1358576 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1358576 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4179 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4179 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1883483 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1883483 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1883483 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1883483 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 967539 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 967539 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254155 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 254155 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15250 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15250 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4062 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4062 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1221694 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1221694 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1221694 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1221694 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23357450000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23357450000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8081474275 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8081474275 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 163906000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 163906000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 39490500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 39490500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31438924275 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31438924275 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31438924275 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31438924275 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451861000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451861000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167064498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167064498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3618925498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3618925498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128055 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128055 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050527 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050527 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.022756 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.022756 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097070 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097070 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24141.094054 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24141.094054 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31797.423915 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31797.423915 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10747.934426 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10747.934426 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9721.935007 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9721.935007 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1035,22 +1035,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1298594 # DTB read hits -system.cpu1.dtb.read_misses 11503 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 332098 # DTB read accesses -system.cpu1.dtb.write_hits 765153 # DTB write hits -system.cpu1.dtb.write_misses 2957 # DTB write misses -system.cpu1.dtb.write_acv 47 # DTB write access violations -system.cpu1.dtb.write_accesses 125840 # DTB write accesses -system.cpu1.dtb.data_hits 2063747 # DTB hits -system.cpu1.dtb.data_misses 14460 # DTB misses -system.cpu1.dtb.data_acv 53 # DTB access violations -system.cpu1.dtb.data_accesses 457938 # DTB accesses -system.cpu1.itb.fetch_hits 372513 # ITB hits -system.cpu1.itb.fetch_misses 8563 # ITB misses -system.cpu1.itb.fetch_acv 155 # ITB acv -system.cpu1.itb.fetch_accesses 381076 # ITB accesses +system.cpu1.dtb.read_hits 2472786 # DTB read hits +system.cpu1.dtb.read_misses 14686 # DTB read misses +system.cpu1.dtb.read_acv 33 # DTB read access violations +system.cpu1.dtb.read_accesses 413814 # DTB read accesses +system.cpu1.dtb.write_hits 1645990 # DTB write hits +system.cpu1.dtb.write_misses 3399 # DTB write misses +system.cpu1.dtb.write_acv 61 # DTB write access violations +system.cpu1.dtb.write_accesses 158815 # DTB write accesses +system.cpu1.dtb.data_hits 4118776 # DTB hits +system.cpu1.dtb.data_misses 18085 # DTB misses +system.cpu1.dtb.data_acv 94 # DTB access violations +system.cpu1.dtb.data_accesses 572629 # DTB accesses +system.cpu1.itb.fetch_hits 546471 # ITB hits +system.cpu1.itb.fetch_misses 10636 # ITB misses +system.cpu1.itb.fetch_acv 251 # ITB acv +system.cpu1.itb.fetch_accesses 557107 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1063,516 +1063,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 10640951 # number of cpu cycles simulated +system.cpu1.numCycles 20144234 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1701905 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1402674 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 62577 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 862370 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 552113 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3332472 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2756183 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 108633 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2168857 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1160511 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 115027 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5500 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3435420 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8139615 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1701905 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 667140 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1472350 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 326710 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 4537469 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24627 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 73138 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47601 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1039363 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 39149 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9806707 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.830005 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.196976 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 228547 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 10150 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 7838813 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 15883595 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3332472 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1389058 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2861385 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 534677 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 7961253 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 27792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 84864 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 61219 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1925840 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 71197 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 19177134 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.828257 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199800 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 8334357 84.99% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 78230 0.80% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 173812 1.77% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 130927 1.34% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 215769 2.20% 91.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 90418 0.92% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 98526 1.00% 93.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 62686 0.64% 93.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 621982 6.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 16315749 85.08% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 188313 0.98% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 313367 1.63% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 233008 1.22% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 393584 2.05% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151826 0.79% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 167771 0.87% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 278696 1.45% 94.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1134820 5.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9806707 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.159939 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.764933 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3510066 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4639401 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1367694 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 78184 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 211361 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 75357 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4832 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 7943726 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 14591 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 211361 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3646380 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 524692 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3638231 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1300485 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 485556 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7343826 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 139 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 57550 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 136110 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 4921664 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 8958013 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 8905584 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52429 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3978815 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 942849 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 306458 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22346 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1365387 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1395502 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 827989 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 138090 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 96967 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6484639 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 311488 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6173957 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 24546 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1207593 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 679802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236614 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9806707 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.629565 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.304884 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 19177134 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.165431 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.788493 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7716271 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8310209 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2661595 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 156637 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 332421 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 147192 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 9531 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 15577857 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 28018 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 332421 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7986115 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 672083 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6791538 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2542197 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 852778 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14454091 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 131 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 86206 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 218054 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9478411 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 17286766 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17086477 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 200289 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 8045295 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1433108 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 570111 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 60569 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2590157 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2624799 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1738404 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 257229 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 149585 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12667252 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 630653 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12308685 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 34992 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1859186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 963032 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 447479 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 19177134 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.641842 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.313805 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 7075152 72.15% 72.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1257607 12.82% 84.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 548751 5.60% 90.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 366543 3.74% 94.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 274418 2.80% 97.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 146525 1.49% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 78833 0.80% 99.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 55100 0.56% 99.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 3778 0.04% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 13743416 71.67% 71.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2506419 13.07% 84.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1066336 5.56% 90.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 706714 3.69% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 606260 3.16% 97.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 273557 1.43% 98.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 174545 0.91% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 89739 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10148 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9806707 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 19177134 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2937 2.09% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 77829 55.26% 57.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60078 42.66% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4629 1.86% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 131937 52.95% 54.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 112626 45.20% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3992 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3816770 61.82% 61.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10118 0.16% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10095 0.16% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1996 0.03% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1354962 21.95% 84.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 784960 12.71% 96.91% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 191064 3.09% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7659302 62.23% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 19564 0.16% 62.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14781 0.12% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2596890 21.10% 83.66% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1675725 13.61% 97.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 335297 2.72% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6173957 # Type of FU issued -system.cpu1.iq.rate 0.580207 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 140844 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.022813 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 22242262 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 7966601 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 5994284 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 77749 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 38725 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37333 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6270612 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40197 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 68178 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12308685 # Type of FU issued +system.cpu1.iq.rate 0.611028 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 249192 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020245 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 43789272 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15018387 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11932725 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 289415 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 141077 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 136872 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12402102 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 151024 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 115183 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 253497 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 450 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1694 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 109535 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 382493 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2469 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 155910 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 346 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8387 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 398 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 20099 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 211361 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 294243 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 17071 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7057887 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 102198 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1395502 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 827989 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 289869 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6102 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1694 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 30581 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 71547 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 102128 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6103512 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1313696 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 70445 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 332421 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 409059 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 59053 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13963733 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 192284 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2624799 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1738404 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 567278 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49311 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2791 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2469 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 54746 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 126604 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 181350 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12183266 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2497630 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 125418 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 261760 # number of nop insts executed -system.cpu1.iew.exec_refs 2085126 # number of memory reference insts executed -system.cpu1.iew.exec_branches 894247 # Number of branches executed -system.cpu1.iew.exec_stores 771430 # Number of stores executed -system.cpu1.iew.exec_rate 0.573587 # Inst execution rate -system.cpu1.iew.wb_sent 6061366 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6031617 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2917806 # num instructions producing a value -system.cpu1.iew.wb_consumers 4086073 # num instructions consuming a value +system.cpu1.iew.exec_nop 665828 # number of nop insts executed +system.cpu1.iew.exec_refs 4154589 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1827055 # Number of branches executed +system.cpu1.iew.exec_stores 1656959 # Number of stores executed +system.cpu1.iew.exec_rate 0.604802 # Inst execution rate +system.cpu1.iew.wb_sent 12107744 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 12069597 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5640555 # num instructions producing a value +system.cpu1.iew.wb_consumers 7931807 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.566831 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.714086 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.599159 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.711131 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1232464 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 74874 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 96289 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9595346 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.599743 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.518608 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1943114 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 183174 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170211 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 18844713 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633421 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.575988 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 7360615 76.71% 76.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1091727 11.38% 88.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 382276 3.98% 92.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 236221 2.46% 94.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 149500 1.56% 96.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 68368 0.71% 96.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 77096 0.80% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 48958 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 180585 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 14387001 76.35% 76.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2066578 10.97% 87.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 777942 4.13% 91.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 478446 2.54% 93.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 347277 1.84% 95.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 135394 0.72% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 132721 0.70% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 138400 0.73% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 380954 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9595346 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5754744 # Number of instructions committed -system.cpu1.commit.committedOps 5754744 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 18844713 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 11936636 # Number of instructions committed +system.cpu1.commit.committedOps 11936636 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1860459 # Number of memory references committed -system.cpu1.commit.loads 1142005 # Number of loads committed -system.cpu1.commit.membars 20259 # Number of memory barriers committed -system.cpu1.commit.branches 814036 # Number of branches committed -system.cpu1.commit.fp_insts 36051 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5384897 # Number of committed integer instructions. -system.cpu1.commit.function_calls 87726 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 180585 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3824800 # Number of memory references committed +system.cpu1.commit.loads 2242306 # Number of loads committed +system.cpu1.commit.membars 59908 # Number of memory barriers committed +system.cpu1.commit.branches 1711003 # Number of branches committed +system.cpu1.commit.fp_insts 135276 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 11053668 # Number of committed integer instructions. +system.cpu1.commit.function_calls 186526 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 380954 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 16310969 # The number of ROB reads -system.cpu1.rob.rob_writes 14184459 # The number of ROB writes -system.cpu1.timesIdled 82580 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 834244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3796004491 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5534760 # Number of Instructions Simulated -system.cpu1.committedOps 5534760 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5534760 # Number of Instructions Simulated -system.cpu1.cpi 1.922568 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.922568 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.520138 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.520138 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 7951221 # number of integer regfile reads -system.cpu1.int_regfile_writes 4345022 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24272 # number of floating regfile reads -system.cpu1.fp_regfile_writes 22982 # number of floating regfile writes -system.cpu1.misc_regfile_reads 283160 # number of misc regfile reads -system.cpu1.misc_regfile_writes 134137 # number of misc regfile writes -system.cpu1.icache.replacements 108736 # number of replacements -system.cpu1.icache.tagsinuse 452.848051 # Cycle average of tags in use -system.cpu1.icache.total_refs 924017 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 109246 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.458131 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1880838222000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 452.848051 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.884469 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.884469 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 924017 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 924017 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 924017 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 924017 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 924017 # number of overall hits -system.cpu1.icache.overall_hits::total 924017 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 115346 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 115346 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 115346 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 115346 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 115346 # number of overall misses -system.cpu1.icache.overall_misses::total 115346 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1915256999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1915256999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1915256999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1915256999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1915256999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1915256999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1039363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1039363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1039363 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1039363 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1039363 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1039363 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.110978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.110978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.110978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16604.450948 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16604.450948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16604.450948 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 222999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 32234171 # The number of ROB reads +system.cpu1.rob.rob_writes 28090700 # The number of ROB writes +system.cpu1.timesIdled 170938 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 967100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3785218747 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11348024 # Number of Instructions Simulated +system.cpu1.committedOps 11348024 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 11348024 # Number of Instructions Simulated +system.cpu1.cpi 1.775131 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.775131 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.563339 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.563339 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 15713233 # number of integer regfile reads +system.cpu1.int_regfile_writes 8535659 # number of integer regfile writes +system.cpu1.fp_regfile_reads 74431 # number of floating regfile reads +system.cpu1.fp_regfile_writes 74222 # number of floating regfile writes +system.cpu1.misc_regfile_reads 667576 # number of misc regfile reads +system.cpu1.misc_regfile_writes 284444 # number of misc regfile writes +system.cpu1.icache.replacements 292722 # number of replacements +system.cpu1.icache.tagsinuse 471.494279 # Cycle average of tags in use +system.cpu1.icache.total_refs 1621349 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 293230 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.529274 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1876700215000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 471.494279 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.920887 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.920887 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1621349 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1621349 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1621349 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1621349 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1621349 # number of overall hits +system.cpu1.icache.overall_hits::total 1621349 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 304491 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 304491 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 304491 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 304491 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 304491 # number of overall misses +system.cpu1.icache.overall_misses::total 304491 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4065162500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4065162500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4065162500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4065162500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4065162500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4065162500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1925840 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1925840 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1925840 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1925840 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1925840 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1925840 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158108 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.158108 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158108 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.158108 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158108 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.158108 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13350.681958 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13350.681958 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13350.681958 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13350.681958 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7433.300000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.826087 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6038 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6038 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6038 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6038 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6038 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6038 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 109308 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 109308 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 109308 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 109308 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 109308 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 109308 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491398999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1491398999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1491398999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1491398999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1491398999 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1491398999 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105168 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.105168 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.105168 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11170 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 11170 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 11170 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 11170 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 11170 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 11170 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 293321 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 293321 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 293321 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 293321 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 293321 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 293321 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3385018500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3385018500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3385018500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3385018500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3385018500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3385018500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.152308 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.152308 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11540.321013 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 61811 # number of replacements -system.cpu1.dcache.tagsinuse 423.387508 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1665798 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62157 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 26.799846 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1880297158000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 423.387508 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.826929 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.826929 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1100458 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1100458 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 541491 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 541491 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16674 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16674 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14757 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14757 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1641949 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1641949 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1641949 # number of overall hits -system.cpu1.dcache.overall_hits::total 1641949 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 110209 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 110209 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 156496 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 156496 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1520 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1520 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 666 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 666 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 266705 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 266705 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 266705 # number of overall misses -system.cpu1.dcache.overall_misses::total 266705 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2207117500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2207117500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6428377585 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6428377585 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 25057000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 25057000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8004500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8004500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8635495085 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8635495085 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8635495085 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8635495085 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1210667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1210667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 697987 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 697987 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18194 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18194 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15423 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15423 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1908654 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1908654 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1908654 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1908654 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.091032 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.091032 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224210 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.224210 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083544 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083544 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.139735 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.139735 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.139735 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.139735 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20026.653903 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20026.653903 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41076.945002 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41076.945002 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16484.868421 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16484.868421 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12018.768769 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12018.768769 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32378.452166 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32378.452166 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 48117991 # number of cycles access was blocked +system.cpu1.dcache.replacements 154238 # number of replacements +system.cpu1.dcache.tagsinuse 492.768701 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3312022 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 154750 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 21.402404 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 38606824000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 492.768701 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.962439 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.962439 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2009764 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2009764 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1195197 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1195197 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47136 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47136 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 45762 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 45762 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3204961 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3204961 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3204961 # number of overall hits +system.cpu1.dcache.overall_hits::total 3204961 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 288765 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 288765 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 330549 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 330549 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7490 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7490 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4284 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 4284 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 619314 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 619314 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 619314 # number of overall misses +system.cpu1.dcache.overall_misses::total 619314 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4275169500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4275169500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8473061608 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8473061608 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77853000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77853000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49370500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49370500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12748231108 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12748231108 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12748231108 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12748231108 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2298529 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2298529 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1525746 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1525746 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54626 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 54626 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 50046 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 50046 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3824275 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3824275 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3824275 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3824275 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125630 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.125630 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.216647 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.216647 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137114 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137114 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085601 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085601 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.161943 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.161943 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.161943 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.161943 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14805.012727 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14805.012727 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25633.299777 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25633.299777 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10394.259012 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10394.259012 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11524.393091 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11524.393091 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20584.438763 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20584.438763 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20584.438763 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20584.438763 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 148655 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 4997 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7912 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9629.375825 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.788549 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 36517 # number of writebacks -system.cpu1.dcache.writebacks::total 36517 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66699 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 66699 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 133155 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 133155 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 347 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 347 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 199854 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 199854 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 199854 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 199854 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43510 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 43510 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23341 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 23341 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1173 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1173 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 665 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 665 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 66851 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 66851 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 66851 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 66851 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 664874003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 664874003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 774412476 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 774412476 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13964500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13964500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5940500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5940500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1439286479 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1439286479 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1439286479 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1439286479 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25429000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25429000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 545455000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 545455000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 570884000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 570884000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035939 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035939 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064472 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064472 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043117 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043117 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.035025 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035025 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15280.946978 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15280.946978 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33178.204704 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33178.204704 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11904.944587 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.944587 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8933.082707 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8933.082707 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 102031 # number of writebacks +system.cpu1.dcache.writebacks::total 102031 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180109 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 180109 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 273076 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 273076 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 765 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 453185 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 453185 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 453185 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 453185 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 108656 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 108656 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57473 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57473 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6725 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6725 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4282 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 4282 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 166129 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 166129 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 166129 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 166129 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1328748500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1328748500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1211037987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1211037987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54734500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54734500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 40806500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 40806500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539786487 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2539786487 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539786487 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2539786487 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 686558000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 686558000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047272 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047272 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123110 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123110 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085561 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085561 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043441 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043441 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12228.947320 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12228.947320 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21071.424617 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21071.424617 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8138.959108 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8138.959108 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9529.775806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9529.775806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1581,162 +1581,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199157 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71465 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.10% 41.78% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 9 0.01% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102444 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175976 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70100 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.35% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 9 0.01% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70091 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142258 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862744375000 97.86% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 69542000 0.00% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 583001500 0.03% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5982500 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40144359500 2.11% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903547260500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980900 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6652 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 169834 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 59752 40.24% 40.24% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.32% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.30% 41.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 283 0.19% 41.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 86412 58.19% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 148505 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 58939 49.14% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.61% 50.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 283 0.24% 51.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 58656 48.91% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 119936 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864736682500 98.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62604500 0.00% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 575436000 0.03% 98.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 137989000 0.01% 98.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36850597000 1.94% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1902363309000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.986394 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684188 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808394 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.65% 3.65% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.68% 12.33% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.37% 13.70% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.61% 28.31% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.46% 28.77% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.65% 32.42% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.57% 36.99% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.74% 39.73% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.46% 40.18% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.37% 41.55% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.74% 44.29% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.91% 45.21% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.44% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.37% 63.01% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.57% 67.58% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.57% 72.15% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.46% 72.60% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.74% 75.34% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.50% 85.84% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.37% 87.21% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.74% 89.95% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.46% 90.41% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.37% 91.78% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.11% 95.89% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.91% 96.80% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.91% 97.72% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.46% 98.17% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.91% 99.09% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.91% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 219 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.678795 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.807623 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed +system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed +system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed +system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed +system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed +system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed +system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed +system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 178 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 101 0.05% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3850 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169235 91.57% 93.74% # number of callpals executed -system.cpu0.kern.callpal::rdps 6384 3.45% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4673 2.53% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 133 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184824 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7179 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1251 # number of protection mode switches +system.cpu0.kern.callpal::wripir 383 0.25% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3188 2.04% 2.29% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.32% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed +system.cpu0.kern.callpal::swpipl 141921 90.80% 93.12% # number of callpals executed +system.cpu0.kern.callpal::rdps 6055 3.87% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4242 2.71% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 315 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 156308 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6637 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1250 -system.cpu0.kern.mode_good::user 1251 +system.cpu0.kern.mode_good::kernel 1098 +system.cpu0.kern.mode_good::user 1098 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.174119 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.165436 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.296679 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901642531000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1904721500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.283904 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1900423407500 99.92% 99.92% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1609733000 0.08% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3851 # number of times the context was actually changed +system.cpu0.kern.swap_context 3189 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2262 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38430 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10197 33.29% 33.29% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1926 6.29% 39.58% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 101 0.33% 39.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18406 60.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30630 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10185 45.68% 45.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1926 8.64% 54.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 101 0.45% 54.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10084 45.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22296 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876291886000 98.58% 98.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533607500 0.03% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 52904000 0.00% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 26445439500 1.39% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903323837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998823 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2560 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 70963 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 22970 38.17% 38.17% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.20% 41.37% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 383 0.64% 42.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 34900 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 60178 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22406 47.94% 47.94% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 4.12% 52.06% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 383 0.82% 52.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22023 47.12% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 46737 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874192202500 98.50% 98.50% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532510000 0.03% 98.53% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 178162000 0.01% 98.54% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 27779026000 1.46% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1902681900500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975446 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.547865 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.727914 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.28% 10.28% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.93% 11.21% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.35% 20.56% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.93% 21.50% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.54% 28.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.80% 30.84% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.80% 33.64% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.67% 38.32% # number of syscalls executed -system.cpu1.kern.syscall::45 18 16.82% 55.14% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.80% 57.94% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.93% 58.88% # number of syscalls executed -system.cpu1.kern.syscall::71 31 28.97% 87.85% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.35% 97.20% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.80% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 107 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.631032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.776646 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed +system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed +system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed +system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed +system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed +system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed +system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed +system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed +system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 148 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 9 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.04% # number of callpals executed -system.cpu1.kern.callpal::swpctx 385 1.22% 1.26% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.27% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.29% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26077 82.56% 83.85% # number of callpals executed -system.cpu1.kern.callpal::rdps 2376 7.52% 91.38% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.38% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.39% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.40% # number of callpals executed -system.cpu1.kern.callpal::rti 2525 7.99% 99.40% # number of callpals executed -system.cpu1.kern.callpal::callsys 142 0.45% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 47 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 283 0.45% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1593 2.54% 3.00% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 3.00% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.01% # number of callpals executed +system.cpu1.kern.callpal::swpipl 54358 86.66% 89.67% # number of callpals executed +system.cpu1.kern.callpal::rdps 2709 4.32% 93.99% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.99% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 94.00% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 94.00% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.01% # number of callpals executed +system.cpu1.kern.callpal::rti 3511 5.60% 99.60% # number of callpals executed +system.cpu1.kern.callpal::callsys 200 0.32% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 48 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31584 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 861 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 514 -system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 26 -system.cpu1.kern.mode_switch_good::kernel 0.596980 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 62728 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1948 # number of protection mode switches +system.cpu1.kern.mode_switch::user 639 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2607 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 948 +system.cpu1.kern.mode_good::user 639 +system.cpu1.kern.mode_good::idle 309 +system.cpu1.kern.mode_switch_good::kernel 0.486653 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.302353 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2103355500 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 871184500 0.05% 0.16% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1899849485000 99.84% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 386 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.118527 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.365037 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6500961500 0.34% 0.34% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1047066000 0.06% 0.40% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1895133865000 99.60% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1594 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 05077073e..76f868d7e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.855236 # Nu sim_ticks 1855236450500 # Number of ticks simulated final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87142 # Simulator instruction rate (inst/s) -host_op_rate 87142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3050446700 # Simulator tick rate (ticks/s) -host_mem_usage 299400 # Number of bytes of host memory used -host_seconds 608.19 # Real time elapsed on the host +host_inst_rate 182093 # Simulator instruction rate (inst/s) +host_op_rate 182093 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6374280472 # Simulator tick rate (ticks/s) +host_mem_usage 298212 # Number of bytes of host memory used +host_seconds 291.05 # Real time elapsed on the host sim_insts 52998368 # Number of instructions simulated sim_ops 52998368 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory @@ -87,11 +87,11 @@ system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +121,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -258,12 +258,12 @@ system.cpu.iq.iqSquashedOperandsExamined 3652702 # Nu system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle @@ -521,11 +521,11 @@ system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -541,24 +541,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1402622 # number of replacements system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use @@ -595,16 +595,16 @@ system.cpu.dcache.overall_misses::cpu.data 3739889 # system.cpu.dcache.overall_misses::total 3739889 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses) @@ -631,22 +631,22 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.254608 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.254608 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24545.090425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24545.090425 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1615102 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 442 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7343.815084 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24555.555556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.681144 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks @@ -675,16 +675,16 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402021809 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402021809 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402034783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402034783 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065688309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32065688309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065688309 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32065688309 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065701283 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32065701283 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065701283 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles @@ -705,16 +705,16 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.470406 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.470406 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,19 +765,19 @@ system.cpu.l2cache.demand_misses::total 404416 # nu system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses system.cpu.l2cache.overall_misses::total 404416 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808284498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808283500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15073473498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15073472500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187378482 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6187378482 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 808284498 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20452567482 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21260851980 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 808284498 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20452567482 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21260851980 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6187369500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 808283500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20452558500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21260842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 808283500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20452558500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21260842000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses) @@ -808,19 +808,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.166826 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.590720 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.524850 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.851444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.847991 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.091888 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.091888 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52571.737963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52571.737963 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.014041 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.014041 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52571.713285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52571.713285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,25 +850,25 @@ system.cpu.l2cache.demand_mshr_misses::total 404415 system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986768000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609687500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777818000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16400737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777818000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16400737500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses @@ -882,19 +882,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.798680 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.529821 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40167.064542 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.094297 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.094297 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |