diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 5394 insertions, 5350 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index fcaff51da..002e59ef5 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906052 # Number of seconds simulated -sim_ticks 1906052165500 # Number of ticks simulated -final_tick 1906052165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.907083 # Number of seconds simulated +sim_ticks 1907083088000 # Number of ticks simulated +final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263346 # Simulator instruction rate (inst/s) -host_op_rate 263346 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8940174363 # Simulator tick rate (ticks/s) -host_mem_usage 335264 # Number of bytes of host memory used -host_seconds 213.20 # Real time elapsed on the host -sim_insts 56145499 # Number of instructions simulated -sim_ops 56145499 # Number of ops (including micro ops) simulated +host_inst_rate 20030 # Simulator instruction rate (inst/s) +host_op_rate 20030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 680419212 # Simulator tick rate (ticks/s) +host_mem_usage 389460 # Number of bytes of host memory used +host_seconds 2802.81 # Real time elapsed on the host +sim_insts 56139550 # Number of instructions simulated +sim_ops 56139550 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25904320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1044672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1044672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7563072 # Number of bytes written to this memory -system.physmem.bytes_written::total 7563072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388417 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25899200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1045632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1045632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7558144 # Number of bytes written to this memory +system.physmem.bytes_written::total 7558144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388322 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404755 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118173 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118173 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 548082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13041977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13590562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548082 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548082 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3967925 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3967925 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3967925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13041977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17558487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404755 # Number of read requests accepted -system.physmem.writeReqs 118173 # Number of write requests accepted -system.physmem.readBursts 404755 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118173 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25897216 # Total number of bytes read from DRAM +system.physmem.num_reads::total 404675 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118096 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118096 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 548289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13031738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13580530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 548289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 548289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3963196 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3963196 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3963196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 548289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13031738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17543726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404675 # Number of read requests accepted +system.physmem.writeReqs 118096 # Number of write requests accepted +system.physmem.readBursts 404675 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118096 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25892096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25904320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7563072 # Total written bytes from the system interface side +system.physmem.bytesWritten 7556352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25899200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7558144 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25477 # Per bank write bursts -system.physmem.perBankRdBursts::1 25704 # Per bank write bursts -system.physmem.perBankRdBursts::2 25816 # Per bank write bursts -system.physmem.perBankRdBursts::3 25781 # Per bank write bursts -system.physmem.perBankRdBursts::4 25083 # Per bank write bursts -system.physmem.perBankRdBursts::5 25010 # Per bank write bursts -system.physmem.perBankRdBursts::6 24709 # Per bank write bursts -system.physmem.perBankRdBursts::7 24576 # Per bank write bursts -system.physmem.perBankRdBursts::8 25196 # Per bank write bursts -system.physmem.perBankRdBursts::9 25297 # Per bank write bursts -system.physmem.perBankRdBursts::10 25389 # Per bank write bursts -system.physmem.perBankRdBursts::11 25021 # Per bank write bursts -system.physmem.perBankRdBursts::12 24534 # Per bank write bursts -system.physmem.perBankRdBursts::13 25530 # Per bank write bursts -system.physmem.perBankRdBursts::14 25795 # Per bank write bursts -system.physmem.perBankRdBursts::15 25726 # Per bank write bursts -system.physmem.perBankWrBursts::0 7822 # Per bank write bursts -system.physmem.perBankWrBursts::1 7672 # Per bank write bursts -system.physmem.perBankWrBursts::2 8075 # Per bank write bursts -system.physmem.perBankWrBursts::3 7745 # Per bank write bursts -system.physmem.perBankWrBursts::4 7196 # Per bank write bursts -system.physmem.perBankWrBursts::5 7016 # Per bank write bursts -system.physmem.perBankWrBursts::6 6702 # Per bank write bursts -system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7309 # Per bank write bursts -system.physmem.perBankWrBursts::9 6908 # Per bank write bursts -system.physmem.perBankWrBursts::10 7271 # Per bank write bursts -system.physmem.perBankWrBursts::11 7002 # Per bank write bursts -system.physmem.perBankWrBursts::12 7086 # Per bank write bursts -system.physmem.perBankWrBursts::13 7981 # Per bank write bursts -system.physmem.perBankWrBursts::14 7993 # Per bank write bursts -system.physmem.perBankWrBursts::15 7947 # Per bank write bursts +system.physmem.perBankRdBursts::0 25475 # Per bank write bursts +system.physmem.perBankRdBursts::1 25702 # Per bank write bursts +system.physmem.perBankRdBursts::2 25824 # Per bank write bursts +system.physmem.perBankRdBursts::3 25771 # Per bank write bursts +system.physmem.perBankRdBursts::4 25094 # Per bank write bursts +system.physmem.perBankRdBursts::5 25022 # Per bank write bursts +system.physmem.perBankRdBursts::6 24642 # Per bank write bursts +system.physmem.perBankRdBursts::7 24532 # Per bank write bursts +system.physmem.perBankRdBursts::8 25301 # Per bank write bursts +system.physmem.perBankRdBursts::9 25195 # Per bank write bursts +system.physmem.perBankRdBursts::10 25365 # Per bank write bursts +system.physmem.perBankRdBursts::11 25031 # Per bank write bursts +system.physmem.perBankRdBursts::12 24528 # Per bank write bursts +system.physmem.perBankRdBursts::13 25559 # Per bank write bursts +system.physmem.perBankRdBursts::14 25792 # Per bank write bursts +system.physmem.perBankRdBursts::15 25731 # Per bank write bursts +system.physmem.perBankWrBursts::0 7824 # Per bank write bursts +system.physmem.perBankWrBursts::1 7667 # Per bank write bursts +system.physmem.perBankWrBursts::2 8078 # Per bank write bursts +system.physmem.perBankWrBursts::3 7735 # Per bank write bursts +system.physmem.perBankWrBursts::4 7199 # Per bank write bursts +system.physmem.perBankWrBursts::5 7011 # Per bank write bursts +system.physmem.perBankWrBursts::6 6644 # Per bank write bursts +system.physmem.perBankWrBursts::7 6403 # Per bank write bursts +system.physmem.perBankWrBursts::8 7407 # Per bank write bursts +system.physmem.perBankWrBursts::9 6813 # Per bank write bursts +system.physmem.perBankWrBursts::10 7251 # Per bank write bursts +system.physmem.perBankWrBursts::11 7009 # Per bank write bursts +system.physmem.perBankWrBursts::12 7080 # Per bank write bursts +system.physmem.perBankWrBursts::13 8008 # Per bank write bursts +system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankWrBursts::15 7944 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1906043365500 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1907074301500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404755 # Read request sizes (log2) +system.physmem.readPktSize::6 404675 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118173 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118096 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,186 +148,191 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64457 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 519.089377 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 317.985274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 407.069012 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14849 23.04% 23.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11122 17.25% 40.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4951 7.68% 47.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3330 5.17% 53.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2494 3.87% 57.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1955 3.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4176 6.48% 66.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1342 2.08% 68.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20238 31.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64457 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.462207 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2902.463532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5289 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64552 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 518.162845 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 316.762326 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 407.336965 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15022 23.27% 23.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11126 17.24% 40.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5008 7.76% 48.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3170 4.91% 53.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2578 3.99% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1854 2.87% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4219 6.54% 66.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1366 2.12% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20209 31.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64552 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5276 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.676839 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2890.632458 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5273 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.326531 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.072850 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.540172 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4687 88.57% 88.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 34 0.64% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 32 0.60% 89.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 42 0.79% 90.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 211 3.99% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 8 0.15% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 13 0.25% 94.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 25 0.47% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 188 3.55% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.06% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 3 0.06% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.06% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.09% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 11 0.21% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 9 0.17% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5276 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5276 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.378317 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.075849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.638302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4671 88.53% 88.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 37 0.70% 89.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 29 0.55% 89.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 43 0.82% 90.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 200 3.79% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.21% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 32 0.61% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 177 3.35% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.13% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 14 0.27% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.08% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.08% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.09% 99.79% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-199 1 0.02% 99.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::200-207 3 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads -system.physmem.totQLat 2635925000 # Total ticks spent queuing -system.physmem.totMemAccLat 10223000000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6514.18 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::208-215 4 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5276 # Writes before turning the bus around for reads +system.physmem.totQLat 2650883750 # Total ticks spent queuing +system.physmem.totMemAccLat 10236458750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2022820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6552.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25264.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25302.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.96 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.36 # Average write queue length when enqueuing -system.physmem.readRowHits 362809 # Number of row buffer hits during reads -system.physmem.writeRowHits 95530 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.84 # Row buffer hit rate for writes -system.physmem.avgGap 3644944.17 # Average gap between requests -system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 238124880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 129929250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 380084400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67910384250 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1084060020000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278789321900 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.910378 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1803172860750 # Time in different power states -system.physmem_0.memoryStateTime::REF 63647220000 # Time in different power states +system.physmem.avgWrQLen 21.50 # Average write queue length when enqueuing +system.physmem.readRowHits 362672 # Number of row buffer hits during reads +system.physmem.writeRowHits 95408 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes +system.physmem.avgGap 3648010.89 # Average gap between requests +system.physmem.pageHitRate 87.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238359240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130057125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1576083600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 379475280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124561092240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67798389510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084774932000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1279458388995 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.899637 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1804362652750 # Time in different power states +system.physmem_0.memoryStateTime::REF 63681540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39230820500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39034493500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249170040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135955875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579406400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385540560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68468592375 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1083570372000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278882999570 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.959521 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1802360809750 # Time in different power states -system.physmem_1.memoryStateTime::REF 63647220000 # Time in different power states +system.physmem_1.actEnergy 249653880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136219875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579515600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385605360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124561092240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68553947025 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1084112170500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1279578204480 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.962459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1803261638750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63681540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 40042885250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 40135521250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15006509 # Number of BP lookups -system.cpu.branchPred.condPredicted 13016597 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 371031 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9764467 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5201318 # Number of BTB hits +system.cpu.branchPred.lookups 15213605 # Number of BP lookups +system.cpu.branchPred.condPredicted 13089935 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 512661 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11946485 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4550663 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.267813 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807808 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 31462 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 38.092066 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 861069 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32299 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6536873 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 544356 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5992517 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 219108 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9242631 # DTB read hits -system.cpu.dtb.read_misses 17134 # DTB read misses +system.cpu.dtb.read_hits 9320625 # DTB read hits +system.cpu.dtb.read_misses 17559 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 765515 # DTB read accesses -system.cpu.dtb.write_hits 6388389 # DTB write hits -system.cpu.dtb.write_misses 2336 # DTB write misses -system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298460 # DTB write accesses -system.cpu.dtb.data_hits 15631020 # DTB hits -system.cpu.dtb.data_misses 19470 # DTB misses -system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1063975 # DTB accesses -system.cpu.itb.fetch_hits 4014011 # ITB hits -system.cpu.itb.fetch_misses 6826 # ITB misses -system.cpu.itb.fetch_acv 642 # ITB acv -system.cpu.itb.fetch_accesses 4020837 # ITB accesses +system.cpu.dtb.read_accesses 766669 # DTB read accesses +system.cpu.dtb.write_hits 6392876 # DTB write hits +system.cpu.dtb.write_misses 2428 # DTB write misses +system.cpu.dtb.write_acv 159 # DTB write access violations +system.cpu.dtb.write_accesses 298894 # DTB write accesses +system.cpu.dtb.data_hits 15713501 # DTB hits +system.cpu.dtb.data_misses 19987 # DTB misses +system.cpu.dtb.data_acv 370 # DTB access violations +system.cpu.dtb.data_accesses 1065563 # DTB accesses +system.cpu.itb.fetch_hits 4013626 # ITB hits +system.cpu.itb.fetch_misses 6348 # ITB misses +system.cpu.itb.fetch_acv 677 # ITB acv +system.cpu.itb.fetch_accesses 4019974 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -340,39 +345,74 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 221712638 # number of cpu cycles simulated +system.cpu.numCycles 223105667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56145499 # Number of instructions committed -system.cpu.committedOps 56145499 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2504937 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5531 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3590391693 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.948894 # CPI: cycles per instruction -system.cpu.ipc 0.253235 # IPC: instructions per cycle +system.cpu.committedInsts 56139550 # Number of instructions committed +system.cpu.committedOps 56139550 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2984225 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5570 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3591060509 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.974126 # CPI: cycles per instruction +system.cpu.ipc 0.251628 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199335 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36193553 64.47% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60844 0.11% 70.28% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::MemRead 9319847 16.60% 86.95% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6372583 11.35% 98.30% # Class of committed instruction +system.cpu.op_class_0::IprAccess 951665 1.70% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 56139550 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211539 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74805 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105907 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182749 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837274169000 96.39% 96.39% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 83596500 0.00% 96.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 707455500 0.04% 96.43% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 67985922500 3.57% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1906051143500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211602 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74817 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105924 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182777 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73450 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73450 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148936 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1838095236500 96.38% 96.38% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 85937000 0.00% 96.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 709530500 0.04% 96.42% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 68191372500 3.58% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1907082076500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981729 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693429 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814855 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693422 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814851 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -408,115 +448,115 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175582 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175610 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5130 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192473 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches +system.cpu.kern.callpal::total 192505 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5879 # number of protection mode switches system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches system.cpu.kern.mode_good::kernel 1907 system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.324541 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324375 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 38725166000 2.03% 2.03% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4529345500 0.24% 2.27% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862796622000 97.73% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 84517271 # Number of cycles that the object actually ticked -system.cpu.idleCycles 137195367 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395430 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13774435 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.867484 # Average number of references to valid blocks. +system.cpu.kern.mode_switch_good::total 0.392750 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 38852804500 2.04% 2.04% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4558296500 0.24% 2.28% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1863670965500 97.72% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.tickCycles 85299333 # Number of cycles that the object actually ticked +system.cpu.idleCycles 137806334 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1394573 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.976747 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13828974 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395085 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.912639 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.976747 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63669791 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63669791 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7815717 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815717 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576828 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576828 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182828 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182828 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199029 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199029 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13392545 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13392545 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13392545 # number of overall hits -system.cpu.dcache.overall_hits::total 13392545 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201618 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201618 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 575220 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 575220 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17222 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17222 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1776838 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1776838 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1776838 # number of overall misses -system.cpu.dcache.overall_misses::total 1776838 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 46968047500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 46968047500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964546500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33964546500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234897500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 234897500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80932594000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80932594000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80932594000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80932594000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9017335 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9017335 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152048 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152048 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200050 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200050 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15169383 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15169383 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15169383 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15169383 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133256 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133256 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093501 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093501 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086088 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086088 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117133 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117133 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117133 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117133 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39087.336824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39087.336824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59046.184938 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59046.184938 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13639.385669 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13639.385669 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45548.662287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45548.662287 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63880747 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63880747 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7869575 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7869575 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576818 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576818 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183500 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183500 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199049 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199049 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13446393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13446393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13446393 # number of overall hits +system.cpu.dcache.overall_hits::total 13446393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201253 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201253 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 574650 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 574650 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16570 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1775903 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1775903 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1775903 # number of overall misses +system.cpu.dcache.overall_misses::total 1775903 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46959686500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46959686500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33959629000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33959629000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 226795500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 226795500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80919315500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80919315500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80919315500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80919315500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9070828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9070828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200070 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200070 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199049 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199049 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15222296 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15222296 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15222296 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15222296 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132430 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.132430 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093417 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093417 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082821 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082821 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.116665 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.116665 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.116665 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.116665 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.253256 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.253256 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59096.195945 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59096.195945 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13687.115269 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13687.115269 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45565.166284 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45565.166284 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -525,129 +565,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838230 # number of writebacks -system.cpu.dcache.writebacks::total 838230 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127262 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127262 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270814 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270814 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837991 # number of writebacks +system.cpu.dcache.writebacks::total 837991 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126783 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61084599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61084599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61084599500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61084599500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528608000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528608000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2161966000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2161966000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3690574000 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1460482 # number of replacements -system.cpu.icache.tags.tagsinuse 508.105568 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125061.315597 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -805,129 +845,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76661 # number of writebacks -system.cpu.l2cache.writebacks::total 76661 # number of writebacks -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405188 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1175000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1175000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13674958500 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383211 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383211 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011172 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249379 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249379 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141820 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113720.298448 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.758869 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.758869 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213196.799667 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213196.799667 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211044.721585 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211044.721585 # average overall mshr uncacheable latency +system.cpu.l2cache.writebacks::writebacks 76584 # number of writebacks +system.cpu.l2cache.writebacks::total 76584 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116580 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116580 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16339 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16339 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272190 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272190 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405109 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16339 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388770 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405109 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1037000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1037000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13677551000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13677551000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1984030500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1984030500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30953906500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30953906500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1984030500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631457500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46615488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1984030500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631457500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46615488000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441963500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441963500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051300500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051300500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3493264000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3493264000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383353 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383353 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011100 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249486 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249486 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278666 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141294 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278666 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141294 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69133.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69133.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117323.305884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117323.305884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121429.126630 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121429.126630 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113721.688894 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113721.688894 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5713060 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856101 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1990 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1247 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2559783 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 956411 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1460482 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 820279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461167 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091716 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 956097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1471396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819662 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304106 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304106 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1472080 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4382756 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4220664 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8603420 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186981696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041437 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 330023133 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 423201 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3296691 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001034 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032145 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4415500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4218097 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8633597 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188378880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142971324 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 331350204 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 423123 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3306675 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001025 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031993 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3293281 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3410 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3303287 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3296691 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5168333000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3306675 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5189065000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2192017465 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2208337564 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105681496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2104397493 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -941,69 +981,69 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7107 # Transaction distribution -system.iobus.trans_dist::ReadResp 7107 # Transaction distribution -system.iobus.trans_dist::WriteReq 51176 # Transaction distribution -system.iobus.trans_dist::WriteResp 51176 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5110 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7103 # Transaction distribution +system.iobus.trans_dist::ReadResp 7103 # Transaction distribution +system.iobus.trans_dist::WriteReq 51175 # Transaction distribution +system.iobus.trans_dist::WriteResp 51175 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116566 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44381 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5419000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5407500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 786000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 805000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 186000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 188500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14810500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14677500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2309500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5936500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6005500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215720167 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215722666 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.290842 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.298739 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1748612862000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.290842 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080678 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080678 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1748617417000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.298739 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081171 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081171 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1019,8 +1059,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244742784 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5244742784 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245324283 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5245324283 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles @@ -1043,17 +1083,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126221.187524 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126221.187524 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.833333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1069,8 +1109,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165341974 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165341974 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165924983 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165924983 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles @@ -1085,58 +1125,58 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.848816 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.848816 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 6934 # Transaction distribution -system.membus.trans_dist::ReadResp 295622 # Transaction distribution -system.membus.trans_dist::WriteReq 9624 # Transaction distribution -system.membus.trans_dist::WriteResp 9624 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118173 # Transaction distribution -system.membus.trans_dist::CleanEvict 262241 # Transaction distribution -system.membus.trans_dist::UpgradeReq 175 # Transaction distribution +system.membus.trans_dist::ReadReq 6930 # Transaction distribution +system.membus.trans_dist::ReadResp 295608 # Transaction distribution +system.membus.trans_dist::WriteReq 9623 # Transaction distribution +system.membus.trans_dist::WriteResp 9623 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118096 # Transaction distribution +system.membus.trans_dist::CleanEvict 262242 # Transaction distribution +system.membus.trans_dist::UpgradeReq 167 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116498 # Transaction distribution -system.membus.trans_dist::ReadExResp 116498 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288705 # Transaction distribution -system.membus.trans_dist::BadAddressError 17 # Transaction distribution +system.membus.trans_dist::ReadExReq 116428 # Transaction distribution +system.membus.trans_dist::ReadExResp 116428 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288702 # Transaction distribution +system.membus.trans_dist::BadAddressError 24 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148657 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181807 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148413 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181567 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265232 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44381 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854045 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1264992 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30799616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30843964 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33511773 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33501692 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 843910 # Request fanout histogram +system.membus.snoop_fanout::samples 843750 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843910 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843750 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843910 # Request fanout histogram -system.membus.reqLayer0.occupancy 29565500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843750 # Request fanout histogram +system.membus.reqLayer0.occupancy 29507500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319337462 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1318874217 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2159897250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2159448000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 1b3e8deca..1db8d7737 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.924156 # Number of seconds simulated -sim_ticks 1924156135000 # Number of ticks simulated -final_tick 1924156135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.929078 # Number of seconds simulated +sim_ticks 1929077876500 # Number of ticks simulated +final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131013 # Simulator instruction rate (inst/s) -host_op_rate 131013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4442767791 # Simulator tick rate (ticks/s) -host_mem_usage 340636 # Number of bytes of host memory used -host_seconds 433.10 # Real time elapsed on the host -sim_insts 56741431 # Number of instructions simulated -sim_ops 56741431 # Number of ops (including micro ops) simulated +host_inst_rate 158135 # Simulator instruction rate (inst/s) +host_op_rate 158134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5371969736 # Simulator tick rate (ticks/s) +host_mem_usage 339544 # Number of bytes of host memory used +host_seconds 359.10 # Real time elapsed on the host +sim_insts 56786201 # Number of instructions simulated +sim_ops 56786201 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 858624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24610432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 114304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 675520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 856320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24603328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 123072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 684608 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26259840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 858624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 114304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 972928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7862976 # Number of bytes written to this memory -system.physmem.bytes_written::total 7862976 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1786 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10555 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26268288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 856320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 979392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7871488 # Number of bytes written to this memory +system.physmem.bytes_written::total 7871488 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13380 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384427 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10697 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410310 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122859 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122859 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 446234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12790247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 351073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13647458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 446234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 505639 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4086454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4086454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4086454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 446234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12790247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 351073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17733912 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410310 # Number of read requests accepted -system.physmem.writeReqs 122859 # Number of write requests accepted -system.physmem.readBursts 410310 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122859 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26253184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 7861568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26259840 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7862976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122992 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122992 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 443901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12753932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 354889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13617018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 443901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 507700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4080441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4080441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4080441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 443901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12753932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 354889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17697459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410442 # Number of read requests accepted +system.physmem.writeReqs 122992 # Number of write requests accepted +system.physmem.readBursts 410442 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122992 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue +system.physmem.bytesWritten 7869440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26268288 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7871488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26222 # Per bank write bursts -system.physmem.perBankRdBursts::1 25818 # Per bank write bursts -system.physmem.perBankRdBursts::2 25998 # Per bank write bursts -system.physmem.perBankRdBursts::3 25425 # Per bank write bursts -system.physmem.perBankRdBursts::4 25236 # Per bank write bursts -system.physmem.perBankRdBursts::5 25660 # Per bank write bursts -system.physmem.perBankRdBursts::6 25903 # Per bank write bursts -system.physmem.perBankRdBursts::7 25509 # Per bank write bursts -system.physmem.perBankRdBursts::8 25730 # Per bank write bursts -system.physmem.perBankRdBursts::9 25899 # Per bank write bursts -system.physmem.perBankRdBursts::10 25820 # Per bank write bursts -system.physmem.perBankRdBursts::11 25243 # Per bank write bursts -system.physmem.perBankRdBursts::12 25580 # Per bank write bursts -system.physmem.perBankRdBursts::13 25319 # Per bank write bursts -system.physmem.perBankRdBursts::14 25297 # Per bank write bursts -system.physmem.perBankRdBursts::15 25547 # Per bank write bursts -system.physmem.perBankWrBursts::0 8465 # Per bank write bursts -system.physmem.perBankWrBursts::1 7798 # Per bank write bursts -system.physmem.perBankWrBursts::2 8098 # Per bank write bursts -system.physmem.perBankWrBursts::3 7477 # Per bank write bursts -system.physmem.perBankWrBursts::4 7191 # Per bank write bursts -system.physmem.perBankWrBursts::5 7211 # Per bank write bursts -system.physmem.perBankWrBursts::6 7415 # Per bank write bursts -system.physmem.perBankWrBursts::7 7062 # Per bank write bursts -system.physmem.perBankWrBursts::8 7370 # Per bank write bursts -system.physmem.perBankWrBursts::9 7621 # Per bank write bursts -system.physmem.perBankWrBursts::10 7713 # Per bank write bursts -system.physmem.perBankWrBursts::11 7334 # Per bank write bursts -system.physmem.perBankWrBursts::12 7954 # Per bank write bursts -system.physmem.perBankWrBursts::13 8039 # Per bank write bursts -system.physmem.perBankWrBursts::14 8051 # Per bank write bursts -system.physmem.perBankWrBursts::15 8038 # Per bank write bursts +system.physmem.perBankRdBursts::0 26358 # Per bank write bursts +system.physmem.perBankRdBursts::1 25853 # Per bank write bursts +system.physmem.perBankRdBursts::2 25982 # Per bank write bursts +system.physmem.perBankRdBursts::3 25455 # Per bank write bursts +system.physmem.perBankRdBursts::4 25391 # Per bank write bursts +system.physmem.perBankRdBursts::5 25779 # Per bank write bursts +system.physmem.perBankRdBursts::6 25718 # Per bank write bursts +system.physmem.perBankRdBursts::7 25362 # Per bank write bursts +system.physmem.perBankRdBursts::8 25502 # Per bank write bursts +system.physmem.perBankRdBursts::9 25880 # Per bank write bursts +system.physmem.perBankRdBursts::10 25847 # Per bank write bursts +system.physmem.perBankRdBursts::11 25125 # Per bank write bursts +system.physmem.perBankRdBursts::12 25573 # Per bank write bursts +system.physmem.perBankRdBursts::13 25368 # Per bank write bursts +system.physmem.perBankRdBursts::14 25415 # Per bank write bursts +system.physmem.perBankRdBursts::15 25720 # Per bank write bursts +system.physmem.perBankWrBursts::0 8608 # Per bank write bursts +system.physmem.perBankWrBursts::1 7821 # Per bank write bursts +system.physmem.perBankWrBursts::2 8027 # Per bank write bursts +system.physmem.perBankWrBursts::3 7496 # Per bank write bursts +system.physmem.perBankWrBursts::4 7316 # Per bank write bursts +system.physmem.perBankWrBursts::5 7320 # Per bank write bursts +system.physmem.perBankWrBursts::6 7241 # Per bank write bursts +system.physmem.perBankWrBursts::7 6937 # Per bank write bursts +system.physmem.perBankWrBursts::8 7156 # Per bank write bursts +system.physmem.perBankWrBursts::9 7588 # Per bank write bursts +system.physmem.perBankWrBursts::10 7741 # Per bank write bursts +system.physmem.perBankWrBursts::11 7304 # Per bank write bursts +system.physmem.perBankWrBursts::12 7945 # Per bank write bursts +system.physmem.perBankWrBursts::13 8097 # Per bank write bursts +system.physmem.perBankWrBursts::14 8174 # Per bank write bursts +system.physmem.perBankWrBursts::15 8189 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 1924155087500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1929076824500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410310 # Read request sizes (log2) +system.physmem.readPktSize::6 410442 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122859 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122992 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -158,187 +158,194 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65042 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 524.503429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 321.000815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 410.854297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14739 22.66% 22.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11347 17.45% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5326 8.19% 48.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2916 4.48% 52.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2591 3.98% 56.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1650 2.54% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3760 5.78% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1191 1.83% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21522 33.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65042 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5512 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.419267 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2843.464031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5509 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 522.399241 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.882184 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.899985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14976 22.92% 22.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11360 17.39% 40.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5432 8.31% 48.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2850 4.36% 52.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2530 3.87% 56.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1671 2.56% 59.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3857 5.90% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1188 1.82% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21470 32.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65334 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5522 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.304962 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2840.771031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5519 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5512 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5512 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.285377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.129455 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.189692 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4905 88.99% 88.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 46 0.83% 89.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 19 0.34% 90.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 46 0.83% 91.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 202 3.66% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 8 0.15% 94.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 9 0.16% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 26 0.47% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 191 3.47% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.09% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 3 0.05% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.16% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.09% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.09% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 8 0.15% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5512 # Writes before turning the bus around for reads -system.physmem.totQLat 4435069250 # Total ticks spent queuing -system.physmem.totMemAccLat 12126431750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10811.81 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5522 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5522 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.267294 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.111227 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.252131 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4917 89.04% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 44 0.80% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 22 0.40% 90.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 38 0.69% 90.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 207 3.75% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.11% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 12 0.22% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 27 0.49% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 186 3.37% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.11% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 8 0.14% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.14% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 6 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.07% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5522 # Writes before turning the bus around for reads +system.physmem.totQLat 4416821750 # Total ticks spent queuing +system.physmem.totMemAccLat 12110471750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10764.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29561.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29514.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing -system.physmem.readRowHits 369385 # Number of row buffer hits during reads -system.physmem.writeRowHits 98616 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.27 # Row buffer hit rate for writes -system.physmem.avgGap 3608902.78 # Average gap between requests -system.physmem.pageHitRate 87.79 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245503440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133955250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1605013800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 393446160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125676364320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63335469060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1098934930500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1290324682530 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.593273 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1827969159500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64251720000 # Time in different power states +system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.77 # Average write queue length when enqueuing +system.physmem.readRowHits 369361 # Number of row buffer hits during reads +system.physmem.writeRowHits 98593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.16 # Row buffer hit rate for writes +system.physmem.avgGap 3616336.46 # Average gap between requests +system.physmem.pageHitRate 87.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 246047760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134252250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1606004400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 393763680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63271865610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101943260750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1293592968690 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.576874 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832974418500 # Time in different power states +system.physmem_0.memoryStateTime::REF 64416040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31933066750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31684384000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246214080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134343000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1594593000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402537600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125676364320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62736550965 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1099460297250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1290250900215 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.554927 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1828845452000 # Time in different power states -system.physmem_1.memoryStateTime::REF 64251720000 # Time in different power states +system.physmem_1.actEnergy 247877280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135250500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1594554000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 403017120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63221156415 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101987750750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1293587380305 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.573972 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1833051648500 # Time in different power states +system.physmem_1.memoryStateTime::REF 64416040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31056774250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31607167750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 15943421 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13949758 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 305064 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10079074 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5240379 # Number of BTB hits +system.cpu0.branchPred.lookups 17100345 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14625316 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 474432 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10759421 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4832502 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.992663 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 792227 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17177 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 44.914145 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 945329 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 34555 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5020643 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 507910 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4512733 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 209375 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9007287 # DTB read hits -system.cpu0.dtb.read_misses 30074 # DTB read misses -system.cpu0.dtb.read_acv 538 # DTB read access violations -system.cpu0.dtb.read_accesses 622567 # DTB read accesses -system.cpu0.dtb.write_hits 5740520 # DTB write hits -system.cpu0.dtb.write_misses 6136 # DTB write misses -system.cpu0.dtb.write_acv 351 # DTB write access violations -system.cpu0.dtb.write_accesses 205436 # DTB write accesses -system.cpu0.dtb.data_hits 14747807 # DTB hits -system.cpu0.dtb.data_misses 36210 # DTB misses -system.cpu0.dtb.data_acv 889 # DTB access violations -system.cpu0.dtb.data_accesses 828003 # DTB accesses -system.cpu0.itb.fetch_hits 1373369 # ITB hits -system.cpu0.itb.fetch_misses 18540 # ITB misses -system.cpu0.itb.fetch_acv 561 # ITB acv -system.cpu0.itb.fetch_accesses 1391909 # ITB accesses +system.cpu0.dtb.read_hits 9634816 # DTB read hits +system.cpu0.dtb.read_misses 36704 # DTB read misses +system.cpu0.dtb.read_acv 586 # DTB read access violations +system.cpu0.dtb.read_accesses 618265 # DTB read accesses +system.cpu0.dtb.write_hits 5807101 # DTB write hits +system.cpu0.dtb.write_misses 8981 # DTB write misses +system.cpu0.dtb.write_acv 421 # DTB write access violations +system.cpu0.dtb.write_accesses 195454 # DTB write accesses +system.cpu0.dtb.data_hits 15441917 # DTB hits +system.cpu0.dtb.data_misses 45685 # DTB misses +system.cpu0.dtb.data_acv 1007 # DTB access violations +system.cpu0.dtb.data_accesses 813719 # DTB accesses +system.cpu0.itb.fetch_hits 1375653 # ITB hits +system.cpu0.itb.fetch_misses 7396 # ITB misses +system.cpu0.itb.fetch_acv 601 # ITB acv +system.cpu0.itb.fetch_accesses 1383049 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,596 +358,600 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 146208045 # number of cpu cycles simulated +system.cpu0.numCycles 146500468 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26065681 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69138767 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 15943421 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6032606 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 111931288 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1030760 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 960 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 863166 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 466353 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7979260 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223234 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 139872418 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.494299 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.727987 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26225748 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 74880065 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 17100345 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6285741 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 112740313 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1369370 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 398 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 147220 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 425638 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 504 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8642043 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 322305 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 140254918 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.533885 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.795707 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 126942613 90.76% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 822727 0.59% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1793626 1.28% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 758856 0.54% 93.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2553230 1.83% 94.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559004 0.40% 95.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 640050 0.46% 95.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 814516 0.58% 96.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4987796 3.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 126345960 90.08% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 903115 0.64% 90.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1906918 1.36% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 803345 0.57% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2649453 1.89% 94.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 589849 0.42% 94.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 700559 0.50% 95.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 843084 0.60% 96.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5512635 3.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 139872418 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.109046 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472879 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21051176 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108291493 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8312277 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1736520 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 480951 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 505721 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 34877 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 60486220 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 106478 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 480951 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21868372 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 77772833 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19641346 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9147803 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10961111 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58426169 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 200234 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2003921 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 229197 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7028864 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39061354 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71018610 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 70882139 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 127236 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34481529 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4579825 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1435923 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 207898 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12319734 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9087403 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6005193 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1334507 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 982358 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52110504 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1852436 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51364410 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 50265 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6320051 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2764098 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1275155 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 139872418 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.367223 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.083437 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 140254918 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.116726 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.511125 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20974212 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 107876486 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8907132 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1841497 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 655590 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 626155 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29675 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 64967024 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 87739 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 655590 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21855511 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 78567360 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18275925 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9798485 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11102045 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 62456562 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 201631 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2042440 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 306402 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7083961 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 42144620 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 75447660 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 75312247 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 126226 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34366321 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7778299 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1457881 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 236313 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12541674 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10026235 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6171298 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1512964 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 977849 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 55240015 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1897630 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 53565100 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 74212 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9657224 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4199823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1322202 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 140254918 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.381912 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.107336 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 118742134 84.89% 84.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9166235 6.55% 91.45% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3802026 2.72% 94.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2678681 1.92% 96.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2780722 1.99% 98.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1354022 0.97% 99.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 885059 0.63% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 353584 0.25% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109955 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 118450817 84.45% 84.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9324559 6.65% 91.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3896910 2.78% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2805800 2.00% 95.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2901850 2.07% 97.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1433856 1.02% 98.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 954902 0.68% 99.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 366563 0.26% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 119661 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 139872418 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 140254918 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 178057 18.55% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 457973 47.71% 66.26% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 323912 33.74% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 172960 16.73% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 530801 51.33% 68.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 330287 31.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3341 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35317882 68.76% 68.77% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56025 0.11% 68.88% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.88% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 27459 0.05% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1664 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.93% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9346041 18.20% 87.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5809377 11.31% 98.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 802621 1.56% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3306 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36704403 68.52% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56318 0.11% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 27375 0.05% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 10076531 18.81% 87.50% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5896825 11.01% 98.51% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 798690 1.49% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51364410 # Type of FU issued -system.cpu0.iq.rate 0.351310 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 959944 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018689 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 243048711 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60036028 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50017442 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 562736 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 263720 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 258274 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52017534 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 303479 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 574771 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 53565100 # Type of FU issued +system.cpu0.iq.rate 0.365631 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1034048 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019305 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 247915569 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 66533789 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51792941 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 577809 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 279350 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 262536 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 54284218 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 311624 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 608466 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1026959 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3812 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17061 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 487007 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2001818 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4069 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18629 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 679305 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18708 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 390954 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18387 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 376944 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 480951 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 74383875 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 944737 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57300574 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 113056 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9087403 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6005193 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1637090 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39248 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 704660 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17061 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 148957 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 344315 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 493272 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50873166 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9059669 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 491244 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 655590 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 75078561 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 955285 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 60714699 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 160012 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10026235 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6171298 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1682472 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 42874 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 711273 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18629 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 185912 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 515422 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 701334 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52870028 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9698038 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 695072 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3337634 # number of nop insts executed -system.cpu0.iew.exec_refs 14819622 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8093106 # Number of branches executed -system.cpu0.iew.exec_stores 5759953 # Number of stores executed -system.cpu0.iew.exec_rate 0.347951 # Inst execution rate -system.cpu0.iew.wb_sent 50383521 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50275716 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25952077 # num instructions producing a value -system.cpu0.iew.wb_consumers 35940166 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.343864 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.722091 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 6643709 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 577281 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 452311 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 138699255 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.364540 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.252346 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3577054 # number of nop insts executed +system.cpu0.iew.exec_refs 15531241 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8401878 # Number of branches executed +system.cpu0.iew.exec_stores 5833203 # Number of stores executed +system.cpu0.iew.exec_rate 0.360886 # Inst execution rate +system.cpu0.iew.wb_sent 52244753 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 52055477 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26703720 # num instructions producing a value +system.cpu0.iew.wb_consumers 36905470 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.355326 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723571 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10154720 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 575428 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 626255 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 138489248 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.363854 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.249176 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 120842585 87.13% 87.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7068214 5.10% 92.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3896866 2.81% 95.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2026273 1.46% 96.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1580895 1.14% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 566091 0.41% 98.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 426311 0.31% 98.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 427447 0.31% 98.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1864573 1.34% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 120648787 87.12% 87.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7115506 5.14% 92.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3823437 2.76% 95.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2034446 1.47% 96.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1589267 1.15% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 580000 0.42% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 430694 0.31% 98.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 453916 0.33% 98.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1813195 1.31% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 138699255 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50561379 # Number of instructions committed -system.cpu0.commit.committedOps 50561379 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 138489248 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50389922 # Number of instructions committed +system.cpu0.commit.committedOps 50389922 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13578630 # Number of memory references committed -system.cpu0.commit.loads 8060444 # Number of loads committed -system.cpu0.commit.membars 196368 # Number of memory barriers committed -system.cpu0.commit.branches 7652854 # Number of branches committed -system.cpu0.commit.fp_insts 255352 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46813547 # Number of committed integer instructions. -system.cpu0.commit.function_calls 647795 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2921820 5.78% 5.78% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32972422 65.21% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54875 0.11% 71.10% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.10% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 26997 0.05% 71.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1664 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8256812 16.33% 87.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5524169 10.93% 98.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 802620 1.59% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13516410 # Number of memory references committed +system.cpu0.commit.loads 8024417 # Number of loads committed +system.cpu0.commit.membars 195679 # Number of memory barriers committed +system.cpu0.commit.branches 7630866 # Number of branches committed +system.cpu0.commit.fp_insts 253714 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46654336 # Number of committed integer instructions. +system.cpu0.commit.function_calls 644656 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2912807 5.78% 5.78% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32876835 65.24% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54961 0.11% 71.13% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.13% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 26901 0.05% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1652 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8220096 16.31% 87.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5497981 10.91% 98.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 798689 1.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 50561379 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1864573 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 193850877 # The number of ROB reads -system.cpu0.rob.rob_writes 115577492 # The number of ROB writes -system.cpu0.timesIdled 518122 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6335627 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3701455446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47642888 # Number of Instructions Simulated -system.cpu0.committedOps 47642888 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 3.068833 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.068833 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.325857 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.325857 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66867100 # number of integer regfile reads -system.cpu0.int_regfile_writes 36418674 # number of integer regfile writes -system.cpu0.fp_regfile_reads 126247 # number of floating regfile reads -system.cpu0.fp_regfile_writes 127860 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1687235 # number of misc regfile reads -system.cpu0.misc_regfile_writes 805033 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1264949 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.087207 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10332814 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1265389 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.165721 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 50389922 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1813195 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 197034230 # The number of ROB reads +system.cpu0.rob.rob_writes 122856265 # The number of ROB writes +system.cpu0.timesIdled 490676 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6245550 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3710936476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47480420 # Number of Instructions Simulated +system.cpu0.committedOps 47480420 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.085492 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.085492 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.324097 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.324097 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 69229174 # number of integer regfile reads +system.cpu0.int_regfile_writes 37925510 # number of integer regfile writes +system.cpu0.fp_regfile_reads 125098 # number of floating regfile reads +system.cpu0.fp_regfile_writes 133204 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1692059 # number of misc regfile reads +system.cpu0.misc_regfile_writes 801866 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1263704 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.064166 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10905904 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1264137 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.627154 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.087207 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988452 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988452 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 440 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.859375 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 55743901 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 55743901 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6363552 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6363552 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3619661 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3619661 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160076 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160076 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184973 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 184973 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9983213 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9983213 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9983213 # number of overall hits -system.cpu0.dcache.overall_hits::total 9983213 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1569683 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1569683 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1696149 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1696149 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20607 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20607 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2893 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2893 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3265832 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3265832 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3265832 # number of overall misses -system.cpu0.dcache.overall_misses::total 3265832 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54492082500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54492082500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110535541459 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 110535541459 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385765500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 385765500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44605000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44605000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 165027623959 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 165027623959 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 165027623959 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 165027623959 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7933235 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7933235 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5315810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5315810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 180683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187866 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187866 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13249045 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13249045 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13249045 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13249045 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197862 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197862 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.319076 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.319076 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114051 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114051 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015399 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015399 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246496 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.246496 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.246496 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.246496 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34715.342206 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34715.342206 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65168.532634 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65168.532634 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18720.119377 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18720.119377 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15418.250951 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15418.250951 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50531.571728 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50531.571728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50531.571728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50531.571728 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6758088 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 13420 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 113551 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 96 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.515883 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 139.791667 # average number of cycles each access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.064166 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988407 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988407 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 433 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.845703 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 58069444 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 58069444 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6953524 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6953524 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3586613 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3586613 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 178977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 178977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184325 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 184325 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10540137 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10540137 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10540137 # number of overall hits +system.cpu0.dcache.overall_hits::total 10540137 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1569058 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1569058 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1703592 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1703592 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20226 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20226 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2959 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2959 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3272650 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3272650 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3272650 # number of overall misses +system.cpu0.dcache.overall_misses::total 3272650 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54620758000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54620758000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110116261626 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 110116261626 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 348212000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 348212000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46063500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46063500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 164737019626 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 164737019626 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 164737019626 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 164737019626 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8522582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8522582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5290205 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5290205 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 199203 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 199203 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187284 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187284 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13812787 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13812787 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13812787 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13812787 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184106 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.184106 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322028 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.322028 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101535 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101535 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015800 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015800 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236929 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.236929 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236929 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.236929 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34811.178427 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34811.178427 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64637.695895 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64637.695895 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17216.058539 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17216.058539 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15567.252450 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15567.252450 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50337.500077 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6721817 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 17671 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 111036 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 742386 # number of writebacks -system.cpu0.dcache.writebacks::total 742386 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 562218 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 562218 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1439926 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1439926 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4884 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4884 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2002144 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2002144 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2002144 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2002144 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007465 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1007465 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256223 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256223 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15723 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15723 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2893 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2893 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263688 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1263688 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263688 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1263688 # number of overall MSHR misses +system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks +system.cpu0.dcache.writebacks::total 741086 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 559859 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449235 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1449235 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5567 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5567 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2009094 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2009094 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2009094 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2009094 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1009199 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1009199 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254357 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 254357 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14659 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14659 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2959 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2959 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263556 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1263556 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263556 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1263556 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10093 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10093 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17124 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17124 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43361344000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43361344000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17653250388 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17653250388 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186143500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186143500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41712000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41712000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61014594388 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61014594388 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61014594388 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 61014594388 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1559676000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1559676000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293857500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293857500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3853533500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3853533500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126993 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126993 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048200 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048200 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087020 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087020 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015399 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015399 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095380 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095380 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095380 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095380 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43040.050027 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43040.050027 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68897.992717 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68897.992717 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.930230 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.930230 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14418.250951 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14418.250951 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48282.957809 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48282.957809 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48282.957809 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48282.957809 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221828.473901 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221828.473901 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227272.119291 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227272.119291 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225036.994861 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225036.994861 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10105 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10105 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17136 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17136 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43480023500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43480023500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17474692057 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17474692057 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 173733500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 173733500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 43104500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 43104500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60954715557 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 60954715557 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2296787000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2296787000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3855733000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3855733000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.073588 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.073588 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015800 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015800 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091477 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091477 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43083.696575 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43083.696575 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68701.439540 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68701.439540 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11851.661096 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11851.661096 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 894689 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.080310 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7039625 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 895201 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.863737 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42372449500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.080310 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992344 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992344 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 911237 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 911749 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.418764 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42368821500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.249711 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992675 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 196 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8874714 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8874714 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7039625 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7039625 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7039625 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7039625 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7039625 # number of overall hits -system.cpu0.icache.overall_hits::total 7039625 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 939633 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 939633 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 939633 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 939633 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 939633 # number of overall misses -system.cpu0.icache.overall_misses::total 939633 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14412797481 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14412797481 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14412797481 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14412797481 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14412797481 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14412797481 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7979258 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7979258 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7979258 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7979258 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7979258 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7979258 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117759 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117759 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117759 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117759 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117759 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117759 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15338.751918 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15338.751918 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15338.751918 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15338.751918 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15338.751918 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15338.751918 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 9737 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9554008 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9554008 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7675800 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7675800 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7675800 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7675800 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7675800 # number of overall hits +system.cpu0.icache.overall_hits::total 7675800 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 966240 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 966240 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 966240 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 966240 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 966240 # number of overall misses +system.cpu0.icache.overall_misses::total 966240 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14731064486 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14731064486 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14731064486 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14731064486 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14731064486 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14731064486 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8642040 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8642040 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8642040 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8642040 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8642040 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8642040 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111807 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111807 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111807 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111807 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111807 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111807 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15245.761391 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15245.761391 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15245.761391 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15245.761391 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 11439 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.784512 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 894689 # number of writebacks -system.cpu0.icache.writebacks::total 894689 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44177 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44177 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44177 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44177 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44177 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44177 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895456 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 895456 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 895456 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 895456 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 895456 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 895456 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12742984487 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12742984487 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12742984487 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12742984487 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12742984487 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12742984487 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112223 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.112223 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.112223 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14230.720981 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14230.720981 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14230.720981 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks +system.cpu0.icache.writebacks::total 911237 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54272 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54272 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54272 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54272 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54272 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 911968 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 911968 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 911968 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 911968 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 911968 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 911968 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12931897989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12931897989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12931897989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12931897989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12931897989 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12931897989 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105527 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105527 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105527 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3770405 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3287478 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 72852 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2172402 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 929208 # Number of BTB hits +system.cpu1.branchPred.lookups 4129053 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2303722 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 822541 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 42.773299 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 184259 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 5155 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 35.704872 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 211273 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8217 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1287279 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 153619 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1133660 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 37557 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2058998 # DTB read hits -system.cpu1.dtb.read_misses 11600 # DTB read misses -system.cpu1.dtb.read_acv 21 # DTB read access violations -system.cpu1.dtb.read_accesses 345698 # DTB read accesses -system.cpu1.dtb.write_hits 1317225 # DTB write hits -system.cpu1.dtb.write_misses 3094 # DTB write misses -system.cpu1.dtb.write_acv 53 # DTB write access violations -system.cpu1.dtb.write_accesses 138357 # DTB write accesses -system.cpu1.dtb.data_hits 3376223 # DTB hits -system.cpu1.dtb.data_misses 14694 # DTB misses -system.cpu1.dtb.data_acv 74 # DTB access violations -system.cpu1.dtb.data_accesses 484055 # DTB accesses -system.cpu1.itb.fetch_hits 573986 # ITB hits -system.cpu1.itb.fetch_misses 6844 # ITB misses -system.cpu1.itb.fetch_acv 105 # ITB acv -system.cpu1.itb.fetch_accesses 580830 # ITB accesses +system.cpu1.dtb.read_hits 2247369 # DTB read hits +system.cpu1.dtb.read_misses 13283 # DTB read misses +system.cpu1.dtb.read_acv 72 # DTB read access violations +system.cpu1.dtb.read_accesses 382556 # DTB read accesses +system.cpu1.dtb.write_hits 1356336 # DTB write hits +system.cpu1.dtb.write_misses 3091 # DTB write misses +system.cpu1.dtb.write_acv 71 # DTB write access violations +system.cpu1.dtb.write_accesses 152961 # DTB write accesses +system.cpu1.dtb.data_hits 3603705 # DTB hits +system.cpu1.dtb.data_misses 16374 # DTB misses +system.cpu1.dtb.data_acv 143 # DTB access violations +system.cpu1.dtb.data_accesses 535517 # DTB accesses +system.cpu1.itb.fetch_hits 615373 # ITB hits +system.cpu1.itb.fetch_misses 3011 # ITB misses +system.cpu1.itb.fetch_acv 117 # ITB acv +system.cpu1.itb.fetch_accesses 618384 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -953,568 +964,567 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16344557 # number of cpu cycles simulated +system.cpu1.numCycles 16726806 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6567420 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 14895137 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3770405 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1113467 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 8326976 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 284690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 333 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 274833 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 63331 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1681040 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 57489 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15400785 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.967167 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.371525 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6696452 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16370488 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4129053 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1187433 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 8741861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 347188 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 25893 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 58137 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 49356 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1820963 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 76422 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15745356 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.039703 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.449166 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12783684 83.01% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 166452 1.08% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 261215 1.70% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 200313 1.30% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 351067 2.28% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 133990 0.87% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 151147 0.98% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 199120 1.29% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1153797 7.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12876670 81.78% 81.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 185062 1.18% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 297924 1.89% 84.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 209767 1.33% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 372753 2.37% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 143050 0.91% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 159866 1.02% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 207293 1.32% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1292971 8.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15400785 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.230683 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.911321 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5395420 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7755332 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1888719 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 226049 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 135264 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 116204 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7167 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12211095 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22842 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 135264 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5551383 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 663921 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5888186 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1958901 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1203128 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11612321 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4312 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 84745 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 20732 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 660077 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 7621170 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13919150 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13857621 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 55424 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6464282 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1156880 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 465120 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 44099 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2006629 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2105779 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1396456 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 250989 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 150424 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 10250493 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 528025 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10010931 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 21465 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1679970 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 786543 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 387236 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15400785 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.650027 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.374650 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15745356 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.246852 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.978698 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5498623 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7777976 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2045729 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 256320 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 166707 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 143442 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7016 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 13354105 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22028 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 166707 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5670233 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 826473 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5769862 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2131801 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1180278 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12651091 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3750 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 88341 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 32960 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 615086 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 8374295 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 15046844 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 14984377 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 56291 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6609856 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1764431 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 476570 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 48769 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2080322 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2346654 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1454994 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 292964 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 152733 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11085695 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 541496 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10671183 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 25309 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2321405 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1075261 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 398456 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15745356 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.677735 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.406788 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11244282 73.01% 73.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1815288 11.79% 84.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 776099 5.04% 89.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 545502 3.54% 93.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 489702 3.18% 96.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 259974 1.69% 98.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 169251 1.10% 99.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 72741 0.47% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 27946 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11382155 72.29% 72.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1870956 11.88% 84.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 802175 5.09% 89.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 575742 3.66% 92.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 534921 3.40% 96.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 285738 1.81% 98.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 185455 1.18% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 78165 0.50% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 30049 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15400785 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15745356 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 26802 9.62% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 149738 53.73% 63.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 102168 36.66% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27488 9.05% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 170713 56.19% 65.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 105586 34.76% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3957 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6209301 62.03% 62.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16861 0.17% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11959 0.12% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1978 0.02% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2148593 21.46% 83.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1341864 13.40% 97.24% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 276418 2.76% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3991 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6611083 61.95% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16524 0.15% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 12068 0.11% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1990 0.02% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2360403 22.12% 84.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1384355 12.97% 97.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 280769 2.63% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10010931 # Type of FU issued -system.cpu1.iq.rate 0.612493 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 278708 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027840 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 35509985 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 12361464 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9636562 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 212834 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 101438 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 98868 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10172012 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 113670 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 100974 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10671183 # Type of FU issued +system.cpu1.iq.rate 0.637969 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 303787 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 37199457 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 13849868 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10195275 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 217360 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 103372 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 100900 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10854739 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 116240 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 112250 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 300733 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 901 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4546 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 138575 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 494389 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1075 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4794 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 168808 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 436 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 85477 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 442 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 89761 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 135264 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 341224 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 281245 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 11333478 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 30763 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2105779 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1396456 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 478482 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4958 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 275268 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4546 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 33466 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 102178 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 135644 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9885056 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2078095 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 125874 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 166707 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 440216 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 341566 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 12247032 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 53191 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2346654 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1454994 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 491166 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 5461 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 335179 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4794 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 42007 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 137108 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 179115 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10495256 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2269179 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 175926 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 554960 # number of nop insts executed -system.cpu1.iew.exec_refs 3404439 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1465257 # Number of branches executed -system.cpu1.iew.exec_stores 1326344 # Number of stores executed -system.cpu1.iew.exec_rate 0.604792 # Inst execution rate -system.cpu1.iew.wb_sent 9770196 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9735430 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4636977 # num instructions producing a value -system.cpu1.iew.wb_consumers 6583946 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.595637 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.704285 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1707241 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 140789 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 123833 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 15089302 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.633097 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.610231 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 619841 # number of nop insts executed +system.cpu1.iew.exec_refs 3634984 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1567515 # Number of branches executed +system.cpu1.iew.exec_stores 1365805 # Number of stores executed +system.cpu1.iew.exec_rate 0.627451 # Inst execution rate +system.cpu1.iew.wb_sent 10344393 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 10296175 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4904906 # num instructions producing a value +system.cpu1.iew.wb_consumers 6922372 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.615549 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708559 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2337439 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 143040 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 155210 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 15327667 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.637432 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.616488 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11642359 77.16% 77.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1582874 10.49% 87.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 578528 3.83% 91.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 347459 2.30% 93.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 270616 1.79% 95.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 111368 0.74% 96.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 102382 0.68% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 112638 0.75% 97.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 341078 2.26% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11807980 77.04% 77.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1622081 10.58% 87.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 578152 3.77% 91.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 357481 2.33% 93.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 274261 1.79% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 117588 0.77% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 104376 0.68% 96.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 117710 0.77% 97.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 348038 2.27% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 15089302 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9552993 # Number of instructions committed -system.cpu1.commit.committedOps 9552993 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 15327667 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9770342 # Number of instructions committed +system.cpu1.commit.committedOps 9770342 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3062927 # Number of memory references committed -system.cpu1.commit.loads 1805046 # Number of loads committed -system.cpu1.commit.membars 44912 # Number of memory barriers committed -system.cpu1.commit.branches 1363215 # Number of branches committed -system.cpu1.commit.fp_insts 97092 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8861525 # Number of committed integer instructions. -system.cpu1.commit.function_calls 149395 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 458406 4.80% 4.80% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5679268 59.45% 64.25% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16577 0.17% 64.42% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 11953 0.13% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1978 0.02% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.57% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1849958 19.37% 83.93% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1258435 13.17% 97.11% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 276418 2.89% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3138451 # Number of memory references committed +system.cpu1.commit.loads 1852265 # Number of loads committed +system.cpu1.commit.membars 45725 # Number of memory barriers committed +system.cpu1.commit.branches 1397481 # Number of branches committed +system.cpu1.commit.fp_insts 99132 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9064844 # Number of committed integer instructions. +system.cpu1.commit.function_calls 152839 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 468541 4.80% 4.80% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5805964 59.42% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16275 0.17% 64.39% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 12061 0.12% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1990 0.02% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1897990 19.43% 83.96% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1286752 13.17% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 280769 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 9552993 # Class of committed instruction -system.cpu1.commit.bw_lim_events 341078 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 25912274 # The number of ROB reads -system.cpu1.rob.rob_writes 22828201 # The number of ROB writes -system.cpu1.timesIdled 132318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 943772 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3831967714 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9098543 # Number of Instructions Simulated -system.cpu1.committedOps 9098543 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.796393 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.796393 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556671 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556671 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12770865 # number of integer regfile reads -system.cpu1.int_regfile_writes 6910748 # number of integer regfile writes -system.cpu1.fp_regfile_reads 54739 # number of floating regfile reads -system.cpu1.fp_regfile_writes 53934 # number of floating regfile writes -system.cpu1.misc_regfile_reads 528553 # number of misc regfile reads -system.cpu1.misc_regfile_writes 224621 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 116660 # number of replacements -system.cpu1.dcache.tags.tagsinuse 487.079416 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2668588 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 117172 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 22.774963 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048837209000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.079416 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951327 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.951327 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 9770342 # Class of committed instruction +system.cpu1.commit.bw_lim_events 348038 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 26989101 # The number of ROB reads +system.cpu1.rob.rob_writes 24630830 # The number of ROB writes +system.cpu1.timesIdled 131471 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 981450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3841428948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9305781 # Number of Instructions Simulated +system.cpu1.committedOps 9305781 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.797464 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.797464 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556339 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556339 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13488576 # number of integer regfile reads +system.cpu1.int_regfile_writes 7349661 # number of integer regfile writes +system.cpu1.fp_regfile_reads 55714 # number of floating regfile reads +system.cpu1.fp_regfile_writes 55051 # number of floating regfile writes +system.cpu1.misc_regfile_reads 538402 # number of misc regfile reads +system.cpu1.misc_regfile_writes 228232 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 120114 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.559727 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2854712 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 120626 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.665810 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 62007957000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.559727 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950312 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.950312 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12701896 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12701896 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1640446 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1640446 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 950506 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 950506 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 34609 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 34609 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32422 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 32422 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2590952 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2590952 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2590952 # number of overall hits -system.cpu1.dcache.overall_hits::total 2590952 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 211694 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 211694 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 265779 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 265779 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5362 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5362 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3043 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3043 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 477473 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 477473 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 477473 # number of overall misses -system.cpu1.dcache.overall_misses::total 477473 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2807776500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2807776500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12432535778 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12432535778 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 52442500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 52442500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 46465500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 46465500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15240312278 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15240312278 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15240312278 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15240312278 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1852140 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1852140 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1216285 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1216285 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39971 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 39971 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35465 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35465 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3068425 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3068425 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3068425 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3068425 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114297 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.114297 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218517 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.218517 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134147 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134147 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085803 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085803 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.155608 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.155608 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.155608 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.155608 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13263.373076 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13263.373076 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46777.720505 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 46777.720505 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9780.399105 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9780.399105 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15269.635228 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15269.635228 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31918.689178 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 31918.689178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31918.689178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 31918.689178 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 748281 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 2150 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 22290 # number of cycles access was blocked +system.cpu1.dcache.tags.tag_accesses 13510694 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 13510694 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1801260 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1801260 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 972413 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 972413 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 37246 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 37246 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 33039 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 33039 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2773673 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2773673 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2773673 # number of overall hits +system.cpu1.dcache.overall_hits::total 2773673 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 221542 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 221542 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 271468 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 271468 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5109 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5109 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3089 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3089 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 493010 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 493010 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 493010 # number of overall misses +system.cpu1.dcache.overall_misses::total 493010 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2936746000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2936746000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12570320655 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12570320655 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51167000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 51167000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47352500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 47352500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15507066655 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15507066655 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15507066655 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15507066655 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2022802 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2022802 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1243881 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1243881 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 42355 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 42355 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 36128 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 36128 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3266683 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3266683 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3266683 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3266683 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109522 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.109522 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218243 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.218243 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120623 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120623 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085502 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085502 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.150921 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.150921 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.150921 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.150921 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13255.933412 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13255.933412 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46304.981269 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46304.981269 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10015.071443 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10015.071443 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15329.394626 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15329.394626 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 31453.858248 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 759613 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1583 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 22564 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.570256 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 179.166667 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 77506 # number of writebacks -system.cpu1.dcache.writebacks::total 77506 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 130194 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 130194 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 220941 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 220941 # 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number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 126338 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 126338 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 126338 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 126338 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks +system.cpu1.dcache.writebacks::total 79554 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 136401 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 226329 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 226329 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 689 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 689 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 362730 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 362730 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 362730 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 362730 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 85141 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 85141 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45139 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 45139 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4420 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4420 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3085 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3085 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 130280 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 130280 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 130280 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 130280 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2978 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2978 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3140 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3140 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1028731500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1028731500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2065280441 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2065280441 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40973500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40973500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43423500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43423500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3094011941 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3094011941 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3094011941 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3094011941 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32188500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32188500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 693701000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 693701000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 725889500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 725889500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044003 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044003 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036865 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036865 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.118161 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.118161 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085775 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085775 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041174 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.041174 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041174 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.041174 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12622.472393 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12622.472393 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46060.940296 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46060.940296 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8675.312302 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8675.312302 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14274.654832 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14274.654832 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24489.955049 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24489.955049 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24489.955049 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24489.955049 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198694.444444 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198694.444444 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232941.907320 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232941.907320 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231175 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231175 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2990 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2990 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3152 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3152 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1075350000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1075350000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2078906462 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2078906462 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39137500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39137500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44267500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44267500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3154256462 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3154256462 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 696582500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 696582500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 728758500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 728758500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036289 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104356 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104356 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085391 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085391 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039881 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039881 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12630.225156 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12630.225156 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46055.660560 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46055.660560 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8854.638009 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8854.638009 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 236774 # number of replacements -system.cpu1.icache.tags.tagsinuse 467.367156 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1435165 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 237286 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.048250 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1897657857500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.367156 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912826 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.912826 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 244089 # number of replacements +system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 244601 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.398997 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1896682174500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 469.435893 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.916867 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.916867 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1918394 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1918394 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1435165 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1435165 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1435165 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1435165 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1435165 # number of overall hits -system.cpu1.icache.overall_hits::total 1435165 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 245875 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 245875 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 245875 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 245875 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 245875 # number of overall misses -system.cpu1.icache.overall_misses::total 245875 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3543557000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3543557000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3543557000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3543557000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3543557000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3543557000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1681040 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1681040 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1681040 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1681040 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1681040 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1681040 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146264 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.146264 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146264 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.146264 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146264 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.146264 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14412.026436 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14412.026436 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14412.026436 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14412.026436 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14412.026436 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14412.026436 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 967 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2065632 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2065632 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1565201 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1565201 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1565201 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1565201 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1565201 # number of overall hits +system.cpu1.icache.overall_hits::total 1565201 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 255762 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 255762 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 255762 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 255762 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 255762 # number of overall misses +system.cpu1.icache.overall_misses::total 255762 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3690348499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3690348499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3690348499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3690348499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3690348499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3690348499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1820963 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1820963 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1820963 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1820963 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1820963 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1820963 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.140454 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.140454 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.140454 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.140454 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.140454 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.140454 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14428.838135 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14428.838135 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14428.838135 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14428.838135 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 721 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 56 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.574468 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 236774 # number of writebacks -system.cpu1.icache.writebacks::total 236774 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8521 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8521 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8521 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8521 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8521 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8521 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 237354 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 237354 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 237354 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 237354 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 237354 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 237354 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3178535500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3178535500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3178535500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3178535500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3178535500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3178535500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.141195 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.141195 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.141195 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13391.539641 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13391.539641 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13391.539641 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks +system.cpu1.icache.writebacks::total 244089 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 11093 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 11093 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 11093 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 11093 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 11093 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244669 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 244669 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 244669 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 244669 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 244669 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 244669 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3289647499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3289647499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3289647499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3289647499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3289647499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3289647499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.134362 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.134362 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.134362 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1530,9 +1540,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7368 # Transaction distribution system.iobus.trans_dist::ReadResp 7368 # Transaction distribution -system.iobus.trans_dist::WriteReq 54623 # Transaction distribution -system.iobus.trans_dist::WriteResp 54623 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11936 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54647 # Transaction distribution +system.iobus.trans_dist::WriteResp 54647 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11984 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1541,11 +1551,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40528 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40576 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 124030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47936 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1554,43 +1564,43 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73938 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 74130 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12379500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735754 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12444500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 818500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 814000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 176000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14310000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14015000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5965001 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6047501 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 87000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215710405 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215709165 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27481000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.518954 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.551900 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1726981777000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.518954 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.032435 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.032435 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1726981964000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.551900 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.034494 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.034494 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1604,14 +1614,14 @@ system.iocache.demand_misses::tsunami.ide 175 # n system.iocache.demand_misses::total 175 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 175 # number of overall misses system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 23088383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 23088383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246547022 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5246547022 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 23088383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 23088383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 23088383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 23088383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22072883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22072883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22072883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22072883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1628,19 +1638,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 131933.617143 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 131933.617143 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126264.608731 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126264.608731 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 131933.617143 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131933.617143 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 131933.617143 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131933.617143 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126130.760000 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126130.760000 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 0 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1654,14 +1664,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 175 system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14338383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14338383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167138735 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3167138735 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 14338383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14338383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 14338383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14338383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13322883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13322883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13322883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13322883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1670,199 +1680,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81933.617143 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76221.090080 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76221.090080 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81933.617143 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81933.617143 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345132 # number of replacements -system.l2c.tags.tagsinuse 65190.773198 # Cycle average of tags in use -system.l2c.tags.total_refs 3987579 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410285 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.719047 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 11177481000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53112.873337 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5260.284322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6538.875697 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 210.626415 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 68.113427 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.810438 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.099775 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001039 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65153 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3005 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4362 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5957 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51615 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994156 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38355291 # Number of tag accesses -system.l2c.tags.data_accesses 38355291 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 819892 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 819892 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 858364 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 858364 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 165 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 273 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 438 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 47 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 77 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 148311 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 29871 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 178182 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 881771 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 235510 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1117281 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 728849 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 74394 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 803243 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 881771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 877160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 235510 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 104265 # number of demand (read+write) hits -system.l2c.demand_hits::total 2098706 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 881771 # number of overall hits -system.l2c.overall_hits::cpu0.data 877160 # number of overall hits -system.l2c.overall_hits::cpu1.inst 235510 # number of overall hits -system.l2c.overall_hits::cpu1.data 104265 # number of overall hits -system.l2c.overall_hits::total 2098706 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2745 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1129 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3874 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 421 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 438 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 859 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 112211 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9825 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122036 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13418 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1804 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15222 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 272977 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 837 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 273814 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 13418 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 385188 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1804 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10662 # number of demand (read+write) misses -system.l2c.demand_misses::total 411072 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13418 # number of overall misses -system.l2c.overall_misses::cpu0.data 385188 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1804 # number of overall misses -system.l2c.overall_misses::cpu1.data 10662 # number of overall misses -system.l2c.overall_misses::total 411072 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 2600000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 16721000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 19321000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2754000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 393500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3147500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 15556825000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1578015500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 17134840500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1793058000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 243367000 # 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number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 243367000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1696730000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 53176623500 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 819892 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 819892 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 858364 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 858364 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2910 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1402 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4312 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 468 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 468 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 936 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 260522 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 39696 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300218 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 895189 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 237314 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1132503 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1001826 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 75231 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1077057 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 895189 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1262348 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 237314 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 114927 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2509778 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 895189 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1262348 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 237314 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 114927 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2509778 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943299 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805278 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.898423 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.899573 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.935897 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.917735 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.430716 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.247506 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.406491 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014989 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007602 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013441 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.272479 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.011126 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.254224 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014989 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.305136 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007602 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.092772 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.163788 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014989 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.305136 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007602 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.092772 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.163788 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 947.176685 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14810.451727 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4987.351575 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6541.567696 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 898.401826 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3664.144354 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138639.037171 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 160612.264631 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 140408.080403 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133630.794455 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 134904.101996 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 133781.697543 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124137.357726 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141833.333333 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 124191.451131 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 133630.794455 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 128361.912884 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 134904.101996 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 159138.060401 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 129360.850411 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 133630.794455 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 128361.912884 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 134904.101996 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 159138.060401 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 129360.850411 # average overall miss latency +system.l2c.tags.replacements 345263 # number of replacements +system.l2c.tags.tagsinuse 65201.794559 # Cycle average of tags in use +system.l2c.tags.total_refs 4034348 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410346 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.831576 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11176866000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 52690.467957 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5287.969178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6933.387030 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 211.163837 # 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mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.889069 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.871486 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.941053 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.905447 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430500 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.247793 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.406018 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013234 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273040 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.011350 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254056 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.091192 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162109 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.091192 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162109 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68985.614165 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69017.410714 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68994.909945 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68584.101382 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68937.360179 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68763.337117 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128400.151934 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150408.600081 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130199.944711 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124669.270256 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114219.328490 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129172.475281 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114267.789098 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118316.948095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 148658.099843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119350.368973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118316.948095 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 148658.099843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119350.368973 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209222.514578 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186117.283951 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208702.140970 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215773.132113 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220851.672241 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216932.722413 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213085.375817 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219066.465736 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214014.614550 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7193 # Transaction distribution -system.membus.trans_dist::ReadResp 296309 # Transaction distribution -system.membus.trans_dist::WriteReq 13071 # Transaction distribution -system.membus.trans_dist::WriteResp 13071 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122859 # Transaction distribution -system.membus.trans_dist::CleanEvict 263080 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10389 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5858 # Transaction distribution +system.membus.trans_dist::ReadResp 297247 # Transaction distribution +system.membus.trans_dist::WriteReq 13095 # Transaction distribution +system.membus.trans_dist::WriteResp 13095 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122992 # Transaction distribution +system.membus.trans_dist::CleanEvict 263076 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10346 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5952 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 122048 # Transaction distribution -system.membus.trans_dist::ReadExResp 121637 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289192 # Transaction distribution -system.membus.trans_dist::BadAddressError 76 # Transaction distribution +system.membus.trans_dist::ReadExReq 121253 # Transaction distribution +system.membus.trans_dist::ReadExResp 120834 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 290100 # Transaction distribution +system.membus.trans_dist::BadAddressError 46 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40528 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181775 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1222455 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182230 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 92 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1222898 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1305892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73938 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31464576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31538514 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1306335 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 74130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31481536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31555666 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34196754 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 11972 # Total snoops (count) -system.membus.snoop_fanout::samples 875257 # Request fanout histogram +system.membus.pkt_size::total 34213906 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12142 # Total snoops (count) +system.membus.snoop_fanout::samples 875570 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 875257 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875570 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 875257 # Request fanout histogram -system.membus.reqLayer0.occupancy 36588499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875570 # Request fanout histogram +system.membus.reqLayer0.occupancy 36438999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1355446474 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1356482971 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 101000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2176763250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2177455750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 924363 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 936113 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 5062297 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2530952 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 339931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1332 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1264 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5114760 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2557108 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 345514 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1336 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2238586 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13071 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13071 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 942766 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1131462 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825685 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10428 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5935 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16363 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301553 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301553 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1132810 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1098675 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 76 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2266679 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13095 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13095 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 943643 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1155325 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 827144 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10512 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6044 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16556 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299688 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299688 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1156637 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1102911 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 46 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2685333 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3847367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 711442 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373868 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7618010 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114552128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128359012 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30341632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12338926 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 285591698 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 462928 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2998059 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.119755 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.324954 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2735017 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3843601 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 733385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 384537 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7696540 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116675136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128186756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31277824 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12692238 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288831954 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 463427 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3024601 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.120612 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.326035 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2639295 88.03% 88.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 358495 11.96% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 268 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2660134 87.95% 87.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 364147 12.04% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 303 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 17 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2998059 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4499211916 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3024601 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4550078915 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 295885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1344759827 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1369499398 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1928238108 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1926492121 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 358125739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 368355265 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 195506142 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 200907831 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2153,170 +2163,170 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6521 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 181676 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64229 40.40% 40.40% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.49% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1930 1.21% 41.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 188 0.12% 41.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92486 58.18% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158964 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63227 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 180918 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 63985 40.38% 40.38% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.47% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1935 1.22% 41.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 191 0.12% 41.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92196 58.19% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158438 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 62993 49.19% 49.19% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1930 1.50% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63039 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128515 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866746585000 97.03% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63847000 0.00% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 578525000 0.03% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 89345000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56353429000 2.93% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1923831731000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984400 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1935 1.51% 50.81% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 191 0.15% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 62802 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128052 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1871632607000 97.04% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 66355000 0.00% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 578065000 0.03% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 91849500 0.00% 97.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56349581000 2.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1928718457500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984496 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681606 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808453 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.65% 3.65% # number of syscalls executed -system.cpu0.kern.syscall::3 16 8.33% 11.98% # number of syscalls executed -system.cpu0.kern.syscall::4 4 2.08% 14.06% # number of syscalls executed -system.cpu0.kern.syscall::6 28 14.58% 28.65% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.52% 29.17% # number of syscalls executed -system.cpu0.kern.syscall::17 8 4.17% 33.33% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.65% 36.98% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.08% 39.06% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.52% 39.58% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.56% 41.15% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.12% 44.27% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.04% 45.31% # number of syscalls executed -system.cpu0.kern.syscall::45 31 16.15% 61.46% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.56% 63.02% # number of syscalls executed -system.cpu0.kern.syscall::48 8 4.17% 67.19% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.69% 71.88% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.52% 72.40% # number of syscalls executed -system.cpu0.kern.syscall::59 6 3.12% 75.52% # number of syscalls executed -system.cpu0.kern.syscall::71 21 10.94% 86.46% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.56% 88.02% # number of syscalls executed -system.cpu0.kern.syscall::74 5 2.60% 90.62% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.52% 91.15% # number of syscalls executed -system.cpu0.kern.syscall::90 2 1.04% 92.19% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.65% 95.83% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.04% 96.88% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.04% 97.92% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.52% 98.44% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.52% 98.96% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.04% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 192 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.681179 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808215 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.68% 3.68% # number of syscalls executed +system.cpu0.kern.syscall::3 15 7.89% 11.58% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.11% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 28 14.74% 28.42% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.53% 28.95% # number of syscalls executed +system.cpu0.kern.syscall::17 8 4.21% 33.16% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.68% 36.84% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.11% 38.95% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.53% 39.47% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.58% 41.05% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.16% 44.21% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.05% 45.26% # number of syscalls executed +system.cpu0.kern.syscall::45 31 16.32% 61.58% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.58% 63.16% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.21% 67.37% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.74% 72.11% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.53% 72.63% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.63% 75.26% # number of syscalls executed +system.cpu0.kern.syscall::71 21 11.05% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.58% 87.89% # number of syscalls executed +system.cpu0.kern.syscall::74 5 2.63% 90.53% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.53% 91.05% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.05% 92.11% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.68% 95.79% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.05% 96.84% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.05% 97.89% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.53% 98.42% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.53% 98.95% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.05% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 190 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 288 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3442 2.06% 2.23% # number of callpals executed -system.cpu0.kern.callpal::tbi 49 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 152297 91.02% 93.29% # number of callpals executed -system.cpu0.kern.callpal::rdps 6331 3.78% 97.07% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.07% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.07% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.08% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.08% # number of callpals executed -system.cpu0.kern.callpal::rti 4417 2.64% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 330 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167317 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6879 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1175 # number of protection mode switches +system.cpu0.kern.callpal::wripir 292 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3426 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151781 91.02% 93.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6336 3.80% 97.08% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.08% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.08% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.09% # number of callpals executed +system.cpu0.kern.callpal::rti 4399 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 318 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 166759 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6855 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1159 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1175 -system.cpu0.kern.mode_good::user 1175 +system.cpu0.kern.mode_good::kernel 1159 +system.cpu0.kern.mode_good::user 1159 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170810 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.169074 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.291780 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1921452590000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2041385500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.289244 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1925885387000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1988942000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3443 # number of times the context was actually changed +system.cpu0.kern.swap_context 3427 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2563 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 58062 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18132 36.97% 36.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 3.93% 40.90% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 288 0.59% 41.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28696 58.51% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49044 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17757 47.43% 47.43% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 5.15% 52.57% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 288 0.77% 53.34% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17469 46.66% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37442 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1877611262500 97.58% 97.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 563601000 0.03% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 141411000 0.01% 97.62% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45839038500 2.38% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1924155313000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979318 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2571 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58929 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18404 37.04% 37.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1933 3.89% 40.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 292 0.59% 41.51% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 29063 58.49% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49692 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 18019 47.45% 47.45% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1933 5.09% 52.55% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 292 0.77% 53.31% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17727 46.69% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37971 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1882485952500 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 565596500 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 145516500 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45879988500 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1929077054000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979081 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.608761 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.763437 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.75% 0.75% # number of syscalls executed -system.cpu1.kern.syscall::3 14 10.45% 11.19% # number of syscalls executed -system.cpu1.kern.syscall::6 14 10.45% 21.64% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.75% 22.39% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.22% 27.61% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.24% 29.85% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.49% 31.34% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.24% 33.58% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.24% 35.82% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.73% 39.55% # number of syscalls executed -system.cpu1.kern.syscall::45 23 17.16% 56.72% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.24% 58.96% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.49% 60.45% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.75% 61.19% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.75% 61.94% # number of syscalls executed -system.cpu1.kern.syscall::71 33 24.63% 86.57% # number of syscalls executed -system.cpu1.kern.syscall::74 11 8.21% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.75% 95.52% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.49% 97.01% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.24% 99.25% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.75% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 134 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.609951 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.764127 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.74% 0.74% # number of syscalls executed +system.cpu1.kern.syscall::3 15 11.03% 11.76% # number of syscalls executed +system.cpu1.kern.syscall::6 14 10.29% 22.06% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.74% 22.79% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.15% 27.94% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.21% 30.15% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.47% 31.62% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.21% 33.82% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.21% 36.03% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.68% 39.71% # number of syscalls executed +system.cpu1.kern.syscall::45 23 16.91% 56.62% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.21% 58.82% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.47% 60.29% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.74% 61.03% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.47% 62.50% # number of syscalls executed +system.cpu1.kern.syscall::71 33 24.26% 86.76% # number of syscalls executed +system.cpu1.kern.syscall::74 11 8.09% 94.85% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.74% 95.59% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.47% 97.06% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.21% 99.26% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.74% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 136 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wripir 191 0.37% 0.37% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1149 2.26% 2.64% # number of callpals executed -system.cpu1.kern.callpal::tbi 4 0.01% 2.64% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.66% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43675 85.89% 88.55% # number of callpals executed -system.cpu1.kern.callpal::rdps 2435 4.79% 93.34% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.34% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.35% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.35% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.35% # number of callpals executed -system.cpu1.kern.callpal::rti 3152 6.20% 99.55% # number of callpals executed -system.cpu1.kern.callpal::callsys 185 0.36% 99.92% # number of callpals executed -system.cpu1.kern.callpal::imb 41 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1171 2.27% 2.65% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 2.66% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed +system.cpu1.kern.callpal::swpipl 44279 85.92% 88.59% # number of callpals executed +system.cpu1.kern.callpal::rdps 2440 4.73% 93.33% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.33% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.34% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.34% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.34% # number of callpals executed +system.cpu1.kern.callpal::rti 3187 6.18% 99.53% # number of callpals executed +system.cpu1.kern.callpal::callsys 197 0.38% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 45 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 50850 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1515 # number of protection mode switches -system.cpu1.kern.mode_switch::user 561 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2424 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 773 -system.cpu1.kern.mode_good::user 561 -system.cpu1.kern.mode_good::idle 212 -system.cpu1.kern.mode_switch_good::kernel 0.510231 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 51536 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1550 # number of protection mode switches +system.cpu1.kern.mode_switch::user 578 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 794 +system.cpu1.kern.mode_good::user 578 +system.cpu1.kern.mode_good::idle 216 +system.cpu1.kern.mode_switch_good::kernel 0.512258 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.087459 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.343556 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4865757000 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 846470000 0.04% 0.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1918443078000 99.70% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1150 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.088670 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.347940 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4980780500 0.26% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 920793000 0.05% 0.31% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1923175472500 99.69% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1172 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 28bcd517c..6d0ef82f7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.875758 # Number of seconds simulated -sim_ticks 1875758115500 # Number of ticks simulated -final_tick 1875758115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.876794 # Number of seconds simulated +sim_ticks 1876794488000 # Number of ticks simulated +final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136821 # Simulator instruction rate (inst/s) -host_op_rate 136821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4844017901 # Simulator tick rate (ticks/s) -host_mem_usage 335520 # Number of bytes of host memory used -host_seconds 387.23 # Real time elapsed on the host -sim_insts 52981544 # Number of instructions simulated -sim_ops 52981544 # Number of ops (including micro ops) simulated +host_inst_rate 164316 # Simulator instruction rate (inst/s) +host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5820514836 # Simulator tick rate (ticks/s) +host_mem_usage 335448 # Number of bytes of host memory used +host_seconds 322.44 # Real time elapsed on the host +sim_insts 52982943 # Number of instructions simulated +sim_ops 52982943 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25840192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory -system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388766 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory +system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15027 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403753 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 510838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13264516 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403799 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117620 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117620 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 512431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13256885 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13775866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 510838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 510838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4011639 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4011639 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4011639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 510838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13264516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13769827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4010924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4010924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4010924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13256885 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403753 # Number of read requests accepted -system.physmem.writeReqs 117576 # Number of write requests accepted -system.physmem.readBursts 403753 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117576 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25832384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue -system.physmem.bytesWritten 7523392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25840192 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7524864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17780751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403799 # Number of read requests accepted +system.physmem.writeReqs 117620 # Number of write requests accepted +system.physmem.readBursts 403799 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117620 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25835776 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 7525824 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25843136 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7527680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25611 # Per bank write bursts -system.physmem.perBankRdBursts::1 25424 # Per bank write bursts -system.physmem.perBankRdBursts::2 25556 # Per bank write bursts -system.physmem.perBankRdBursts::3 25503 # Per bank write bursts -system.physmem.perBankRdBursts::4 25379 # Per bank write bursts -system.physmem.perBankRdBursts::5 24725 # Per bank write bursts -system.physmem.perBankRdBursts::6 24941 # Per bank write bursts -system.physmem.perBankRdBursts::7 25083 # Per bank write bursts -system.physmem.perBankRdBursts::8 24938 # Per bank write bursts -system.physmem.perBankRdBursts::9 25019 # Per bank write bursts -system.physmem.perBankRdBursts::10 25561 # Per bank write bursts -system.physmem.perBankRdBursts::11 24881 # Per bank write bursts -system.physmem.perBankRdBursts::12 24458 # Per bank write bursts -system.physmem.perBankRdBursts::13 25273 # Per bank write bursts -system.physmem.perBankRdBursts::14 25708 # Per bank write bursts -system.physmem.perBankRdBursts::15 25571 # Per bank write bursts -system.physmem.perBankWrBursts::0 7931 # Per bank write bursts -system.physmem.perBankWrBursts::1 7523 # Per bank write bursts -system.physmem.perBankWrBursts::2 7959 # Per bank write bursts -system.physmem.perBankWrBursts::3 7526 # Per bank write bursts -system.physmem.perBankWrBursts::4 7322 # Per bank write bursts -system.physmem.perBankWrBursts::5 6664 # Per bank write bursts -system.physmem.perBankWrBursts::6 6770 # Per bank write bursts -system.physmem.perBankWrBursts::7 6720 # Per bank write bursts -system.physmem.perBankWrBursts::8 7147 # Per bank write bursts -system.physmem.perBankWrBursts::9 6703 # Per bank write bursts -system.physmem.perBankWrBursts::10 7408 # Per bank write bursts -system.physmem.perBankWrBursts::11 6973 # Per bank write bursts -system.physmem.perBankWrBursts::12 7144 # Per bank write bursts -system.physmem.perBankWrBursts::13 7893 # Per bank write bursts -system.physmem.perBankWrBursts::14 8063 # Per bank write bursts -system.physmem.perBankWrBursts::15 7807 # Per bank write bursts +system.physmem.perBankRdBursts::0 25625 # Per bank write bursts +system.physmem.perBankRdBursts::1 25421 # Per bank write bursts +system.physmem.perBankRdBursts::2 25559 # Per bank write bursts +system.physmem.perBankRdBursts::3 25464 # Per bank write bursts +system.physmem.perBankRdBursts::4 25431 # Per bank write bursts +system.physmem.perBankRdBursts::5 24732 # Per bank write bursts +system.physmem.perBankRdBursts::6 24935 # Per bank write bursts +system.physmem.perBankRdBursts::7 25090 # Per bank write bursts +system.physmem.perBankRdBursts::8 24946 # Per bank write bursts +system.physmem.perBankRdBursts::9 25020 # Per bank write bursts +system.physmem.perBankRdBursts::10 25560 # Per bank write bursts +system.physmem.perBankRdBursts::11 24886 # Per bank write bursts +system.physmem.perBankRdBursts::12 24460 # Per bank write bursts +system.physmem.perBankRdBursts::13 25266 # Per bank write bursts +system.physmem.perBankRdBursts::14 25703 # Per bank write bursts +system.physmem.perBankRdBursts::15 25586 # Per bank write bursts +system.physmem.perBankWrBursts::0 7949 # Per bank write bursts +system.physmem.perBankWrBursts::1 7513 # Per bank write bursts +system.physmem.perBankWrBursts::2 7969 # Per bank write bursts +system.physmem.perBankWrBursts::3 7485 # Per bank write bursts +system.physmem.perBankWrBursts::4 7367 # Per bank write bursts +system.physmem.perBankWrBursts::5 6667 # Per bank write bursts +system.physmem.perBankWrBursts::6 6767 # Per bank write bursts +system.physmem.perBankWrBursts::7 6715 # Per bank write bursts +system.physmem.perBankWrBursts::8 7150 # Per bank write bursts +system.physmem.perBankWrBursts::9 6697 # Per bank write bursts +system.physmem.perBankWrBursts::10 7421 # Per bank write bursts +system.physmem.perBankWrBursts::11 6978 # Per bank write bursts +system.physmem.perBankWrBursts::12 7150 # Per bank write bursts +system.physmem.perBankWrBursts::13 7899 # Per bank write bursts +system.physmem.perBankWrBursts::14 8060 # Per bank write bursts +system.physmem.perBankWrBursts::15 7804 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 1875752798500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 1876789160500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403753 # Read request sizes (log2) +system.physmem.readPktSize::6 403799 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117576 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 35859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117620 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 35764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -148,190 +148,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62096 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 537.164648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.293750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 411.963299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13665 22.01% 22.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10559 17.00% 39.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4854 7.82% 46.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2778 4.47% 51.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2418 3.89% 55.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1622 2.61% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3711 5.98% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1214 1.96% 65.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21275 34.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62096 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.619423 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2241.505208 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5195 99.90% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5200 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5200 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.606346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.258970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.077519 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4603 88.52% 88.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 36 0.69% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 24 0.46% 89.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 35 0.67% 90.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 205 3.94% 94.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 11 0.21% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 15 0.29% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 35 0.67% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 175 3.37% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.12% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 7 0.13% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 2 0.04% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 11 0.21% 99.35% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::61 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.886657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.247155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 411.697741 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13677 22.01% 22.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10478 16.86% 38.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4968 7.99% 46.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2775 4.47% 51.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2441 3.93% 55.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1588 2.56% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3776 6.08% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1174 1.89% 65.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21262 34.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62139 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5217 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.374545 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2903.927058 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5214 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5217 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5217 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.539965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.244136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.635763 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4619 88.54% 88.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 29 0.56% 89.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 25 0.48% 89.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 38 0.73% 90.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 214 4.10% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 9 0.17% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.21% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 34 0.65% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 184 3.53% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.10% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.08% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.12% 99.35% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 6 0.12% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.08% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.13% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::344-351 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5200 # Writes before turning the bus around for reads -system.physmem.totQLat 4180311250 # Total ticks spent queuing -system.physmem.totMemAccLat 11748392500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018155000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10356.76 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.08% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 8 0.15% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.06% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 6 0.12% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5217 # Writes before turning the bus around for reads +system.physmem.totQLat 4201005000 # Total ticks spent queuing +system.physmem.totMemAccLat 11770080000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10406.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29106.76 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29156.67 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing -system.physmem.readRowHits 363824 # Number of row buffer hits during reads -system.physmem.writeRowHits 95264 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads +system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing +system.physmem.readRowHits 363845 # Number of row buffer hits during reads +system.physmem.writeRowHits 95291 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes -system.physmem.avgGap 3598021.21 # Average gap between requests -system.physmem.pageHitRate 88.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 232326360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126765375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577331600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378529200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61450630965 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1071548691000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1257829429860 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.572492 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1782417296500 # Time in different power states -system.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states +system.physmem.avgGap 3599387.75 # Average gap between requests +system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 233399880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127351125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577604600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378639360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61740410985 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1071915840750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1258556040540 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.589641 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1783024934000 # Time in different power states +system.physmem_0.memoryStateTime::REF 62670140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30701746000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31095099750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 237119400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129380625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1570990200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383214240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61460167635 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1071540333750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1257836361210 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.576183 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1782399409250 # Time in different power states -system.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states +system.physmem_1.actEnergy 236370960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128972250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571130600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383350320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61477234290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.573928 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states +system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30719647000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17926200 # Number of BP lookups -system.cpu.branchPred.condPredicted 15634549 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 367641 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11517888 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5853508 # Number of BTB hits +system.cpu.branchPred.lookups 19569408 # Number of BP lookups +system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.821019 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 912312 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21142 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42865 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6372302 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 563108 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5809194 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 264983 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10248777 # DTB read hits -system.cpu.dtb.read_misses 41124 # DTB read misses -system.cpu.dtb.read_acv 537 # DTB read access violations -system.cpu.dtb.read_accesses 965282 # DTB read accesses -system.cpu.dtb.write_hits 6643148 # DTB write hits -system.cpu.dtb.write_misses 9690 # DTB write misses -system.cpu.dtb.write_acv 398 # DTB write access violations -system.cpu.dtb.write_accesses 341994 # DTB write accesses -system.cpu.dtb.data_hits 16891925 # DTB hits -system.cpu.dtb.data_misses 50814 # DTB misses -system.cpu.dtb.data_acv 935 # DTB access violations -system.cpu.dtb.data_accesses 1307276 # DTB accesses -system.cpu.itb.fetch_hits 1767471 # ITB hits -system.cpu.itb.fetch_misses 28221 # ITB misses -system.cpu.itb.fetch_acv 656 # ITB acv -system.cpu.itb.fetch_accesses 1795692 # ITB accesses +system.cpu.dtb.read_hits 11131372 # DTB read hits +system.cpu.dtb.read_misses 49301 # DTB read misses +system.cpu.dtb.read_acv 623 # DTB read access violations +system.cpu.dtb.read_accesses 996761 # DTB read accesses +system.cpu.dtb.write_hits 6776847 # DTB write hits +system.cpu.dtb.write_misses 12217 # DTB write misses +system.cpu.dtb.write_acv 418 # DTB write access violations +system.cpu.dtb.write_accesses 345142 # DTB write accesses +system.cpu.dtb.data_hits 17908219 # DTB hits +system.cpu.dtb.data_misses 61518 # DTB misses +system.cpu.dtb.data_acv 1041 # DTB access violations +system.cpu.dtb.data_accesses 1341903 # DTB accesses +system.cpu.itb.fetch_hits 1817383 # ITB hits +system.cpu.itb.fetch_misses 10321 # ITB misses +system.cpu.itb.fetch_acv 767 # ITB acv +system.cpu.itb.fetch_accesses 1827704 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,252 +344,252 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 154296938 # number of cpu cycles simulated +system.cpu.numCycles 155167561 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29565992 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 77998562 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17926200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6765820 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115499750 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1227580 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1879 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1313604 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 470747 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 522 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8986717 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269982 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 147496190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.528817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.784795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1681668 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 87 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 29150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207083 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 421165 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 751 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9930605 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 406777 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 148422395 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.577690 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.864310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132977860 90.16% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 927689 0.63% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1955483 1.33% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 905427 0.61% 92.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2772003 1.88% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 615447 0.42% 95.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 725348 0.49% 95.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009173 0.68% 96.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5607760 3.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132578342 89.33% 89.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1033201 0.70% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2106811 1.42% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971505 0.65% 92.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2908700 1.96% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 663530 0.45% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 808471 0.54% 95.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1037122 0.70% 95.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6314713 4.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 147496190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116180 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.505509 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23986183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 111594322 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9434858 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1908489 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 572337 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 581608 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 41807 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68042420 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 132440 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 572337 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24909467 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78381394 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21682831 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10333745 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11616414 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65623799 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 205401 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2094519 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 225742 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7349306 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43739456 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79586592 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79405874 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168265 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38181154 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5558294 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1689229 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239421 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13564930 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10374266 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6952166 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1510457 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1094829 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58464384 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2137218 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57492092 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57307 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7620053 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3404147 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1476015 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 147496190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.389787 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.113704 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148422395 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126118 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.552578 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24118440 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 111208587 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10245196 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2044112 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 806059 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 738327 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 35573 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 74062953 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 114064 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 806059 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25129468 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 79314805 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20217508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11209636 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11744917 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 71031430 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 202187 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2134257 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 304114 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7385918 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47856784 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85577316 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85396639 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168224 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38182032 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9674744 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1729903 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 277398 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13945265 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11667584 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7222268 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1740236 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1128330 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62719117 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2208284 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60532785 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11944453 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5319004 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1547012 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148422395 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.407841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.141989 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 123903149 84.00% 84.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10174594 6.90% 90.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4283554 2.90% 93.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3020095 2.05% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3079434 2.09% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1494296 1.01% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1011464 0.69% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 404727 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124877 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 123871811 83.46% 83.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10428219 7.03% 90.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4419616 2.98% 93.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3188761 2.15% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3243069 2.19% 97.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1605515 1.08% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1096686 0.74% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 430660 0.29% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 138058 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 147496190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148422395 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210492 18.68% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 541350 48.03% 66.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375218 33.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206261 16.62% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 637065 51.34% 67.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 397617 32.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39049419 67.92% 67.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61870 0.11% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10658869 18.54% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6723409 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949053 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7280 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40910867 67.58% 67.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62087 0.10% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38559 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11677582 19.29% 87.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6883616 11.37% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949158 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57492092 # Type of FU issued -system.cpu.iq.rate 0.372607 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1127060 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019604 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262951820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67904206 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55848058 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712920 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336440 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329015 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58229078 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382791 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 635540 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60532785 # Type of FU issued +system.cpu.iq.rate 0.390112 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1240943 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020500 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 270086631 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76534291 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58304379 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 736956 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359180 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336827 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61370896 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 395552 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 686477 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1281314 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3324 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 573929 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2574541 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4210 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 22293 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 843973 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 459106 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18024 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 466103 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 572337 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74665457 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1160593 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64290812 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 139650 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10374266 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6952166 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1889682 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43932 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 913665 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 176905 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409384 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 586289 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56905925 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10317589 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586166 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 806059 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 75493298 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1202730 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68906340 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 204916 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11667584 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7222268 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1958885 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 46577 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 953145 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 22293 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 228745 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 630471 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 859216 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59676170 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11213777 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 856614 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3689210 # number of nop insts executed -system.cpu.iew.exec_refs 16985526 # number of memory reference insts executed -system.cpu.iew.exec_branches 8973539 # Number of branches executed -system.cpu.iew.exec_stores 6667937 # Number of stores executed -system.cpu.iew.exec_rate 0.368808 # Inst execution rate -system.cpu.iew.wb_sent 56314090 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56177073 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28757350 # num instructions producing a value -system.cpu.iew.wb_consumers 39943859 # num instructions consuming a value -system.cpu.iew.wb_rate 0.364084 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719944 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8001816 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661203 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537200 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146094021 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.384495 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.286335 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3978939 # number of nop insts executed +system.cpu.iew.exec_refs 18023142 # number of memory reference insts executed +system.cpu.iew.exec_branches 9384066 # Number of branches executed +system.cpu.iew.exec_stores 6809365 # Number of stores executed +system.cpu.iew.exec_rate 0.384592 # Inst execution rate +system.cpu.iew.wb_sent 58885265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58641206 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29760600 # num instructions producing a value +system.cpu.iew.wb_consumers 41260135 # num instructions consuming a value +system.cpu.iew.wb_rate 0.377922 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721292 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12542077 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661272 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 769434 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146251910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.384089 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.283290 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 126314306 86.46% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7853790 5.38% 91.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4274774 2.93% 94.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2236101 1.53% 96.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1744788 1.19% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615632 0.42% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 478334 0.33% 98.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 476966 0.33% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2099330 1.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 126403677 86.43% 86.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7969213 5.45% 91.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4187918 2.86% 94.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2256490 1.54% 96.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1756984 1.20% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 633259 0.43% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 482491 0.33% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 524954 0.36% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2036924 1.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146094021 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56172359 # Number of instructions committed -system.cpu.commit.committedOps 56172359 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146251910 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56173766 # Number of instructions committed +system.cpu.commit.committedOps 56173766 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471189 # Number of memory references committed -system.cpu.commit.loads 9092952 # Number of loads committed -system.cpu.commit.membars 226351 # Number of memory barriers committed -system.cpu.commit.branches 8440746 # Number of branches committed +system.cpu.commit.refs 15471338 # Number of memory references committed +system.cpu.commit.loads 9093043 # Number of loads committed +system.cpu.commit.membars 226379 # Number of memory barriers committed +system.cpu.commit.branches 8441154 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52021709 # Number of committed integer instructions. -system.cpu.commit.function_calls 740586 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198088 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36219325 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52023017 # Number of committed integer instructions. +system.cpu.commit.function_calls 740601 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198096 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36220454 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -617,423 +617,423 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319303 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384192 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949053 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9319422 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6384252 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949158 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56172359 # Class of committed instruction -system.cpu.commit.bw_lim_events 2099330 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 207919346 # The number of ROB reads -system.cpu.rob.rob_writes 129746181 # The number of ROB writes -system.cpu.timesIdled 581168 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6800748 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3597219294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52981544 # Number of Instructions Simulated -system.cpu.committedOps 52981544 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.912277 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.912277 # CPI: Total CPI of All Threads -system.cpu.ipc 0.343374 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.343374 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74565581 # number of integer regfile reads -system.cpu.int_regfile_writes 40526554 # number of integer regfile writes -system.cpu.fp_regfile_reads 167056 # number of floating regfile reads -system.cpu.fp_regfile_writes 167536 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985625 # number of misc regfile reads -system.cpu.misc_regfile_writes 939435 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1401792 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11831016 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1402304 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.436841 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 56173766 # Class of committed instruction +system.cpu.commit.bw_lim_events 2036924 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 212681294 # The number of ROB reads +system.cpu.rob.rob_writes 139606986 # The number of ROB writes +system.cpu.timesIdled 557347 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6745166 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598421416 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52982943 # Number of Instructions Simulated +system.cpu.committedOps 52982943 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.928632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.928632 # CPI: Total CPI of All Threads +system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77864960 # number of integer regfile reads +system.cpu.int_regfile_writes 42584488 # number of integer regfile writes +system.cpu.fp_regfile_reads 166613 # number of floating regfile reads +system.cpu.fp_regfile_writes 175794 # number of floating regfile writes +system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads +system.cpu.misc_regfile_writes 939529 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1405900 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63836509 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63836509 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7238578 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7238578 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4190111 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4190111 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186204 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186204 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215724 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215724 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11428689 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11428689 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11428689 # number of overall hits -system.cpu.dcache.overall_hits::total 11428689 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1796989 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1796989 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1957670 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1957670 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23246 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23246 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3754659 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3754659 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3754659 # number of overall misses -system.cpu.dcache.overall_misses::total 3754659 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57191537500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57191537500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116815247150 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116815247150 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 448333000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 448333000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 872000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 872000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 174006784650 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 174006784650 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 174006784650 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 174006784650 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9035567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9035567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147781 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147781 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209450 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209450 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215753 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215753 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15183348 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15183348 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15183348 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15183348 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198879 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198879 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318435 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318435 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110986 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.110986 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247288 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247288 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247288 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247288 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31826.314741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31826.314741 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59670.550782 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59670.550782 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19286.457885 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19286.457885 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30068.965517 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30068.965517 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46344.231167 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46344.231167 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7151643 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5595 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133832 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437466 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 199.821429 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319827 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319827 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098410 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098410 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000445 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000445 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.236730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.236730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.236730 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.236730 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46109.302994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46109.302994 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7149027 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5119 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133846 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841120 # number of writebacks -system.cpu.dcache.writebacks::total 841120 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703166 # 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number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290679 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18012 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18012 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384502 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384502 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384502 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384502 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks +system.cpu.dcache.writebacks::total 843569 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # 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number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44561431000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 44561431000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18441083775 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18441083775 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229476500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229476500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 843000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 843000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63002514775 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63002514775 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63002514775 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63002514775 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528979500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528979500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154218500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154218500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683198000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683198000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121057 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121057 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047282 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047282 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085997 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085997 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091186 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091186 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40739.160723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40739.160723 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63441.403662 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63441.403662 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12740.200977 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12740.200977 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29068.965517 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29068.965517 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220631.962482 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220631.962482 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224444.519692 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224444.519692 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222845.958374 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222845.958374 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44732838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 44732838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18336828964 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18336828964 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214607500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214607500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1779000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1779000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63069666964 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63069666964 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63069666964 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63069666964 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528639000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528639000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154562000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154562000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683201000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683201000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111881 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111881 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047061 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047061 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071461 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071461 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000445 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000445 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.086948 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.086948 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1035081 # number of replacements -system.cpu.icache.tags.tagsinuse 507.835100 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7897485 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1035589 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.626080 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.835100 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.991865 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1074186 # number of replacements +system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10022677 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10022677 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7897486 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7897486 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7897486 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7897486 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7897486 # number of overall hits -system.cpu.icache.overall_hits::total 7897486 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1089229 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1089229 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1089229 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1089229 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1089229 # number of overall misses -system.cpu.icache.overall_misses::total 1089229 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16358882985 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16358882985 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16358882985 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16358882985 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16358882985 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16358882985 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8986715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8986715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8986715 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8986715 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8986715 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8986715 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121204 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121204 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121204 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121204 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121204 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121204 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.772898 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15018.772898 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.772898 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15018.772898 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.772898 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15018.772898 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 10400 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits +system.cpu.icache.overall_hits::total 8786985 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1143615 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1143615 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1143615 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1143615 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1143615 # number of overall misses +system.cpu.icache.overall_misses::total 1143615 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17001547978 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17001547978 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17001547978 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17001547978 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17001547978 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17001547978 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9930600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9930600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9930600 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9930600 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9930600 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9930600 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115161 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.115161 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.115161 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.115161 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.115161 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.115161 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14866.496136 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14866.496136 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 12933 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 342 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.766234 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.815789 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1035081 # number of writebacks -system.cpu.icache.writebacks::total 1035081 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53267 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53267 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53267 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035962 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1035962 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1035962 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1035962 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1035962 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1035962 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14427899492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14427899492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14427899492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14427899492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14427899492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14427899492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115277 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115277 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115277 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13927.054749 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13927.054749 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13927.054749 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13927.054749 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13927.054749 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13927.054749 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1074186 # number of writebacks +system.cpu.icache.writebacks::total 1074186 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68615 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68615 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68615 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68615 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68615 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68615 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075000 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1075000 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1075000 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1075000 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1075000 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1075000 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14900351984 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14900351984 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14900351984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14900351984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14900351984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14900351984 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108251 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108251 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338544 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65279.658287 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4165713 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403711 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.318552 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 9186443000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53291.619090 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5239.581641 # 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Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39690670 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39690670 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 841120 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 841120 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1034540 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1034540 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185946 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185946 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1042,144 +1042,138 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76064 # number of writebacks -system.cpu.l2cache.writebacks::total 76064 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 101 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 101 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115508 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115508 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 14973 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 14973 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273861 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273861 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 14973 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389369 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404342 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 14973 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389369 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404342 # number of overall MSHR misses +system.cpu.l2cache.writebacks::writebacks 76108 # number of writebacks +system.cpu.l2cache.writebacks::total 76108 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 45 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 45 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114791 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 114791 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15028 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15028 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274518 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274518 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15028 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389309 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404337 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15028 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389309 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404337 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6981000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6981000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 479500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 479500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14949871007 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14949871007 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1865086000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1865086000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31278266000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31278266000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1865086000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46228137007 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 48093223007 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1865086000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46228137007 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 48093223007 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043799500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043799500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486079500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486079500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.776923 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.776923 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.241379 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.241379 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383170 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383170 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014458 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248754 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248754 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165848 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165848 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69118.811881 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69118.811881 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129427.147964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129427.147964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124563.280572 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124563.280572 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114212.195238 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114212.195238 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208121.212121 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208121.212121 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212940.143780 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212940.143780 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210919.621249 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210919.621249 # average overall mshr uncacheable latency +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3100000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3100000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 546000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 546000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14869460001 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14869460001 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1874795000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1874795000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31368563001 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31368563001 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1874795000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46238023002 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 48112818002 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1874795000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46238023002 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 48112818002 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442000500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442000500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2044145000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2044145000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486145500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486145500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.562500 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.562500 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.083333 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382857 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382857 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013984 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248067 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248067 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276801 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.162968 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276801 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.162968 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68888.888889 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68888.888889 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129535.068089 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129535.068089 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124753.460208 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124753.460208 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114267.782080 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114267.782080 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4875380 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2437337 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2172 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2143899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 958701 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1035081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 823325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 96 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 299827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 299827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7346784 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132526592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143633332 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 276159924 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422430 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2876994 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001301 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.036051 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3223811 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252378 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7476189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137523904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144052988 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 281576892 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422541 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2920171 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001264 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.035530 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2873250 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3744 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2916480 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3691 0.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2876994 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4326954000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2920171 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4411678000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1555197985 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613546403 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2115406799 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121618679 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1195,9 +1189,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51150 # Transaction distribution -system.iobus.trans_dist::WriteResp 51150 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51151 # Transaction distribution +system.iobus.trans_dist::WriteResp 51151 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1206,11 +1200,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1219,43 +1213,43 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5356500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5364000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 825500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14331000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14181000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5952500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6052000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215698160 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.249420 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1725995722000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.249420 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1269,14 +1263,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245293777 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5245293777 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21806383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21828883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21828883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21828883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21828883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1293,19 +1287,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126234.447848 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126234.447848 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126178.514451 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126178.514451 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1319,14 +1313,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165897973 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165897973 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13156383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13178883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13178883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13178883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13178883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1335,63 +1329,63 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.229616 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.229616 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295856 # Transaction distribution -system.membus.trans_dist::WriteReq 9598 # Transaction distribution -system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117576 # Transaction distribution -system.membus.trans_dist::CleanEvict 261861 # Transaction distribution -system.membus.trans_dist::UpgradeReq 350 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.membus.trans_dist::ReadResp 296606 # Transaction distribution +system.membus.trans_dist::WriteReq 9599 # Transaction distribution +system.membus.trans_dist::WriteResp 9599 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution +system.membus.trans_dist::CleanEvict 261864 # Transaction distribution +system.membus.trans_dist::UpgradeReq 278 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 115259 # Transaction distribution -system.membus.trans_dist::ReadExResp 115259 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289007 # Transaction distribution -system.membus.trans_dist::BadAddressError 81 # Transaction distribution +system.membus.trans_dist::ReadExReq 114558 # Transaction distribution +system.membus.trans_dist::ReadExResp 114558 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289719 # Transaction distribution +system.membus.trans_dist::BadAddressError 43 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145859 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145930 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 86 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179074 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262502 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1262499 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30713088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757244 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33409204 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842145 # Request fanout histogram +system.membus.pkt_size::total 33414972 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 438 # Total snoops (count) +system.membus.snoop_fanout::samples 842137 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842145 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842137 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842145 # Request fanout histogram -system.membus.reqLayer0.occupancy 28932500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842137 # Request fanout histogram +system.membus.reqLayer0.occupancy 28883000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314336715 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 105000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2138304000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 911117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1425,28 +1419,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211012 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105568 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105584 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182266 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818034033000 96.92% 96.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64890000 0.00% 96.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561380500 0.03% 96.96% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57096986000 3.04% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1875757289500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818987792000 96.92% 96.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67503500 0.00% 96.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 563118000 0.03% 96.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57175249500 3.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1876793663000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694311 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815422 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694262 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815391 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1485,29 +1479,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175126 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175147 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191971 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191994 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5854 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326273 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29989573500 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2896538000 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1842871170000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 30164955000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2918722500 0.16% 1.76% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1843709977500 98.24% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 1e558125c..864d8545a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.843590 # Number of seconds simulated -sim_ticks 1843589966000 # Number of ticks simulated -final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.843617 # Number of seconds simulated +sim_ticks 1843616607000 # Number of ticks simulated +final_tick 1843616607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235004 # Simulator instruction rate (inst/s) -host_op_rate 235004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6029262323 # Simulator tick rate (ticks/s) -host_mem_usage 334496 # Number of bytes of host memory used -host_seconds 305.77 # Real time elapsed on the host -sim_insts 71858166 # Number of instructions simulated -sim_ops 71858166 # Number of ops (including micro ops) simulated +host_inst_rate 222443 # Simulator instruction rate (inst/s) +host_op_rate 222443 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5619525357 # Simulator tick rate (ticks/s) +host_mem_usage 335188 # Number of bytes of host memory used +host_seconds 328.07 # Real time elapsed on the host +sim_insts 72977545 # Number of instructions simulated +sim_ops 72977545 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 498752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20812864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 142016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1542464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 270784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2513408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 493824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20821760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 146560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1538304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 275200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2511424 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25781248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 498752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 142016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 270784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 911552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7470272 # Number of bytes written to this memory -system.physmem.bytes_written::total 7470272 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 325201 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24101 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25788032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 493824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 146560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 275200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 915584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7477248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7477248 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7716 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 325340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4300 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39241 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402832 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116723 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116723 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 270533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 11289313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 836663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 146879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1363323 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402938 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116832 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116832 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 267856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 11293975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 834395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 149272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1362227 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13984264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 270533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 146879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 494444 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4052025 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052025 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4052025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 270533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 11289313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 836663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 146879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1363323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13987741 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 267856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79496 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 149272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 496624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4055750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4055750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4055750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 267856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 11293975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 834395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 149272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1362227 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18036288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 69838 # Number of read requests accepted -system.physmem.writeReqs 43200 # Number of write requests accepted -system.physmem.readBursts 69838 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 43200 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 4468672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue -system.physmem.bytesWritten 2763328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 4469632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2764800 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 18043491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 69882 # Number of read requests accepted +system.physmem.writeReqs 42058 # Number of write requests accepted +system.physmem.readBursts 69882 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 42058 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 4471360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue +system.physmem.bytesWritten 2689856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 4472448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2691712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4348 # Per bank write bursts -system.physmem.perBankRdBursts::1 4129 # Per bank write bursts -system.physmem.perBankRdBursts::2 4337 # Per bank write bursts -system.physmem.perBankRdBursts::3 4598 # Per bank write bursts +system.physmem.perBankRdBursts::0 4380 # Per bank write bursts +system.physmem.perBankRdBursts::1 4144 # Per bank write bursts +system.physmem.perBankRdBursts::2 4349 # Per bank write bursts +system.physmem.perBankRdBursts::3 4638 # Per bank write bursts system.physmem.perBankRdBursts::4 3888 # Per bank write bursts -system.physmem.perBankRdBursts::5 4661 # Per bank write bursts -system.physmem.perBankRdBursts::6 4235 # Per bank write bursts -system.physmem.perBankRdBursts::7 4148 # Per bank write bursts -system.physmem.perBankRdBursts::8 4712 # Per bank write bursts -system.physmem.perBankRdBursts::9 4417 # Per bank write bursts -system.physmem.perBankRdBursts::10 4595 # Per bank write bursts -system.physmem.perBankRdBursts::11 4084 # Per bank write bursts -system.physmem.perBankRdBursts::12 4058 # Per bank write bursts -system.physmem.perBankRdBursts::13 4570 # Per bank write bursts -system.physmem.perBankRdBursts::14 4705 # Per bank write bursts -system.physmem.perBankRdBursts::15 4338 # Per bank write bursts -system.physmem.perBankWrBursts::0 2799 # Per bank write bursts -system.physmem.perBankWrBursts::1 2436 # Per bank write bursts -system.physmem.perBankWrBursts::2 2792 # Per bank write bursts -system.physmem.perBankWrBursts::3 3104 # Per bank write bursts -system.physmem.perBankWrBursts::4 2401 # Per bank write bursts -system.physmem.perBankWrBursts::5 2782 # Per bank write bursts -system.physmem.perBankWrBursts::6 2480 # Per bank write bursts -system.physmem.perBankWrBursts::7 2289 # Per bank write bursts -system.physmem.perBankWrBursts::8 3134 # Per bank write bursts -system.physmem.perBankWrBursts::9 2510 # Per bank write bursts -system.physmem.perBankWrBursts::10 2861 # Per bank write bursts -system.physmem.perBankWrBursts::11 2441 # Per bank write bursts -system.physmem.perBankWrBursts::12 2439 # Per bank write bursts -system.physmem.perBankWrBursts::13 2831 # Per bank write bursts -system.physmem.perBankWrBursts::14 3033 # Per bank write bursts -system.physmem.perBankWrBursts::15 2845 # Per bank write bursts +system.physmem.perBankRdBursts::5 4647 # Per bank write bursts +system.physmem.perBankRdBursts::6 4275 # Per bank write bursts +system.physmem.perBankRdBursts::7 4272 # Per bank write bursts +system.physmem.perBankRdBursts::8 4610 # Per bank write bursts +system.physmem.perBankRdBursts::9 4314 # Per bank write bursts +system.physmem.perBankRdBursts::10 4557 # Per bank write bursts +system.physmem.perBankRdBursts::11 4086 # Per bank write bursts +system.physmem.perBankRdBursts::12 4064 # Per bank write bursts +system.physmem.perBankRdBursts::13 4584 # Per bank write bursts +system.physmem.perBankRdBursts::14 4708 # Per bank write bursts +system.physmem.perBankRdBursts::15 4349 # Per bank write bursts +system.physmem.perBankWrBursts::0 2696 # Per bank write bursts +system.physmem.perBankWrBursts::1 2323 # Per bank write bursts +system.physmem.perBankWrBursts::2 2672 # Per bank write bursts +system.physmem.perBankWrBursts::3 3008 # Per bank write bursts +system.physmem.perBankWrBursts::4 2271 # Per bank write bursts +system.physmem.perBankWrBursts::5 2656 # Per bank write bursts +system.physmem.perBankWrBursts::6 2498 # Per bank write bursts +system.physmem.perBankWrBursts::7 2402 # Per bank write bursts +system.physmem.perBankWrBursts::8 3013 # Per bank write bursts +system.physmem.perBankWrBursts::9 2448 # Per bank write bursts +system.physmem.perBankWrBursts::10 2834 # Per bank write bursts +system.physmem.perBankWrBursts::11 2439 # Per bank write bursts +system.physmem.perBankWrBursts::12 2426 # Per bank write bursts +system.physmem.perBankWrBursts::13 2711 # Per bank write bursts +system.physmem.perBankWrBursts::14 2911 # Per bank write bursts +system.physmem.perBankWrBursts::15 2721 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 1842577981000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 1842604622000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 69838 # Read request sizes (log2) +system.physmem.readPktSize::6 69882 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 43200 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 42058 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,192 +153,188 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 37 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 1943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.141427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 203.044984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 371.054922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7137 35.54% 35.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4621 23.01% 58.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1666 8.30% 66.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 928 4.62% 71.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 708 3.53% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 489 2.44% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 446 2.22% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 393 1.96% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3693 18.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20081 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1852 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.694924 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 845.707136 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 1850 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20044 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 357.274795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.112689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 369.610579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7222 36.03% 36.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4570 22.80% 58.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1644 8.20% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 908 4.53% 71.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 718 3.58% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 515 2.57% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 476 2.37% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 378 1.89% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3613 18.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20044 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1835 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 38.063215 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 849.708875 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1833 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1852 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.313715 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.866365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.527044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 41 2.21% 2.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 7 0.38% 2.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 1554 83.91% 86.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 22 1.19% 87.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 8 0.43% 88.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 17 0.92% 89.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 85 4.59% 93.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 1 0.05% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 5 0.27% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 12 0.65% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 79 4.27% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 1 0.05% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 1 0.05% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 2 0.11% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.11% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 1 0.05% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 1 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.22% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1852 # Writes before turning the bus around for reads -system.physmem.totQLat 868841000 # Total ticks spent queuing -system.physmem.totMemAccLat 2178022250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 349115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12443.48 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 1835 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1835 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.904087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.705845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.745243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 40 2.18% 2.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 6 0.33% 2.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 1558 84.90% 87.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 20 1.09% 88.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 5 0.27% 88.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 16 0.87% 89.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 75 4.09% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.33% 94.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 1 0.05% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 15 0.82% 94.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 72 3.92% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.16% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 2 0.11% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.05% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.27% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.11% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.11% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.11% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1835 # Writes before turning the bus around for reads +system.physmem.totQLat 876234250 # Total ticks spent queuing +system.physmem.totMemAccLat 2186203000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 349325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12541.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31193.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31291.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.02 # Average write queue length when enqueuing -system.physmem.readRowHits 58950 # Number of row buffer hits during reads -system.physmem.writeRowHits 33969 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.63 # Row buffer hit rate for writes -system.physmem.avgGap 16300518.24 # Average gap between requests -system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75327840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 41027250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 267883200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 136617840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36136650240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 799618982250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 925467232860 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.951944 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1310356278000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45598540000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing +system.physmem.readRowHits 58965 # Number of row buffer hits during reads +system.physmem.writeRowHits 32885 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.19 # Row buffer hit rate for writes +system.physmem.avgGap 16460645.18 # Average gap between requests +system.physmem.pageHitRate 82.07 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75547080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 41146875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 269825400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 133008480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89192778480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 36154606095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 800813931750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 926680844160 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.855224 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1310352812250 # Time in different power states +system.physmem_0.memoryStateTime::REF 45599580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9770912000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9807496500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 76484520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41621250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 276736200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 143169120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35633622105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799038075000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 924400452435 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.003354 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1311078051250 # Time in different power states -system.physmem_1.memoryStateTime::REF 45598540000 # Time in different power states +system.physmem_1.actEnergy 75985560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41344875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 275121600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 139339440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89192778480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35610008715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799074942000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 924409520670 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.996911 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1311143061750 # Time in different power states +system.physmem_1.memoryStateTime::REF 45599580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9034735750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9002444500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4864866 # DTB read hits -system.cpu0.dtb.read_misses 6190 # DTB read misses +system.cpu0.dtb.read_hits 4891655 # DTB read hits +system.cpu0.dtb.read_misses 6160 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 429298 # DTB read accesses -system.cpu0.dtb.write_hits 3435008 # DTB write hits -system.cpu0.dtb.write_misses 688 # DTB write misses +system.cpu0.dtb.read_accesses 428724 # DTB read accesses +system.cpu0.dtb.write_hits 3459344 # DTB write hits +system.cpu0.dtb.write_misses 685 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 165213 # DTB write accesses -system.cpu0.dtb.data_hits 8299874 # DTB hits -system.cpu0.dtb.data_misses 6878 # DTB misses +system.cpu0.dtb.write_accesses 165214 # DTB write accesses +system.cpu0.dtb.data_hits 8350999 # DTB hits +system.cpu0.dtb.data_misses 6845 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 594511 # DTB accesses -system.cpu0.itb.fetch_hits 2740787 # ITB hits -system.cpu0.itb.fetch_misses 3088 # ITB misses +system.cpu0.dtb.data_accesses 593938 # DTB accesses +system.cpu0.itb.fetch_hits 2745673 # ITB hits +system.cpu0.itb.fetch_misses 3063 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2743875 # ITB accesses +system.cpu0.itb.fetch_accesses 2748736 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,32 +347,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928566651 # number of cpu cycles simulated +system.cpu0.numCycles 928907955 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211440 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211433 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105704 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182590 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1820420490500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39420000 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 369089000 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22760232500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1843589232000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1820384307000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39982500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 369735500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22821848000 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1843615873000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694732 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815789 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -415,7 +411,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175329 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -424,7 +420,7 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192243 # number of callpals executed +system.cpu0.kern.callpal::total 192244 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches @@ -435,488 +431,488 @@ system.cpu0.kern.mode_switch_good::kernel 0.322243 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29995203000 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2591439000 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1811002588000 98.23% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 30037472000 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2599704500 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810978694500 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.committedInsts 32582067 # Number of instructions committed -system.cpu0.committedOps 32582067 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30467910 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 163902 # Number of float alu accesses -system.cpu0.num_func_calls 798062 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4326152 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30467910 # number of integer instructions -system.cpu0.num_fp_insts 163902 # number of float instructions -system.cpu0.num_int_register_reads 42599897 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22343200 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84869 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86282 # number of times the floating registers were written -system.cpu0.num_mem_refs 8329687 # number of memory refs -system.cpu0.num_load_insts 4886082 # Number of load instructions -system.cpu0.num_store_insts 3443605 # Number of store instructions -system.cpu0.num_idle_cycles 904742998.451047 # Number of idle cycles -system.cpu0.num_busy_cycles 23823652.548953 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025656 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974344 # Percentage of idle cycles -system.cpu0.Branches 5381713 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1604740 4.92% 4.92% # Class of executed instruction -system.cpu0.op_class::IntAlu 21953705 67.37% 72.29% # Class of executed instruction -system.cpu0.op_class::IntMult 32143 0.10% 72.39% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.39% # Class of executed instruction -system.cpu0.op_class::FloatAdd 13006 0.04% 72.43% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1630 0.01% 72.43% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::MemRead 5016904 15.39% 87.83% # Class of executed instruction -system.cpu0.op_class::MemWrite 3446714 10.58% 98.40% # Class of executed instruction -system.cpu0.op_class::IprAccess 520313 1.60% 100.00% # Class of executed instruction +system.cpu0.committedInsts 33609672 # Number of instructions committed +system.cpu0.committedOps 33609672 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31482741 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 165750 # Number of float alu accesses +system.cpu0.num_func_calls 801937 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4632385 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31482741 # number of integer instructions +system.cpu0.num_fp_insts 165750 # number of float instructions +system.cpu0.num_int_register_reads 44252512 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23025410 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85784 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 87202 # number of times the floating registers were written +system.cpu0.num_mem_refs 8380910 # number of memory refs +system.cpu0.num_load_insts 4912915 # Number of load instructions +system.cpu0.num_store_insts 3467995 # Number of store instructions +system.cpu0.num_idle_cycles 904803576.609886 # Number of idle cycles +system.cpu0.num_busy_cycles 24104378.390114 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025949 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974051 # Percentage of idle cycles +system.cpu0.Branches 5693464 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1614345 4.80% 4.80% # Class of executed instruction +system.cpu0.op_class::IntAlu 22916205 68.17% 72.97% # Class of executed instruction +system.cpu0.op_class::IntMult 32373 0.10% 73.07% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 73.07% # Class of executed instruction +system.cpu0.op_class::FloatAdd 13074 0.04% 73.11% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1630 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 73.11% # Class of executed instruction +system.cpu0.op_class::MemRead 5044574 15.01% 88.12% # Class of executed instruction +system.cpu0.op_class::MemWrite 3471125 10.33% 98.44% # Class of executed instruction +system.cpu0.op_class::IprAccess 523401 1.56% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 32589155 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1393265 # number of replacements +system.cpu0.op_class::total 33616727 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1394181 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13241654 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393777 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.500554 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13501786 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1394693 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.680830 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.747103 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216699 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034010 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497553 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236751 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265691 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.971999 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 119.140649 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.885165 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499945 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.232697 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.267354 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63386315 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63386315 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4025113 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1019893 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2537393 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7582399 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3145683 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 772678 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357185 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5275546 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114073 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19050 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51175 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184298 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122917 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21014 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55400 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199331 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7170796 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1792571 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3894578 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12857945 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7170796 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1792571 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3894578 # number of overall hits -system.cpu0.dcache.overall_hits::total 12857945 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 726690 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 86811 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 548555 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1362056 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 165054 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 38389 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 671866 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 875309 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9398 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2090 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7703 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19191 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 891744 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 125200 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1220421 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2237365 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 891744 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 125200 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1220421 # number of overall misses -system.cpu0.dcache.overall_misses::total 2237365 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2310208500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8890735000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11200943500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2130423000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29514538622 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 31644961622 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27861500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 150253000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 178114500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 108000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 108000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4440631500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 38405273622 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42845905122 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4440631500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 38405273622 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42845905122 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4751803 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1106704 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3085948 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8944455 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3310737 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 811067 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2029051 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6150855 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123471 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21140 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58878 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203489 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122918 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21014 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55403 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199335 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8062540 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1917771 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5114999 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15095310 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8062540 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1917771 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5114999 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15095310 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.152929 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.078441 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.177759 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152279 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049854 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047331 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331123 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.142307 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076115 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.098865 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130830 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094310 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110603 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065284 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.238597 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.148216 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110603 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065284 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.238597 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.148216 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26611.932820 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16207.554393 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8223.555786 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55495.662820 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43929.204070 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36152.903286 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13330.861244 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19505.776970 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9281.147413 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 36000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35468.302716 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31468.873136 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19150.163305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35468.302716 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31468.873136 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19150.163305 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1652562 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2580 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 59814 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.628348 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 215 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 64418479 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 64418479 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4048167 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1034034 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2748996 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7831197 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3168136 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 783371 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1326904 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372517000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 424017500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796534500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665934500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 722111500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388046000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078441 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084333 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038801 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047331 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048923 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022380 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.098865 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103978 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040356 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25611.932820 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17968.249272 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19880.199794 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54495.662820 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46495.213765 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.333423 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.889252 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.949342 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 35000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230233.003708 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226545.648464 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225970.308789 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.883268 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 836302 # number of writebacks +system.cpu0.dcache.writebacks::total 836302 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 286455 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 286455 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 571181 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 571181 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1840 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1840 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 857636 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 857636 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 857636 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 857636 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 87342 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 258052 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 345394 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38690 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 97532 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 136222 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2145 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5420 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7565 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 22 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 22 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 126032 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 355584 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 481616 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 126032 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 355584 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 481616 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1346 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1396 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2742 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1629 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 1971 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3600 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2975 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3367 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6342 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2228045000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4632792500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860837500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092472500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4580895301 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6673367801 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26648000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69159500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95807500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 489000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 489000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4320517500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9213687801 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13534205301 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4320517500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9213687801 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13534205301 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296833500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 314974000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 611807500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 374975500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 441435000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 816410500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 671809000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 756409000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1428218000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.077888 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.078352 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037572 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047065 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048873 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022142 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099522 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.082310 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035739 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000406 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000110 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.064850 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067229 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.064850 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.067229 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031386 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25509.434178 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17952.941655 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19863.800471 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54083.031791 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46968.126369 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48988.913692 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12423.310023 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12760.055351 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12664.573695 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 22227.272727 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22227.272727 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34281.115114 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25911.424026 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28101.652148 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34281.115114 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25911.424026 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28101.652148 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220530.089153 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225626.074499 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223124.544128 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230187.538367 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223964.992390 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226780.694444 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225818.151261 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224653.697654 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225199.936928 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 963447 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.175727 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41538422 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 963958 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 43.091527 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10558559500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250530 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956033 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.969164 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.510255 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160070 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328065 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998390 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 969392 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.185439 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43108744 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 969903 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 44.446449 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10560905500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 255.222519 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 86.294219 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 169.668701 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.498481 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.168543 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.331384 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998409 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43483376 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43483376 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32077016 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7032806 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2428600 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41538422 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32077016 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7032806 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2428600 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41538422 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32077016 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7032806 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2428600 # number of overall hits -system.cpu0.icache.overall_hits::total 41538422 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 512139 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 125213 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 343464 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 980816 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 512139 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 125213 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 343464 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 980816 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 512139 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 125213 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 343464 # number of overall misses -system.cpu0.icache.overall_misses::total 980816 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1899535500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5061406468 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6960941968 # 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number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7158019 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2772064 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42519238 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32589155 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7158019 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2772064 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42519238 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015715 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.017493 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.123902 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023068 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015715 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.017493 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.123902 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023068 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015715 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017493 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.123902 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023068 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15170.433581 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14736.352188 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7097.092592 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15170.433581 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14736.352188 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7097.092592 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15170.433581 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14736.352188 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7097.092592 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8655 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 45070514 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 45070514 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 33100208 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7336693 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2671843 # 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average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14677.787995 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7098.202203 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15186.253536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14677.787995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7098.202203 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8327 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 361 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 386 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.975069 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.572539 # 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mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010630 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010630 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13857.183250 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13737.156647 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4484314476 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6294636476 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1810322000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4484314476 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6294636476 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1810322000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4484314476 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6294636476 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017096 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.107958 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010285 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017096 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.107958 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010285 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017096 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.107958 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010285 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13877.737624 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13877.737624 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13877.737624 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1125881 # DTB read hits -system.cpu1.dtb.read_misses 1262 # DTB read misses -system.cpu1.dtb.read_acv 31 # DTB read access violations -system.cpu1.dtb.read_accesses 118172 # DTB read accesses -system.cpu1.dtb.write_hits 832506 # DTB write hits -system.cpu1.dtb.write_misses 154 # DTB write misses +system.cpu1.dtb.read_hits 1140904 # DTB read hits +system.cpu1.dtb.read_misses 1286 # DTB read misses +system.cpu1.dtb.read_acv 30 # DTB read access violations +system.cpu1.dtb.read_accesses 118136 # DTB read accesses +system.cpu1.dtb.write_hits 843894 # DTB write hits +system.cpu1.dtb.write_misses 157 # DTB write misses system.cpu1.dtb.write_acv 18 # DTB write access violations -system.cpu1.dtb.write_accesses 48626 # DTB write accesses -system.cpu1.dtb.data_hits 1958387 # DTB hits -system.cpu1.dtb.data_misses 1416 # DTB misses -system.cpu1.dtb.data_acv 49 # DTB access violations -system.cpu1.dtb.data_accesses 166798 # DTB accesses -system.cpu1.itb.fetch_hits 755228 # ITB hits -system.cpu1.itb.fetch_misses 636 # ITB misses +system.cpu1.dtb.write_accesses 48616 # DTB write accesses +system.cpu1.dtb.data_hits 1984798 # DTB hits +system.cpu1.dtb.data_misses 1443 # DTB misses +system.cpu1.dtb.data_acv 48 # DTB access violations +system.cpu1.dtb.data_accesses 166752 # DTB accesses +system.cpu1.itb.fetch_hits 760414 # ITB hits +system.cpu1.itb.fetch_misses 659 # ITB misses system.cpu1.itb.fetch_acv 28 # ITB acv -system.cpu1.itb.fetch_accesses 755864 # ITB accesses +system.cpu1.itb.fetch_accesses 761073 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -929,7 +925,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953452805 # number of cpu cycles simulated +system.cpu1.numCycles 953506414 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -949,90 +945,94 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7156553 # Number of instructions committed -system.cpu1.committedOps 7156553 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6641394 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 39637 # Number of float alu accesses -system.cpu1.num_func_calls 205363 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 849545 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6641394 # number of integer instructions -system.cpu1.num_fp_insts 39637 # number of float instructions -system.cpu1.num_int_register_reads 9238548 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4861490 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 20633 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21093 # number of times the floating registers were written -system.cpu1.num_mem_refs 1965214 # number of memory refs -system.cpu1.num_load_insts 1130466 # Number of load instructions -system.cpu1.num_store_insts 834748 # Number of store instructions -system.cpu1.num_idle_cycles 924897133.577308 # Number of idle cycles -system.cpu1.num_busy_cycles 28555671.422692 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029950 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970050 # Percentage of idle cycles -system.cpu1.Branches 1119461 # Number of branches fetched -system.cpu1.op_class::No_OpClass 390354 5.45% 5.45% # Class of executed instruction -system.cpu1.op_class::IntAlu 4632011 64.71% 70.16% # Class of executed instruction -system.cpu1.op_class::IntMult 7720 0.11% 70.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3352 0.05% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatDiv 449 0.01% 70.33% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::MemRead 1159039 16.19% 86.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 835953 11.68% 98.20% # Class of executed instruction -system.cpu1.op_class::IprAccess 129140 1.80% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7462812 # Number of instructions committed +system.cpu1.committedOps 7462812 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6940057 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 40181 # Number of float alu accesses +system.cpu1.num_func_calls 208293 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 930314 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6940057 # number of integer instructions +system.cpu1.num_fp_insts 40181 # number of float instructions +system.cpu1.num_int_register_reads 9712470 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5067319 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 20912 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21313 # number of times the floating registers were written +system.cpu1.num_mem_refs 1991766 # number of memory refs +system.cpu1.num_load_insts 1145591 # Number of load instructions +system.cpu1.num_store_insts 846175 # Number of store instructions +system.cpu1.num_idle_cycles 924284293.570885 # Number of idle cycles +system.cpu1.num_busy_cycles 29222120.429115 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030647 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969353 # Percentage of idle cycles +system.cpu1.Branches 1204252 # Number of branches fetched +system.cpu1.op_class::No_OpClass 396048 5.31% 5.31% # Class of executed instruction +system.cpu1.op_class::IntAlu 4903561 65.69% 71.00% # Class of executed instruction +system.cpu1.op_class::IntMult 7744 0.10% 71.10% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.10% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3327 0.04% 71.15% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::FloatDiv 440 0.01% 71.15% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.15% # Class of executed instruction +system.cpu1.op_class::MemRead 1174639 15.74% 86.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 847384 11.35% 98.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 131160 1.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7158018 # Class of executed instruction -system.cpu2.branchPred.lookups 10791255 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10058403 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 121654 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8435844 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6655738 # Number of BTB hits +system.cpu1.op_class::total 7464303 # Class of executed instruction +system.cpu2.branchPred.lookups 11115445 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10184701 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 190030 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8583596 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6500261 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 78.898306 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 298678 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7720 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 75.728879 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 358939 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 14100 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1769440 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 184650 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 1584790 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 83567 # Number of mispredicted indirect branches. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3519605 # DTB read hits -system.cpu2.dtb.read_misses 12192 # DTB read misses -system.cpu2.dtb.read_acv 125 # DTB read access violations -system.cpu2.dtb.read_accesses 255658 # DTB read accesses -system.cpu2.dtb.write_hits 2173211 # DTB write hits -system.cpu2.dtb.write_misses 2700 # DTB write misses -system.cpu2.dtb.write_acv 124 # DTB write access violations -system.cpu2.dtb.write_accesses 93379 # DTB write accesses -system.cpu2.dtb.data_hits 5692816 # DTB hits -system.cpu2.dtb.data_misses 14892 # DTB misses -system.cpu2.dtb.data_acv 249 # DTB access violations -system.cpu2.dtb.data_accesses 349037 # DTB accesses -system.cpu2.itb.fetch_hits 552522 # ITB hits -system.cpu2.itb.fetch_misses 5239 # ITB misses -system.cpu2.itb.fetch_acv 186 # ITB acv -system.cpu2.itb.fetch_accesses 557761 # ITB accesses +system.cpu2.dtb.read_hits 3745527 # DTB read hits +system.cpu2.dtb.read_misses 14326 # DTB read misses +system.cpu2.dtb.read_acv 141 # DTB read access violations +system.cpu2.dtb.read_accesses 264538 # DTB read accesses +system.cpu2.dtb.write_hits 2181134 # DTB write hits +system.cpu2.dtb.write_misses 3579 # DTB write misses +system.cpu2.dtb.write_acv 134 # DTB write access violations +system.cpu2.dtb.write_accesses 94734 # DTB write accesses +system.cpu2.dtb.data_hits 5926661 # DTB hits +system.cpu2.dtb.data_misses 17905 # DTB misses +system.cpu2.dtb.data_acv 275 # DTB access violations +system.cpu2.dtb.data_accesses 359272 # DTB accesses +system.cpu2.itb.fetch_hits 551804 # ITB hits +system.cpu2.itb.fetch_misses 2698 # ITB misses +system.cpu2.itb.fetch_acv 198 # ITB acv +system.cpu2.itb.fetch_accesses 554502 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1045,303 +1045,303 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 32231216 # number of cpu cycles simulated +system.cpu2.numCycles 32148288 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9243140 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 40614337 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10791255 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6954416 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 20748537 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 401448 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 916 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 2007 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 193088 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 89379 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1066 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2772079 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 89992 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.icacheStallCycles 9118770 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 42633402 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 11115445 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 7043850 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20872660 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 537018 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10698 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1962 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 54145 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 92611 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 906 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3019400 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 130811 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 30488864 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.332104 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.325204 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 30420027 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.401491 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.386543 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 21032791 68.99% 68.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 294156 0.96% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 468874 1.54% 71.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5033027 16.51% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 879823 2.89% 90.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194768 0.64% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 230051 0.75% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433078 1.42% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1922296 6.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20612041 67.76% 67.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 327280 1.08% 68.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509415 1.67% 70.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5051332 16.61% 87.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 910040 2.99% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 211501 0.70% 90.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 256047 0.84% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 439619 1.45% 93.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2102752 6.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 30488864 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.334808 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.260093 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7572995 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 14121086 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7836457 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 524591 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 187872 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 174587 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13215 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 37262943 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 41463 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 187872 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7849913 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4677015 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6609993 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8056869 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2861349 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 36455800 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 58084 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 369048 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 93720 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1797134 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 24334504 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 45550794 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 45486602 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 59958 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22464723 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1869781 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 530990 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 62923 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3828293 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3503034 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2266301 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 453472 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 325651 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 33952570 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 679538 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 33658910 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16165 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2512562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1127430 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 486035 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 30488864 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.103974 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.612784 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30420027 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.345755 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.326148 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7385112 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13918236 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8048801 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 564027 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 258008 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 221892 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 11066 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 38888307 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 34887 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 258008 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7685688 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4963925 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6082795 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8292905 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2890873 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 37903882 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 59292 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 377519 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 110958 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1815831 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 25463853 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 47138476 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 47075647 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 58641 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22316309 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 3147544 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 533093 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 73531 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3880120 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3861851 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2321017 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 521824 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 313958 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 35078134 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 686210 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34388477 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 25878 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 3859283 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1728855 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 496373 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30420027 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.130455 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.630155 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18447860 60.51% 60.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2702530 8.86% 69.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1349610 4.43% 73.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5752968 18.87% 92.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1041424 3.42% 96.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 588365 1.93% 98.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 396836 1.30% 99.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 164449 0.54% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44822 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18175934 59.75% 59.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2731876 8.98% 68.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1376382 4.52% 73.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5800287 19.07% 92.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1083705 3.56% 95.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 612376 2.01% 97.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 420135 1.38% 99.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 169190 0.56% 99.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 50142 0.16% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 30488864 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30420027 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 81533 21.03% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.03% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 179737 46.36% 67.39% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126415 32.61% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 80804 19.32% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 207140 49.52% 68.84% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 130362 31.16% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 3114 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 27463980 81.59% 81.60% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21318 0.06% 81.67% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 22163 0.07% 81.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1557 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3647310 10.84% 92.57% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2197101 6.53% 99.10% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 302367 0.90% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 3134 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27917447 81.18% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21186 0.06% 81.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 22118 0.06% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3912960 11.38% 92.70% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2212878 6.43% 99.14% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 297188 0.86% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 33658910 # Type of FU issued -system.cpu2.iq.rate 1.044295 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 387685 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.011518 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 97946508 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 37024649 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 33041720 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 264026 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 125654 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122549 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 33902559 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 140922 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 200179 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34388477 # Type of FU issued +system.cpu2.iq.rate 1.069683 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 418306 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.012164 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 99374264 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39499421 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 33606798 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 266901 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 130860 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122949 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 34661254 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 142395 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 213891 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 430903 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1110 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5745 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178531 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 829369 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1314 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6796 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 267816 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4239 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 217245 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4168 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 214093 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 187872 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4009534 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 206574 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35996335 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51785 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3503034 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2266301 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 605122 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12947 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 158194 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5745 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 59769 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 133968 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193737 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33463084 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3540458 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 195826 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 258008 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4262177 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 221870 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 37207095 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 66855 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3861851 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2321017 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 613182 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 13352 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 173159 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6796 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 74128 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 200909 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 275037 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 34112414 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3770128 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 276063 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1364227 # number of nop insts executed -system.cpu2.iew.exec_refs 5721059 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7732015 # Number of branches executed -system.cpu2.iew.exec_stores 2180601 # Number of stores executed -system.cpu2.iew.exec_rate 1.038220 # Inst execution rate -system.cpu2.iew.wb_sent 33206737 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 33164269 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 19394211 # num instructions producing a value -system.cpu2.iew.wb_consumers 23137569 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.028949 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.838213 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 2629534 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 193503 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177029 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 30027785 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.109667 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.847605 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 1442751 # number of nop insts executed +system.cpu2.iew.exec_refs 5960966 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7830155 # Number of branches executed +system.cpu2.iew.exec_stores 2190838 # Number of stores executed +system.cpu2.iew.exec_rate 1.061096 # Inst execution rate +system.cpu2.iew.wb_sent 33803794 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 33729747 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 19634882 # num instructions producing a value +system.cpu2.iew.wb_consumers 23447045 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.049193 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.837414 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 4049200 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 189837 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 246514 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 29720868 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.113415 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846179 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 19194769 63.92% 63.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2226064 7.41% 71.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1158797 3.86% 75.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5473612 18.23% 93.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 589514 1.96% 95.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 197059 0.66% 96.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164152 0.55% 96.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 162472 0.54% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 861346 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18948933 63.76% 63.76% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2226621 7.49% 71.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1117677 3.76% 75.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5469793 18.40% 93.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 585496 1.97% 95.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 200130 0.67% 96.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 163612 0.55% 96.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 172854 0.58% 97.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 835752 2.81% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 30027785 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 33320829 # Number of instructions committed -system.cpu2.commit.committedOps 33320829 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 29720868 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 33091654 # Number of instructions committed +system.cpu2.commit.committedOps 33091654 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5159901 # Number of memory references committed -system.cpu2.commit.loads 3072131 # Number of loads committed -system.cpu2.commit.membars 67946 # Number of memory barriers committed -system.cpu2.commit.branches 7559828 # Number of branches committed -system.cpu2.commit.fp_insts 120718 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31821279 # Number of committed integer instructions. -system.cpu2.commit.function_calls 240082 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1204397 3.61% 3.61% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 26540433 79.65% 83.27% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20865 0.06% 83.33% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21723 0.07% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1557 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3140077 9.42% 92.82% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2089410 6.27% 99.09% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 302367 0.91% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5085683 # Number of memory references committed +system.cpu2.commit.loads 3032482 # Number of loads committed +system.cpu2.commit.membars 66632 # Number of memory barriers committed +system.cpu2.commit.branches 7528249 # Number of branches committed +system.cpu2.commit.fp_insts 118326 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31611835 # Number of committed integer instructions. +system.cpu2.commit.function_calls 236844 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1189725 3.60% 3.60% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26406955 79.80% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20610 0.06% 83.46% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.46% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21680 0.07% 83.52% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.52% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.52% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.52% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.53% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3099114 9.37% 92.89% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2054816 6.21% 99.10% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 297188 0.90% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 33320829 # Class of committed instruction -system.cpu2.commit.bw_lim_events 861346 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 65041726 # The number of ROB reads -system.cpu2.rob.rob_writes 72360391 # The number of ROB writes -system.cpu2.timesIdled 178229 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1742352 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747482810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 32119546 # Number of Instructions Simulated -system.cpu2.committedOps 32119546 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.003477 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.003477 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.996535 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.996535 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 43931463 # number of integer regfile reads -system.cpu2.int_regfile_writes 23250358 # number of integer regfile writes -system.cpu2.fp_regfile_reads 74602 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74558 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5374687 # number of misc regfile reads -system.cpu2.misc_regfile_writes 272957 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 33091654 # Class of committed instruction +system.cpu2.commit.bw_lim_events 835752 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 65950880 # The number of ROB reads +system.cpu2.rob.rob_writes 74981980 # The number of ROB writes +system.cpu2.timesIdled 163418 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1728261 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747565688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31905061 # Number of Instructions Simulated +system.cpu2.committedOps 31905061 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.007623 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.007623 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.992434 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.992434 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 44683951 # number of integer regfile reads +system.cpu2.int_regfile_writes 23750131 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73395 # number of floating regfile reads +system.cpu2.fp_regfile_writes 76222 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5369196 # number of misc regfile reads +system.cpu2.misc_regfile_writes 267799 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1384,31 +1384,31 @@ system.iobus.pkt_size_system.bridge.master::total 45584 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2566000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2556000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 118500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 130500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 55500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 65000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6361000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2120500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2150000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 86466426 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 80490654 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9084000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16844000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 15688000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261273 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261471 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694926915000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261273 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078830 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078830 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694927317000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261471 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078842 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078842 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1422,14 +1422,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9575962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9575962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2102569464 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2102569464 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9575962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9575962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9575962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9575962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9857962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9857962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 1957317692 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1957317692 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9857962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9857962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9857962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9857962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1446,14 +1446,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55352.381503 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 55352.381503 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 50600.920870 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 50600.920870 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 55352.381503 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 55352.381503 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56982.439306 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 56982.439306 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 47105.258279 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 47105.258279 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 56982.439306 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 56982.439306 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 56982.439306 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 56982.439306 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1464,252 +1464,252 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # 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number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6075962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 6075962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6075962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.400847 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.400847 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # 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mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.358939 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.277474 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.135412 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017945 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013195 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.113905 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046632 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020579 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017945 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.187867 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013195 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109046 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.029617 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017945 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.187867 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013195 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109046 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.029617 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68466.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68466.666667 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 69166.666667 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69166.666667 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117717.433571 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125717.838417 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 123005.992336 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121568.340611 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 124325.698605 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123367.527162 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116185.715687 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117655.634262 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116988.987764 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121568.340611 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117069.061462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 124325.698605 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123202.342242 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121109.061370 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121568.340611 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117069.061462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 124325.698605 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123202.342242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121109.061370 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208024.888559 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 213125.358166 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210621.626550 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218681.706568 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212463.470320 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215277.222222 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213860.168067 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212737.897238 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213264.348786 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294755 # Transaction distribution +system.membus.trans_dist::ReadResp 295030 # Transaction distribution system.membus.trans_dist::WriteReq 9812 # Transaction distribution system.membus.trans_dist::WriteResp 9812 # Transaction distribution -system.membus.trans_dist::WritebackDirty 116723 # Transaction distribution -system.membus.trans_dist::CleanEvict 261851 # Transaction distribution -system.membus.trans_dist::UpgradeReq 160 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 116 # Transaction distribution -system.membus.trans_dist::ReadExReq 115650 # Transaction distribution -system.membus.trans_dist::ReadExResp 115650 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287867 # Transaction distribution -system.membus.trans_dist::BadAddressError 256 # Transaction distribution +system.membus.trans_dist::WritebackDirty 116832 # Transaction distribution +system.membus.trans_dist::CleanEvict 261846 # Transaction distribution +system.membus.trans_dist::UpgradeReq 193 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 117 # Transaction distribution +system.membus.trans_dist::ReadExReq 115481 # Transaction distribution +system.membus.trans_dist::ReadExResp 115481 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287900 # Transaction distribution +system.membus.trans_dist::BadAddressError 14 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 24896 # Transaction distribution +system.membus.trans_dist::InvalidateResp 26048 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143238 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 512 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177662 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1286086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 28 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109578 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109578 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1287126 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30604608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30650192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33314512 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 160 # Total snoops (count) -system.membus.snoop_fanout::samples 840765 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30619392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30664976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33329424 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 142 # Total snoops (count) +system.membus.snoop_fanout::samples 840769 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840769 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840765 # Request fanout histogram -system.membus.reqLayer0.occupancy 11148000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840769 # Request fanout histogram +system.membus.reqLayer0.occupancy 11262500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 350987320 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 344258394 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 374958750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 375059750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 368038 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 358538 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4714924 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2357142 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1129 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1129 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4728439 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2363791 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1687 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1128 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1128 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062215 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2069439 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 879068 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 963447 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 600902 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 878363 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 969392 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 601395 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 39 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302901 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302901 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 964138 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091204 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 256 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 16656 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4215380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7107076 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123363712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142746256 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266109968 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421211 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4208443 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.000983 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.031334 # Request fanout histogram +system.toL2Bus.trans_dist::SCUpgradeReq 25 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 60 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302550 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302550 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 970097 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1092227 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 14 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 15504 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2909488 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4217684 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7127172 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124121024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142832784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266953808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421384 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4223997 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.001001 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.031618 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4204307 99.90% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4136 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4219770 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4227 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4208443 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1783289500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4223997 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1779844500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 97962 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 678414167 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 680727278 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 743545456 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 738329921 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |