diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
3 files changed, 4183 insertions, 4208 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 8de825134..353384b9f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903702 # Number of seconds simulated -sim_ticks 1903702212500 # Number of ticks simulated -final_tick 1903702212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904274 # Number of seconds simulated +sim_ticks 1904273734500 # Number of ticks simulated +final_tick 1904273734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94355 # Simulator instruction rate (inst/s) -host_op_rate 94355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3162860632 # Simulator tick rate (ticks/s) -host_mem_usage 314400 # Number of bytes of host memory used -host_seconds 601.89 # Real time elapsed on the host -sim_insts 56791782 # Number of instructions simulated -sim_ops 56791782 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 898816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24768192 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 430592 # Number of bytes read from this memory -system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 898816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7790720 # Number of bytes written to this memory -system.physmem.bytes_written::total 7790720 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387003 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6728 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121730 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121730 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 472141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13010539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 226187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15141931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 472141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4092405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4092405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4092405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 472141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13010539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 226187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19234336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450402 # Total number of read requests seen -system.physmem.writeReqs 121730 # Total number of write requests seen -system.physmem.cpureqs 577215 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28825728 # Total number of bytes read from memory -system.physmem.bytesWritten 7790720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7790720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5081 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28459 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28620 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7644 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6897 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7004 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7923 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8079 # Track writes on a per bank basis +host_inst_rate 95291 # Simulator instruction rate (inst/s) +host_op_rate 95291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3200085877 # Simulator tick rate (ticks/s) +host_mem_usage 314408 # Number of bytes of host memory used +host_seconds 595.07 # Real time elapsed on the host +sim_insts 56704659 # Number of instructions simulated +sim_ops 56704659 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 939456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24909888 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 36288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 341184 # Number of bytes read from this memory +system.physmem.bytes_read::total 28877632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 939456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 36288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 975744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7866880 # Number of bytes written to this memory +system.physmem.bytes_written::total 7866880 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389217 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 567 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5331 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451213 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122920 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122920 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 493341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13081044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1392035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 179168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15164643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 493341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4131171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4131171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4131171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 493341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13081044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1392035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 179168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19295814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451213 # Total number of read requests seen +system.physmem.writeReqs 122920 # Total number of write requests seen +system.physmem.cpureqs 579004 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28877632 # Total number of bytes read from memory +system.physmem.bytesWritten 7866880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28877632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7866880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4871 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28452 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28334 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27691 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7420 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7615 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7448 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7267 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7422 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7420 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8140 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8013 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7323 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 1903701167000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1904269209000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450402 # Categorize read packet sizes +system.physmem.readPktSize::6 451213 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121730 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1498 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122920 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1488 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -138,395 +138,398 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 910.430717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 224.153261 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2362.806871 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14303 35.57% 35.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6082 15.12% 50.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3751 9.33% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2511 6.24% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1745 4.34% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1426 3.55% 74.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1071 2.66% 76.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 838 2.08% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 669 1.66% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 518 1.29% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 558 1.39% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 522 1.30% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 270 0.67% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 231 0.57% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 190 0.47% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 283 0.70% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 119 0.30% 87.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 115 0.29% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 106 0.26% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 202 0.50% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 170 0.42% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 105 0.26% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 478 1.19% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 629 1.56% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 105 0.26% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 36 0.09% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 35 0.09% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 97 0.24% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 7 0.02% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 13 0.03% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 52 0.13% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 1 0.00% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.01% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.01% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 9 0.02% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 8 0.02% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 10 0.02% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 7 0.02% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 9 0.02% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 4 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 4 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 2 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 4 0.01% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 3 0.01% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2430 6.04% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 3741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 904.415372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.615874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2354.830128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14269 35.13% 35.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6234 15.35% 50.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3791 9.33% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2540 6.25% 66.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1773 4.36% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1547 3.81% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1102 2.71% 76.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 849 2.09% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 692 1.70% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 549 1.35% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 540 1.33% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 500 1.23% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 249 0.61% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 230 0.57% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 188 0.46% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 304 0.75% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 110 0.27% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 108 0.27% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 118 0.29% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 201 0.49% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 117 0.29% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 501 1.23% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 643 1.58% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 97 0.24% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 31 0.08% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 107 0.26% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 9 0.02% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 14 0.03% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 38 0.09% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 3 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 4 0.01% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 21 0.05% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 11 0.03% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 2 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.01% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 3 0.01% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 5 0.01% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.01% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 1 0.00% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.00% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2429 5.98% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.03% 99.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 251 0.62% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 8 0.02% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 248 0.61% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 7 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17219 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40212 # Bytes accessed per row activation -system.physmem.totQLat 6402871500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13861687750 # Sum of mem lat for all requests -system.physmem.totBusLat 2251705000 # Total cycles spent in databus access -system.physmem.totBankLat 5207111250 # Total cycles spent in bank access -system.physmem.avgQLat 14217.83 # Average queueing delay per request -system.physmem.avgBankLat 11562.60 # Average bank access latency per request +system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40619 # Bytes accessed per row activation +system.physmem.totQLat 6391304750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13854944750 # Sum of mem lat for all requests +system.physmem.totBusLat 2255690000 # Total cycles spent in databus access +system.physmem.totBankLat 5207950000 # Total cycles spent in bank access +system.physmem.avgQLat 14167.07 # Average queueing delay per request +system.physmem.avgBankLat 11544.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30780.43 # Average memory access latency -system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30711.10 # Average memory access latency +system.physmem.avgRdBW 15.16 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.13 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.16 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.13 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.34 # Average write queue length over time -system.physmem.readRowHits 434557 # Number of row buffer hits during reads -system.physmem.writeRowHits 97288 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.92 # Row buffer hit rate for writes -system.physmem.avgGap 3327381.04 # Average gap between requests -system.membus.throughput 19293384 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296598 # Transaction distribution -system.membus.trans_dist::ReadResp 296521 # Transaction distribution -system.membus.trans_dist::WriteReq 13135 # Transaction distribution -system.membus.trans_dist::WriteResp 13135 # Transaction distribution -system.membus.trans_dist::Writeback 121730 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10421 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6167 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5084 # Transaction distribution -system.membus.trans_dist::ReadExReq 162105 # Transaction distribution -system.membus.trans_dist::ReadExResp 161668 # Transaction distribution +system.physmem.avgWrQLen 14.33 # Average write queue length over time +system.physmem.readRowHits 435283 # Number of row buffer hits during reads +system.physmem.writeRowHits 98148 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes +system.physmem.avgGap 3316773.66 # Average gap between requests +system.membus.throughput 19353836 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296513 # Transaction distribution +system.membus.trans_dist::ReadResp 296436 # Transaction distribution +system.membus.trans_dist::WriteReq 13046 # Transaction distribution +system.membus.trans_dist::WriteResp 13046 # Transaction distribution +system.membus.trans_dist::Writeback 122920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9558 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5502 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4874 # Transaction distribution +system.membus.trans_dist::ReadExReq 162935 # Transaction distribution +system.membus.trans_dist::ReadExResp 162546 # Transaction distribution system.membus.trans_dist::BadAddressError 77 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921574 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 961398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 40658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1045233 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 962210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 40482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1046240 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1086045 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 74458 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31309568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31384026 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 74458 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36616448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36690906 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36690906 # Total data (bytes) -system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 38097999 # Layer occupancy (ticks) +system.membus.pkt_count::total 1086876 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31436416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31510170 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 36744512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36818266 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36818266 # Total data (bytes) +system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 37871498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1605971749 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1615737499 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 99000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3826622399 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3831920118 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376246245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376228744 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 343505 # number of replacements -system.l2c.tagsinuse 65255.093992 # Cycle average of tags in use -system.l2c.total_refs 2579423 # Total number of references to valid blocks. -system.l2c.sampled_refs 408514 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.314161 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6822436750 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53604.114045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5280.498450 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6105.169912 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 200.990170 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 64.321415 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.817934 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080574 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093157 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003067 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000981 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995714 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 854455 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 729616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 224847 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 72618 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1881536 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 819443 # number of Writeback hits -system.l2c.Writeback_hits::total 819443 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 291 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 461 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 69 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 152110 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27598 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179708 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 854455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 881726 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 224847 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 100216 # number of demand (read+write) hits -system.l2c.demand_hits::total 2061244 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 854455 # number of overall hits -system.l2c.overall_hits::cpu0.data 881726 # number of overall hits -system.l2c.overall_hits::cpu1.inst 224847 # number of overall hits -system.l2c.overall_hits::cpu1.data 100216 # number of overall hits -system.l2c.overall_hits::total 2061244 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14046 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273516 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1243 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 442 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289247 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2692 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1131 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3823 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 459 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 486 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 945 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114088 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6344 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120432 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14046 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387604 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1243 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6786 # number of demand (read+write) misses -system.l2c.demand_misses::total 409679 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14046 # number of overall misses -system.l2c.overall_misses::cpu0.data 387604 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1243 # number of overall misses -system.l2c.overall_misses::cpu1.data 6786 # number of overall misses -system.l2c.overall_misses::total 409679 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1212902500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17141442000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 111720500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 37403000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18503468000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 969500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5036492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 6005992 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 803000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 136500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 939500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9233070997 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 696312000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9929382997 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1212902500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26374512997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 111720500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 733715000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 28432850997 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1212902500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26374512997 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 111720500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 733715000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 28432850997 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 868501 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1003132 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 226090 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 73060 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2170783 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 819443 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 819443 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2862 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1422 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4284 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 502 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 512 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1014 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 266198 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 33942 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300140 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 868501 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1269330 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 226090 # 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miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940601 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795359 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.892390 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.914343 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.949219 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.931953 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.428583 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.186907 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.401253 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.305361 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005498 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73889.329806 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95483.872639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57272.434121 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73637.228065 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56107.900804 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73889.329806 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95483.872639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57272.434121 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -664,15 +667,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41695 # number of replacements -system.iocache.tagsinuse 0.492474 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1710349466000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.492474 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.030780 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.030780 # Average percentage of cache occupancy +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.488928 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.488928 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030558 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030558 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -681,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41727 # n system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21568883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21568883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10518241771 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10518241771 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10539810654 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10539810654 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10539810654 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10539810654 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21574383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21574383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10460928278 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10460928278 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10482502661 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10482502661 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10482502661 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10482502661 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -705,19 +708,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123250.760000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123250.760000 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 253134.428451 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 253134.428451 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 252589.705802 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 252589.705802 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 276539 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123282.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123282.188571 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251755.108731 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251755.108731 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 251216.302658 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 251216.302658 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 272971 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27281 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27017 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.136689 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.103675 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -731,14 +734,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41727 system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12468133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8356835276 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8356835276 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8369303409 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8369303409 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8369303409 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8369303409 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12472883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12472883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8298854290 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8298854290 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8311327173 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8311327173 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8311327173 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8311327173 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -747,14 +750,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71246.474286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71246.474286 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 201117.522045 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 201117.522045 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71273.617143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71273.617143 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199722.138285 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199722.138285 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -768,35 +771,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12372167 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10430268 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 327512 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8051050 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5251093 # Number of BTB hits +system.cpu0.branchPred.lookups 12622908 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10616030 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 342195 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8196943 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5349460 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.222462 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 787082 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28165 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.261647 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 815211 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29656 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8811099 # DTB read hits -system.cpu0.dtb.read_misses 30390 # DTB read misses -system.cpu0.dtb.read_acv 555 # DTB read access violations -system.cpu0.dtb.read_accesses 626499 # DTB read accesses -system.cpu0.dtb.write_hits 5759352 # DTB write hits -system.cpu0.dtb.write_misses 7345 # DTB write misses -system.cpu0.dtb.write_acv 331 # DTB write access violations -system.cpu0.dtb.write_accesses 208988 # DTB write accesses -system.cpu0.dtb.data_hits 14570451 # DTB hits -system.cpu0.dtb.data_misses 37735 # DTB misses -system.cpu0.dtb.data_acv 886 # DTB access violations -system.cpu0.dtb.data_accesses 835487 # DTB accesses -system.cpu0.itb.fetch_hits 988720 # ITB hits -system.cpu0.itb.fetch_misses 28459 # ITB misses -system.cpu0.itb.fetch_acv 940 # ITB acv -system.cpu0.itb.fetch_accesses 1017179 # ITB accesses +system.cpu0.dtb.read_hits 9003860 # DTB read hits +system.cpu0.dtb.read_misses 33263 # DTB read misses +system.cpu0.dtb.read_acv 538 # DTB read access violations +system.cpu0.dtb.read_accesses 672573 # DTB read accesses +system.cpu0.dtb.write_hits 5893133 # DTB write hits +system.cpu0.dtb.write_misses 8284 # DTB write misses +system.cpu0.dtb.write_acv 368 # DTB write access violations +system.cpu0.dtb.write_accesses 235576 # DTB write accesses +system.cpu0.dtb.data_hits 14896993 # DTB hits +system.cpu0.dtb.data_misses 41547 # DTB misses +system.cpu0.dtb.data_acv 906 # DTB access violations +system.cpu0.dtb.data_accesses 908149 # DTB accesses +system.cpu0.itb.fetch_hits 1042149 # ITB hits +system.cpu0.itb.fetch_misses 31540 # ITB misses +system.cpu0.itb.fetch_acv 1064 # ITB acv +system.cpu0.itb.fetch_accesses 1073689 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -809,269 +812,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 113576100 # number of cpu cycles simulated +system.cpu0.numCycles 115698572 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24795587 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63494847 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12372167 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6038175 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11937811 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1694344 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37245698 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31806 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195246 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 359396 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7671411 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 221670 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 75653727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839282 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177028 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25430461 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 64765722 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12622908 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6164671 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12173111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1754282 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37681561 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 33129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 206182 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 360791 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 463 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7843120 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 77014869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.840951 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.178782 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63715916 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 763032 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1559362 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 696709 0.92% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2577784 3.41% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 516509 0.68% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 573501 0.76% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 819035 1.08% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4431879 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64841758 84.19% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 778083 1.01% 85.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1579221 2.05% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 722075 0.94% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2615191 3.40% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 535253 0.69% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 589170 0.77% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 842021 1.09% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4512097 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 75653727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.108933 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559051 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26076145 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36746783 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10850479 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 927296 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1053023 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 507905 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35356 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62314637 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105308 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1053023 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27090322 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15013520 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18214120 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10165522 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4117218 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58954969 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7221 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 636497 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1465868 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39489312 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71817747 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71438623 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 379124 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34689683 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4799621 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1442009 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 210125 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11209509 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9215492 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6028586 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1140138 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 729797 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52283270 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1794569 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51124724 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87475 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5854476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3047065 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1215266 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 75653727 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.675773 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.327184 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77014869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109102 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559780 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26714732 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 37197398 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11068686 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 941364 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1092688 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 522796 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36882 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 63559406 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 110759 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1092688 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27743135 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15107351 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18539290 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10375436 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4156967 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 60135459 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7108 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 639244 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1468640 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 40265671 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 73230382 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72843642 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 386740 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35289688 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4975975 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1473731 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 214800 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11344202 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9431276 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6179329 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1162337 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 768163 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53333771 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1831002 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52106137 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 101747 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6058761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3179609 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1240264 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77014869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.676572 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.327910 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52928215 69.96% 69.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10364815 13.70% 83.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4648030 6.14% 89.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3048990 4.03% 93.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2439160 3.22% 97.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1210231 1.60% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 645067 0.85% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 315070 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54149 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53895136 69.98% 69.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10485242 13.61% 83.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4754218 6.17% 89.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3135006 4.07% 93.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2479570 3.22% 97.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1230098 1.60% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 664050 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 318021 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53528 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 75653727 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77014869 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82277 12.13% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 315255 46.46% 58.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 280962 41.41% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83201 11.94% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 325493 46.71% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 288201 41.36% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35245093 68.94% 68.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56186 0.11% 69.06% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15594 0.03% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9165347 17.93% 87.02% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5826893 11.40% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 809947 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35867732 68.84% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57468 0.11% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15763 0.03% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9368607 17.98% 86.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5962928 11.44% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 827971 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51124724 # Type of FU issued -system.cpu0.iq.rate 0.450136 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 678494 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 178124739 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59681238 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50082929 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 544404 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 263662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 256861 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51514533 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 284900 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 542155 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52106137 # Type of FU issued +system.cpu0.iq.rate 0.450361 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 696895 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013375 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 181470771 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60967498 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51029740 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 555013 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 268874 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 261978 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52508945 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 290302 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 547963 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1111126 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3856 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12844 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 447697 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1165767 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4234 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13137 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 465736 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 153340 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18478 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 155290 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1053023 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10729289 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 792549 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57283617 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 622169 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9215492 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6028586 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1581349 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 577410 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6280 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12844 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 162347 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 348099 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 510446 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50735914 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8864635 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 388809 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1092688 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10796951 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 798319 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58424017 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 633798 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9431276 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6179329 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1612922 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 582630 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5498 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13137 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 168729 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 358890 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 527619 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51705429 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9061014 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 400707 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3205778 # number of nop insts executed -system.cpu0.iew.exec_refs 14644864 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8078425 # Number of branches executed -system.cpu0.iew.exec_stores 5780229 # Number of stores executed -system.cpu0.iew.exec_rate 0.446713 # Inst execution rate -system.cpu0.iew.wb_sent 50428595 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50339790 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25084021 # num instructions producing a value -system.cpu0.iew.wb_consumers 33790368 # num instructions consuming a value +system.cpu0.iew.exec_nop 3259244 # number of nop insts executed +system.cpu0.iew.exec_refs 14976241 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8231181 # Number of branches executed +system.cpu0.iew.exec_stores 5915227 # Number of stores executed +system.cpu0.iew.exec_rate 0.446898 # Inst execution rate +system.cpu0.iew.wb_sent 51387761 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51291718 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25550537 # num instructions producing a value +system.cpu0.iew.wb_consumers 34415470 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.443225 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742342 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443322 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742414 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6311482 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 579303 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 475138 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74600704 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.681919 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.596319 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6546847 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 590738 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 492268 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75922181 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681996 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.596696 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55419889 74.29% 74.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8033545 10.77% 85.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4371447 5.86% 90.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2356278 3.16% 94.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1324268 1.78% 95.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 555518 0.74% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 469565 0.63% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 427219 0.57% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1642975 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56427011 74.32% 74.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8133810 10.71% 85.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4455745 5.87% 90.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2411043 3.18% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1335893 1.76% 95.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 570067 0.75% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 478554 0.63% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 445477 0.59% 97.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1664581 2.19% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74600704 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50871658 # Number of instructions committed -system.cpu0.commit.committedOps 50871658 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75922181 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51778647 # Number of instructions committed +system.cpu0.commit.committedOps 51778647 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13685255 # Number of memory references committed -system.cpu0.commit.loads 8104366 # Number of loads committed -system.cpu0.commit.membars 196950 # Number of memory barriers committed -system.cpu0.commit.branches 7686240 # Number of branches committed -system.cpu0.commit.fp_insts 254806 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47114322 # Number of committed integer instructions. -system.cpu0.commit.function_calls 650737 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1642975 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13979102 # Number of memory references committed +system.cpu0.commit.loads 8265509 # Number of loads committed +system.cpu0.commit.membars 200777 # Number of memory barriers committed +system.cpu0.commit.branches 7822311 # Number of branches committed +system.cpu0.commit.fp_insts 259967 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47959803 # Number of committed integer instructions. +system.cpu0.commit.function_calls 666551 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1664581 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129943858 # The number of ROB reads -system.cpu0.rob.rob_writes 115419344 # The number of ROB writes -system.cpu0.timesIdled 1091777 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 37922373 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693821721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47948786 # Number of Instructions Simulated -system.cpu0.committedOps 47948786 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47948786 # Number of Instructions Simulated -system.cpu0.cpi 2.368696 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.368696 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.422173 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.422173 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66777793 # number of integer regfile reads -system.cpu0.int_regfile_writes 36448823 # number of integer regfile writes -system.cpu0.fp_regfile_reads 126128 # number of floating regfile reads -system.cpu0.fp_regfile_writes 127569 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1693303 # number of misc regfile reads -system.cpu0.misc_regfile_writes 810480 # number of misc regfile writes +system.cpu0.rob.rob_reads 132380203 # The number of ROB reads +system.cpu0.rob.rob_writes 117743806 # The number of ROB writes +system.cpu0.timesIdled 1106178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38683703 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3692842270 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48811521 # Number of Instructions Simulated +system.cpu0.committedOps 48811521 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 48811521 # Number of Instructions Simulated +system.cpu0.cpi 2.370313 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.370313 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.421885 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.421885 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68020458 # number of integer regfile reads +system.cpu0.int_regfile_writes 37124303 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128594 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130201 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1727987 # number of misc regfile reads +system.cpu0.misc_regfile_writes 827975 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1103,49 +1106,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111431458 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2199741 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2199647 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13135 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13135 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 819443 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10566 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6236 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16802 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343057 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301508 # Transaction distribution +system.toL2Bus.throughput 111303171 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2194950 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2194857 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13046 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13046 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 821103 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9701 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5568 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15269 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343378 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301828 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1737096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3343563 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 452207 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 314296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5847162 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 55584064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 129094452 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 14469760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 11514982 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 210663258 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210652954 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1479360 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4959879460 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1783020 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3388598 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 397843 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 270349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5839810 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 57053376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 131002064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 12730112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 9815754 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 210601306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210591002 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1360704 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964254488 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3910967404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4017252621 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5778463419 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5927096055 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1017961113 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 540290711 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 895637092 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 468506529 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1437243 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54687 # Transaction distribution -system.iobus.trans_dist::WriteResp 54687 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1436442 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 54598 # Transaction distribution +system.iobus.trans_dist::WriteResp 54598 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1156,11 +1159,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40482 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1172,9 +1175,9 @@ system.iobus.pkt_count::system.tsunami.ethernet.pio 102 system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 124112 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123936 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1185,11 +1188,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 74458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 73754 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1201,11 +1204,11 @@ system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2736082 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2736082 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11417000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2735378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2735378 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11237000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1225,253 +1228,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378279654 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378252917 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27523000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27436000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43098256 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.replacements 867916 # number of replacements -system.cpu0.icache.tagsinuse 509.785268 # Cycle average of tags in use -system.cpu0.icache.total_refs 6758563 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 868427 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.782534 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25769681000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.785268 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995674 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995674 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6758564 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6758564 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6758564 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6758564 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6758564 # number of overall hits -system.cpu0.icache.overall_hits::total 6758564 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 912847 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 912847 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 912847 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 912847 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 912847 # number of overall misses -system.cpu0.icache.overall_misses::total 912847 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13149310993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13149310993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13149310993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13149310993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13149310993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13149310993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7671411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7671411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7671411 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7671411 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7671411 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7671411 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118993 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118993 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118993 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118993 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118993 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118993 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14404.726086 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14404.726086 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14404.726086 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14404.726086 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3418 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 152 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.486842 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 890887 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.759385 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6905559 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891396 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.746904 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.759385 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995624 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995624 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6905559 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6905559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6905559 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6905559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6905559 # number of overall hits +system.cpu0.icache.overall_hits::total 6905559 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 937559 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 937559 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 937559 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 937559 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 937559 # number of overall misses +system.cpu0.icache.overall_misses::total 937559 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13556216106 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13556216106 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13556216106 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13556216106 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13556216106 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13556216106 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7843118 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7843118 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7843118 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7843118 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7843118 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7843118 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119539 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119539 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119539 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119539 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119539 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119539 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14459.053890 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14459.053890 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14459.053890 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14459.053890 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6417 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1109 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.168182 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 554.500000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44252 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44252 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44252 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44252 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44252 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44252 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868595 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 868595 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 868595 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 868595 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 868595 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 868595 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814937089 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814937089 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814937089 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10814937089 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814937089 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10814937089 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113225 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113225 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113225 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12451.069934 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45998 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45998 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45998 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45998 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45998 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45998 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 891561 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 891561 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 891561 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 891561 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 891561 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 891561 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11118457121 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11118457121 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11118457121 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11118457121 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11118457121 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11118457121 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113674 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113674 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113674 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12470.775551 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1271376 # number of replacements -system.cpu0.dcache.tagsinuse 505.686526 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10390956 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1271888 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.169710 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 25830000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.686526 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987669 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987669 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6393137 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6393137 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3639350 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3639350 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 161427 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 161427 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185616 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 185616 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10032487 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10032487 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10032487 # number of overall hits -system.cpu0.dcache.overall_hits::total 10032487 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1573505 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1573505 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1738147 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1738147 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20045 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20045 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3020 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3020 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3311652 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3311652 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3311652 # number of overall misses -system.cpu0.dcache.overall_misses::total 3311652 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39654304500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39654304500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77521243901 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77521243901 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 292960500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 292960500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 22204000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 22204000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117175548401 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117175548401 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117175548401 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117175548401 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7966642 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7966642 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5377497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5377497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 181472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 188636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13344139 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13344139 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13344139 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13344139 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197512 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197512 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323226 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323226 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110458 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110458 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248173 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248173 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248173 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248173 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25201.257384 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25201.257384 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44599.935392 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44599.935392 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14615.140933 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14615.140933 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7352.317881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7352.317881 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35382.808460 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35382.808460 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2842539 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 840 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 51698 # number of cycles access was blocked +system.cpu0.dcache.tags.replacements 1288020 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.688069 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10644807 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1288532 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.261189 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.688069 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987672 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.987672 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6550900 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6550900 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3728429 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3728429 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165070 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 165070 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189835 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189835 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10279329 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10279329 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10279329 # number of overall hits +system.cpu0.dcache.overall_hits::total 10279329 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1597921 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1597921 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1777729 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1777729 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20672 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20672 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2669 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2669 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3375650 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3375650 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3375650 # number of overall misses +system.cpu0.dcache.overall_misses::total 3375650 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40268021859 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40268021859 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79880065793 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79880065793 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301767496 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 301767496 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20162915 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20162915 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 120148087652 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 120148087652 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 120148087652 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 120148087652 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8148821 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8148821 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5506158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5506158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185742 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 185742 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13654979 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13654979 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13654979 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13654979 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196092 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.196092 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322862 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.322862 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111294 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111294 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013865 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013865 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247210 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.247210 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247210 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.247210 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25200.258247 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25200.258247 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44933.769879 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44933.769879 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14597.885836 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14597.885836 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7554.482952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7554.482952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35592.578511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35592.578511 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2948269 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 52342 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 54.983539 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 120 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 56.327022 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 746874 # number of writebacks -system.cpu0.dcache.writebacks::total 746874 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 575080 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 575080 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465992 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1465992 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4461 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4461 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2041072 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2041072 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2041072 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2041072 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 998425 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 998425 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272155 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272155 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3020 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3020 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1270580 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1270580 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1270580 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1270580 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26454916051 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26454916051 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11388682739 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11388682739 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172348003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172348003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 16164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 16164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 37843598790 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 37843598790 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 37843598790 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 37843598790 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459347502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459347502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2156087498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2156087498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3615435000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3615435000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085876 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085876 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095216 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095216 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26496.648272 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26496.648272 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41846.310885 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41846.310885 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11059.291774 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11059.291774 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5352.317881 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5352.317881 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 760237 # number of writebacks +system.cpu0.dcache.writebacks::total 760237 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 590547 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 590547 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1499620 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1499620 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4585 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4585 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2090167 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2090167 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2090167 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2090167 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007374 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1007374 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 278109 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 278109 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2668 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2668 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1285483 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1285483 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1285483 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1285483 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26624787726 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26624787726 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11708735082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11708735082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178034254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178034254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14826085 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14826085 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38333522808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38333522808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38333522808 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38333522808 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465041000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465041000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2164117998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2164117998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3629158998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3629158998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123622 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123622 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050509 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050509 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013859 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013859 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094140 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094140 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26429.893690 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26429.893690 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42101.244771 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42101.244771 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11066.964257 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11066.964257 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5557.003373 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5557.003373 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1479,35 +1482,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2604526 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2153409 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 75247 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1513707 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 876072 # Number of BTB hits +system.cpu1.branchPred.lookups 2340238 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1946356 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 62804 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1358794 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 776922 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.875930 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 179167 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7740 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.177320 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 157214 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 6628 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1932131 # DTB read hits -system.cpu1.dtb.read_misses 10237 # DTB read misses -system.cpu1.dtb.read_acv 25 # DTB read access violations -system.cpu1.dtb.read_accesses 320506 # DTB read accesses -system.cpu1.dtb.write_hits 1251341 # DTB write hits -system.cpu1.dtb.write_misses 1962 # DTB write misses -system.cpu1.dtb.write_acv 65 # DTB write access violations -system.cpu1.dtb.write_accesses 130037 # DTB write accesses -system.cpu1.dtb.data_hits 3183472 # DTB hits -system.cpu1.dtb.data_misses 12199 # DTB misses -system.cpu1.dtb.data_acv 90 # DTB access violations -system.cpu1.dtb.data_accesses 450543 # DTB accesses -system.cpu1.itb.fetch_hits 430844 # ITB hits -system.cpu1.itb.fetch_misses 6753 # ITB misses -system.cpu1.itb.fetch_acv 212 # ITB acv -system.cpu1.itb.fetch_accesses 437597 # ITB accesses +system.cpu1.dtb.read_hits 1733483 # DTB read hits +system.cpu1.dtb.read_misses 9288 # DTB read misses +system.cpu1.dtb.read_acv 9 # DTB read access violations +system.cpu1.dtb.read_accesses 276268 # DTB read accesses +system.cpu1.dtb.write_hits 1103623 # DTB write hits +system.cpu1.dtb.write_misses 1818 # DTB write misses +system.cpu1.dtb.write_acv 38 # DTB write access violations +system.cpu1.dtb.write_accesses 104203 # DTB write accesses +system.cpu1.dtb.data_hits 2837106 # DTB hits +system.cpu1.dtb.data_misses 11106 # DTB misses +system.cpu1.dtb.data_acv 47 # DTB access violations +system.cpu1.dtb.data_accesses 380471 # DTB accesses +system.cpu1.itb.fetch_hits 375000 # ITB hits +system.cpu1.itb.fetch_misses 5508 # ITB misses +system.cpu1.itb.fetch_acv 148 # ITB acv +system.cpu1.itb.fetch_accesses 380508 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1520,508 +1523,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 15794943 # number of cpu cycles simulated +system.cpu1.numCycles 14113255 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6044274 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12313553 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2604526 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1055239 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2204838 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 395965 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6209579 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26246 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62195 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 53260 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1481011 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50405 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14852690 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.829045 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.204427 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5353605 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 10974333 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2340238 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 934136 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1960258 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 346091 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 5695969 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 25528 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 53832 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 54284 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1309338 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 41617 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 13363974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.821188 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.197770 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12647852 85.16% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 141564 0.95% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 235652 1.59% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 175889 1.18% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 303768 2.05% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 119285 0.80% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 129403 0.87% 92.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 209113 1.41% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 890164 5.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11403716 85.33% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 124023 0.93% 86.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 213549 1.60% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 153465 1.15% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 264643 1.98% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 105166 0.79% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 115273 0.86% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 186335 1.39% 94.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 797804 5.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14852690 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164896 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.779588 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5971093 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6462269 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2062064 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 112088 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 245175 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 113398 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7205 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12081319 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21458 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 245175 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6179272 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 425366 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5395094 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1962879 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 644902 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11197795 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 57093 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 157527 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7361429 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13363056 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13213666 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 149390 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6300177 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1061252 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 451071 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 42573 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1993362 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2041709 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1326014 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 180090 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 100258 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9822573 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 491625 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9565946 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29815 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1410113 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 705464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352077 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14852690 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644055 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.318534 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13363974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.165818 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.777590 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5293087 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 5922521 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1836128 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 97560 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 214677 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 97799 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5876 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10774764 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 17225 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 214677 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5481600 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 352411 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4990949 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1741665 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 582670 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 9967248 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 54670 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 132191 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 6553947 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 11886744 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 11748684 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 138060 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5636582 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 917365 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 415822 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 37623 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1815514 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1827244 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1170543 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 163690 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 89610 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8737156 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 452580 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8518295 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27160 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1245229 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 620627 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 325893 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13363974 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.637407 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.312561 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10648951 71.70% 71.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1930050 12.99% 84.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 818337 5.51% 90.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 551122 3.71% 93.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 476075 3.21% 97.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 213789 1.44% 98.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 136394 0.92% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 69529 0.47% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8443 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9608930 71.90% 71.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1736625 12.99% 84.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 727835 5.45% 90.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 487296 3.65% 93.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 421265 3.15% 97.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 191133 1.43% 98.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 120060 0.90% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 63613 0.48% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 7217 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14852690 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13363974 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3207 1.63% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 106178 53.97% 55.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 87357 44.40% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2685 1.53% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 94663 54.03% 55.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 77863 44.44% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5966011 62.37% 62.40% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16243 0.17% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10971 0.11% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2021702 21.13% 83.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1274955 13.33% 97.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 270775 2.83% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5299330 62.21% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14840 0.17% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10732 0.13% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1812344 21.28% 83.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1125275 13.21% 97.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 250497 2.94% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9565946 # Type of FU issued -system.cpu1.iq.rate 0.605633 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 196742 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020567 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 33995446 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11620704 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9288457 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 215693 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 105258 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 101999 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9646700 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 112462 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 92569 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8518295 # Type of FU issued +system.cpu1.iq.rate 0.603567 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 175211 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020569 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 30403276 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10338814 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8274405 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 199659 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 97460 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 94461 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8585899 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 104089 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 83773 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 282729 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1535 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1711 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 123624 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 247116 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1193 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1397 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 111584 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 323 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 14236 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 14213 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 245175 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 256542 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 43339 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10829040 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 147658 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2041709 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1326014 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 444647 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 36382 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1620 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1711 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 33953 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 99696 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 133649 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9473535 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1949759 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 92411 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 214677 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 210872 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 38123 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9643840 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 131515 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1827244 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1170543 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 410565 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 32525 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1557 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1397 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28168 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 87904 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 116072 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8443529 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1749257 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 74766 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 514842 # number of nop insts executed -system.cpu1.iew.exec_refs 3209162 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1413585 # Number of branches executed -system.cpu1.iew.exec_stores 1259403 # Number of stores executed -system.cpu1.iew.exec_rate 0.599783 # Inst execution rate -system.cpu1.iew.wb_sent 9417236 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9390456 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4401006 # num instructions producing a value -system.cpu1.iew.wb_consumers 6190652 # num instructions consuming a value +system.cpu1.iew.exec_nop 454104 # number of nop insts executed +system.cpu1.iew.exec_refs 2860324 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1252098 # Number of branches executed +system.cpu1.iew.exec_stores 1111067 # Number of stores executed +system.cpu1.iew.exec_rate 0.598269 # Inst execution rate +system.cpu1.iew.wb_sent 8394111 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8368866 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3943473 # num instructions producing a value +system.cpu1.iew.wb_consumers 5568899 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.594523 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710912 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.592979 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708124 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1449457 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 139548 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 125475 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14607515 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.636458 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.578813 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1277535 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126687 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 110026 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13149297 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.631052 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.572436 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11126487 76.17% 76.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1625013 11.12% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 604004 4.13% 91.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 371910 2.55% 93.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 263907 1.81% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 102565 0.70% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 109537 0.75% 97.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 110097 0.75% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 293995 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10035587 76.32% 76.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1461499 11.11% 87.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 536339 4.08% 91.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 329312 2.50% 94.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 237007 1.80% 95.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 91157 0.69% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 98866 0.75% 97.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 97470 0.74% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 262060 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14607515 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9297065 # Number of instructions committed -system.cpu1.commit.committedOps 9297065 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13149297 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8297892 # Number of instructions committed +system.cpu1.commit.committedOps 8297892 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2961370 # Number of memory references committed -system.cpu1.commit.loads 1758980 # Number of loads committed -system.cpu1.commit.membars 44792 # Number of memory barriers committed -system.cpu1.commit.branches 1328076 # Number of branches committed -system.cpu1.commit.fp_insts 100787 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8610735 # Number of committed integer instructions. -system.cpu1.commit.function_calls 147103 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 293995 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2639087 # Number of memory references committed +system.cpu1.commit.loads 1580128 # Number of loads committed +system.cpu1.commit.membars 40354 # Number of memory barriers committed +system.cpu1.commit.branches 1179945 # Number of branches committed +system.cpu1.commit.fp_insts 93281 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7680197 # Number of committed integer instructions. +system.cpu1.commit.function_calls 130349 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 262060 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 24970897 # The number of ROB reads -system.cpu1.rob.rob_writes 21736671 # The number of ROB writes -system.cpu1.timesIdled 134601 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 942253 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3790981004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8842996 # Number of Instructions Simulated -system.cpu1.committedOps 8842996 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8842996 # Number of Instructions Simulated -system.cpu1.cpi 1.786153 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.786153 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.559862 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.559862 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12205153 # number of integer regfile reads -system.cpu1.int_regfile_writes 6674473 # number of integer regfile writes -system.cpu1.fp_regfile_reads 55471 # number of floating regfile reads -system.cpu1.fp_regfile_writes 55305 # number of floating regfile writes -system.cpu1.misc_regfile_reads 527113 # number of misc regfile reads -system.cpu1.misc_regfile_writes 218222 # number of misc regfile writes -system.cpu1.icache.replacements 225540 # number of replacements -system.cpu1.icache.tagsinuse 470.721925 # Cycle average of tags in use -system.cpu1.icache.total_refs 1246547 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 226052 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.514426 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1877726350000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.721925 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919379 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919379 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1246547 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1246547 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1246547 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1246547 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1246547 # number of overall hits -system.cpu1.icache.overall_hits::total 1246547 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 234464 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 234464 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 234464 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 234464 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 234464 # number of overall misses -system.cpu1.icache.overall_misses::total 234464 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3166624000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3166624000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3166624000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3166624000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3166624000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3166624000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1481011 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1481011 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1481011 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1481011 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1481011 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1481011 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158313 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.158313 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158313 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.158313 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158313 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.158313 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.800464 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.800464 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13505.800464 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13505.800464 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked +system.cpu1.rob.rob_reads 22380631 # The number of ROB reads +system.cpu1.rob.rob_writes 19363835 # The number of ROB writes +system.cpu1.timesIdled 119058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 749281 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3793736462 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 7893138 # Number of Instructions Simulated +system.cpu1.committedOps 7893138 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 7893138 # Number of Instructions Simulated +system.cpu1.cpi 1.788041 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.788041 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.559271 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.559271 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 10874027 # number of integer regfile reads +system.cpu1.int_regfile_writes 5958512 # number of integer regfile writes +system.cpu1.fp_regfile_reads 51748 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51512 # number of floating regfile writes +system.cpu1.misc_regfile_reads 484557 # number of misc regfile reads +system.cpu1.misc_regfile_writes 198633 # number of misc regfile writes +system.cpu1.icache.tags.replacements 198364 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.505741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1103940 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 198874 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.550952 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1894556454000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.505741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918957 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.918957 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1103940 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1103940 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1103940 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1103940 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1103940 # number of overall hits +system.cpu1.icache.overall_hits::total 1103940 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 205398 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 205398 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 205398 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 205398 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 205398 # number of overall misses +system.cpu1.icache.overall_misses::total 205398 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2726676790 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2726676790 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2726676790 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2726676790 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2726676790 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2726676790 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1309338 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1309338 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1309338 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1309338 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1309338 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1309338 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.156872 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.156872 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.156872 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.156872 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.156872 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.156872 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13275.089290 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13275.089290 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13275.089290 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13275.089290 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.777778 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.166667 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8347 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8347 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8347 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8347 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8347 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8347 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 226117 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 226117 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 226117 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 226117 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 226117 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 226117 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2628094387 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2628094387 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2628094387 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2628094387 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2628094387 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2628094387 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152677 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.152677 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.152677 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11622.719154 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6463 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6463 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6463 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6463 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6463 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6463 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 198935 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 198935 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 198935 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 198935 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 198935 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 198935 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2267895657 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2267895657 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2267895657 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2267895657 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2267895657 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2267895657 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151936 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.151936 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.151936 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11400.184266 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 108851 # number of replacements -system.cpu1.dcache.tagsinuse 491.736427 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2599646 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 109251 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 23.795169 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 43858959000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.736427 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.960423 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.960423 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1587502 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1587502 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 943251 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 943251 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32579 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 32579 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 31559 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 31559 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2530753 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2530753 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2530753 # number of overall hits -system.cpu1.dcache.overall_hits::total 2530753 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 209244 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 209244 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 218379 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 218379 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5510 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5510 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3216 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3216 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 427623 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 427623 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 427623 # number of overall misses -system.cpu1.dcache.overall_misses::total 427623 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2938034500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2938034500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7305073698 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7305073698 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 55149000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 55149000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 23385500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 23385500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10243108198 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10243108198 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10243108198 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10243108198 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1796746 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1796746 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1161630 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1161630 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38089 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 38089 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 34775 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 34775 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2958376 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2958376 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2958376 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2958376 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.116457 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.116457 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187994 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187994 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.144661 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.144661 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092480 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092480 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.144547 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.144547 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.144547 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.144547 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14041.188756 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14041.188756 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33451.356119 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33451.356119 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10008.892922 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10008.892922 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7271.610697 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7271.610697 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23953.595101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23953.595101 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 227083 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 93782 # number of replacements +system.cpu1.dcache.tags.tagsinuse 490.645175 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2322631 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 94098 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.683107 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.645175 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958291 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.958291 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1425624 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1425624 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 844173 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 844173 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 28774 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 28774 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27671 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 27671 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2269797 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2269797 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2269797 # number of overall hits +system.cpu1.dcache.overall_hits::total 2269797 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 184725 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 184725 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178548 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178548 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4789 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4789 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2902 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2902 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 363273 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 363273 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 363273 # number of overall misses +system.cpu1.dcache.overall_misses::total 363273 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2584165220 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2584165220 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5809552721 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5809552721 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46614997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46614997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21574947 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 21574947 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8393717941 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8393717941 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8393717941 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8393717941 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1610349 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1610349 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1022721 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1022721 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33563 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 33563 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30573 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 30573 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2633070 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2633070 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2633070 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2633070 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114711 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114711 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174581 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.174581 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142687 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142687 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.137966 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.137966 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.137966 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.137966 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.255488 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.255488 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32537.764192 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32537.764192 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9733.764251 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9733.764251 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7434.509649 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7434.509649 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23105.812821 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23105.812821 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 188355 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 4054 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3483 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.014554 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 54.078381 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 72569 # number of writebacks -system.cpu1.dcache.writebacks::total 72569 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129770 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 129770 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 179212 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 179212 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 594 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 594 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 308982 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 308982 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 308982 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 308982 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79474 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 79474 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39167 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 39167 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4916 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4916 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3216 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3216 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 118641 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 118641 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 118641 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 118641 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 893939249 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 893939249 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081571527 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081571527 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37210004 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37210004 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16953500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16953500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1975510776 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1975510776 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1975510776 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1975510776 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23615501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23615501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 628297501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 628297501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 651913002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 651913002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044232 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044232 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.129066 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.129066 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092480 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092480 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040103 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040103 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11248.197511 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11248.197511 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27614.357163 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27614.357163 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7569.162734 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7569.162734 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5271.610697 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5271.610697 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 60866 # number of writebacks +system.cpu1.dcache.writebacks::total 60866 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 114750 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 114750 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 145883 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 145883 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 398 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 398 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 260633 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 260633 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 260633 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 260633 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69975 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 69975 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32665 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 32665 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4391 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4391 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 102640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 102640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 102640 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 102640 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 781048941 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 781048941 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 869596715 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 869596715 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32787753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32787753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15774053 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15774053 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1650645656 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1650645656 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1650645656 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1650645656 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18096000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18096000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600498502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 600498502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 618594502 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 618594502 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031939 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031939 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130829 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130829 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094855 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094855 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038981 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038981 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11161.828382 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11161.828382 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26621.665850 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26621.665850 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7467.035527 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7467.035527 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5439.328621 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5439.328621 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2030,170 +2033,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6605 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 182638 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64421 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.21% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 210 0.13% 41.93% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92368 58.07% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 159055 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63463 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.49% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 210 0.16% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63253 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128982 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863089530500 97.87% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64074500 0.00% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567937500 0.03% 97.90% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 100797000 0.01% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39879064000 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903701403500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.985129 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6628 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 186556 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65870 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.19% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 193 0.12% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94141 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162260 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64876 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.46% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 193 0.15% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64684 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131809 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863192383000 97.84% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64528500 0.00% 97.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571927000 0.03% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 92721000 0.00% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40351323000 2.12% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904272882500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984910 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684793 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810927 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.687097 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812332 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 302 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3478 2.07% 2.26% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 152288 90.83% 93.12% # number of callpals executed -system.cpu0.kern.callpal::rdps 6536 3.90% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4500 2.68% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.21% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167660 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7044 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches +system.cpu0.kern.callpal::wripir 275 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3568 2.09% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155408 90.82% 93.10% # number of callpals executed +system.cpu0.kern.callpal::rdps 6655 3.89% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4603 2.69% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 171120 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7202 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1285 -system.cpu0.kern.mode_good::user 1286 +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.182425 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.190225 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.308643 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901692288000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2009107500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.319725 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1902171924000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2100950500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3479 # number of times the context was actually changed +system.cpu0.kern.swap_context 3569 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 57331 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18009 36.73% 36.73% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.92% 40.65% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 302 0.62% 41.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28797 58.73% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49032 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17590 47.41% 47.41% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 5.19% 52.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 302 0.81% 53.41% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17288 46.59% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37104 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1873168497000 98.41% 98.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531845000 0.03% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 136792000 0.01% 98.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29552054000 1.55% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903389188000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976734 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2405 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 53020 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16452 36.11% 36.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 4.22% 40.33% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 275 0.60% 40.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26914 59.07% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45564 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16069 47.18% 47.18% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 5.65% 52.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 275 0.81% 53.63% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15794 46.37% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34061 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1873583378500 98.41% 98.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531505500 0.03% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 123925000 0.01% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29687237000 1.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903926046000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976720 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.600340 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.756730 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.586832 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.747542 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 210 0.41% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wripir 193 0.41% 0.41% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1165 2.30% 2.72% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.73% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.75% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43701 86.29% 89.04% # number of callpals executed -system.cpu1.kern.callpal::rdps 2223 4.39% 93.43% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.43% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.44% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.44% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.44% # number of callpals executed -system.cpu1.kern.callpal::rti 3104 6.13% 99.57% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.34% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1035 2.21% 2.63% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.63% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.65% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40418 86.22% 88.87% # number of callpals executed +system.cpu1.kern.callpal::rdps 2100 4.48% 93.35% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.35% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.36% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.36% # number of callpals executed +system.cpu1.kern.callpal::rti 2947 6.29% 99.65% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.26% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 50643 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1414 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2447 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 685 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 226 -system.cpu1.kern.mode_switch_good::kernel 0.484441 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 46877 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1217 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2392 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 567 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 200 +system.cpu1.kern.mode_switch_good::kernel 0.465900 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.092358 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.317130 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4654463000 0.24% 0.24% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 807268500 0.04% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1897916233000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1166 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.083612 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.285211 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3949860500 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 686482000 0.04% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1898967291500 99.76% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1036 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 6711c23df..59daab93c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,124 +1,124 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859220 # Number of seconds simulated -sim_ticks 1859219766000 # Number of ticks simulated -final_tick 1859219766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860201 # Number of seconds simulated +sim_ticks 1860200687500 # Number of ticks simulated +final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91264 # Simulator instruction rate (inst/s) -host_op_rate 91264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3202546943 # Simulator tick rate (ticks/s) -host_mem_usage 310256 # Number of bytes of host memory used -host_seconds 580.54 # Real time elapsed on the host -sim_insts 52982774 # Number of instructions simulated -sim_ops 52982774 # Number of ops (including micro ops) simulated +host_inst_rate 112423 # Simulator instruction rate (inst/s) +host_op_rate 112423 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3947369845 # Simulator tick rate (ticks/s) +host_mem_usage 310252 # Number of bytes of host memory used +host_seconds 471.25 # Real time elapsed on the host +sim_insts 52979577 # Number of instructions simulated +sim_ops 52979577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879296 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28495424 # Number of bytes read from this memory +system.physmem.bytes_read::total 28495552 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7515968 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515968 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388739 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445241 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13381510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1426560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15326550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4042229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4042229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4042229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13381510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1426560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19368779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445241 # Total number of read requests seen -system.physmem.writeReqs 117428 # Total number of write requests seen -system.physmem.cpureqs 562841 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28495424 # Total number of bytes read from memory -system.physmem.bytesWritten 7515392 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28495424 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7515392 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28436 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27802 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27225 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27536 # Track reads on a per bank basis +system.physmem.num_reads::total 445243 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117437 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117437 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15318536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040407 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040407 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445243 # Total number of read requests seen +system.physmem.writeReqs 117437 # Total number of write requests seen +system.physmem.cpureqs 562856 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28495552 # Total number of bytes read from memory +system.physmem.bytesWritten 7515968 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 55 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27265 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27330 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27528 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28320 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7499 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7517 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6762 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6683 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7320 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8048 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7826 # Track writes on a per bank basis +system.physmem.perBankRdReqs::13 28243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28321 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7923 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7495 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7495 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6687 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6715 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7135 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7403 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7111 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7888 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8047 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7823 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1859214351000 # Total gap between requests +system.physmem.totGap 1860195209000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445241 # Categorize read packet sizes +system.physmem.readPktSize::6 445243 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117428 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 330939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117437 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 330882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3039 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -129,10 +129,10 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see @@ -141,235 +141,234 @@ system.physmem.wrQLenPdf::9 5106 # Wh system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 960.941176 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 233.799958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2437.428145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 12972 34.62% 34.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5555 14.83% 49.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3417 9.12% 58.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2277 6.08% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1679 4.48% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1428 3.81% 72.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 991 2.64% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 802 2.14% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 632 1.69% 79.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 550 1.47% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 599 1.60% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 534 1.43% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 276 0.74% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 243 0.65% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 192 0.51% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 257 0.69% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 103 0.27% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 109 0.29% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 145 0.39% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 226 0.60% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 117 0.31% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 450 1.20% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 603 1.61% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 73 0.19% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 37 0.10% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 34 0.09% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 78 0.21% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 30 0.08% 92.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 11 0.03% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 8 0.02% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 42 0.11% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 24 0.06% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 2 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.02% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 2 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2434 6.50% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 3 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 955.810131 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 232.523406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2430.690638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13031 34.59% 34.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5648 14.99% 49.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3558 9.45% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2240 5.95% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1644 4.36% 69.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1436 3.81% 73.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 989 2.63% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 804 2.13% 77.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 676 1.79% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 516 1.37% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 573 1.52% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 541 1.44% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 276 0.73% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 231 0.61% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 160 0.42% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 263 0.70% 86.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 87 0.23% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 129 0.34% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 153 0.41% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 242 0.64% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 113 0.30% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 462 1.23% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 590 1.57% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 81 0.22% 91.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 28 0.07% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 16 0.04% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 89 0.24% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 26 0.07% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 8 0.02% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 14 0.04% 92.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 43 0.11% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 28 0.07% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 18 0.05% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 7 0.02% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 5 0.01% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 6 0.02% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.01% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.01% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 2 0.01% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 3 0.01% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.01% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.01% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.01% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.01% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 5 0.01% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2432 6.46% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 3 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 13 0.03% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 7 0.02% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 2 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17283 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37468 # Bytes accessed per row activation -system.physmem.totQLat 6065400750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13430024500 # Sum of mem lat for all requests -system.physmem.totBusLat 2225905000 # Total cycles spent in databus access -system.physmem.totBankLat 5138718750 # Total cycles spent in bank access -system.physmem.avgQLat 13624.57 # Average queueing delay per request -system.physmem.avgBankLat 11542.99 # Average bank access latency per request +system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 5 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37668 # Bytes accessed per row activation +system.physmem.totQLat 6113897250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13475242250 # Sum of mem lat for all requests +system.physmem.totBusLat 2225940000 # Total cycles spent in databus access +system.physmem.totBankLat 5135405000 # Total cycles spent in bank access +system.physmem.avgQLat 13733.29 # Average queueing delay per request +system.physmem.avgBankLat 11535.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30167.56 # Average memory access latency -system.physmem.avgRdBW 15.33 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30268.66 # Average memory access latency +system.physmem.avgRdBW 15.32 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.33 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.32 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.93 # Average write queue length over time -system.physmem.readRowHits 430163 # Number of row buffer hits during reads -system.physmem.writeRowHits 94965 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes -system.physmem.avgGap 3304277.21 # Average gap between requests -system.membus.throughput 19411663 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296022 # Transaction distribution -system.membus.trans_dist::ReadResp 295937 # Transaction distribution +system.physmem.avgWrQLen 9.67 # Average write queue length over time +system.physmem.readRowHits 430049 # Number of row buffer hits during reads +system.physmem.writeRowHits 94886 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes +system.physmem.avgGap 3305955.80 # Average gap between requests +system.membus.throughput 19401806 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295958 # Transaction distribution +system.membus.trans_dist::ReadResp 295878 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117428 # Transaction distribution -system.membus.trans_dist::UpgradeReq 173 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 156790 # Transaction distribution -system.membus.trans_dist::ReadExResp 156790 # Transaction distribution -system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.trans_dist::Writeback 117437 # Transaction distribution +system.membus.trans_dist::UpgradeReq 178 # Transaction distribution +system.membus.trans_dist::UpgradeResp 178 # Transaction distribution +system.membus.trans_dist::ReadExReq 156851 # Transaction distribution +system.membus.trans_dist::ReadExResp 156851 # Transaction distribution +system.membus.trans_dist::BadAddressError 80 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884153 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1008811 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1008832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745908 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36010816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36054964 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36054964 # Total data (bytes) +system.membus.tot_pkt_size::system.physmem.port 36011520 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36055668 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29876000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29849000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1541728249 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1552225748 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 108500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 97500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3763624798 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3765192546 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376221741 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.261712 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709369770000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.261712 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078857 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078857 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -378,14 +377,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10471007269 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10471007269 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10492350152 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10492350152 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10492350152 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10492350152 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21345883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21345883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10482445518 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10482445518 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10503791401 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10503791401 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10503791401 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10503791401 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -402,19 +401,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251997.672049 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251997.672049 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 251464.353553 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 251464.353553 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 273612 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123386.606936 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123386.606936 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252272.947584 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 252272.947584 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 251738.559641 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 251738.559641 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 274094 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27136 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27191 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.082989 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.080321 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -428,14 +427,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8309607278 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8309607278 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8321953411 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8321953411 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8321953411 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8321953411 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12348383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12348383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8320362536 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8320362536 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8332710919 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8332710919 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8332710919 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8332710919 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -444,14 +443,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199980.922170 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199980.922170 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71377.936416 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71377.936416 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200239.760685 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 200239.760685 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -465,35 +464,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13839600 # Number of BP lookups -system.cpu.branchPred.condPredicted 11609173 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399191 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9510547 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5805743 # Number of BTB hits +system.cpu.branchPred.lookups 13856452 # Number of BP lookups +system.cpu.branchPred.condPredicted 11625252 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 398822 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9666189 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5826807 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.045311 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 906368 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39168 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 60.280292 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 904750 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39047 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9923550 # DTB read hits -system.cpu.dtb.read_misses 41274 # DTB read misses -system.cpu.dtb.read_acv 543 # DTB read access violations -system.cpu.dtb.read_accesses 941562 # DTB read accesses -system.cpu.dtb.write_hits 6598688 # DTB write hits -system.cpu.dtb.write_misses 10641 # DTB write misses -system.cpu.dtb.write_acv 411 # DTB write access violations -system.cpu.dtb.write_accesses 338433 # DTB write accesses -system.cpu.dtb.data_hits 16522238 # DTB hits -system.cpu.dtb.data_misses 51915 # DTB misses -system.cpu.dtb.data_acv 954 # DTB access violations -system.cpu.dtb.data_accesses 1279995 # DTB accesses -system.cpu.itb.fetch_hits 1308614 # ITB hits -system.cpu.itb.fetch_misses 36742 # ITB misses -system.cpu.itb.fetch_acv 1058 # ITB acv -system.cpu.itb.fetch_accesses 1345356 # ITB accesses +system.cpu.dtb.read_hits 9922890 # DTB read hits +system.cpu.dtb.read_misses 41426 # DTB read misses +system.cpu.dtb.read_acv 537 # DTB read access violations +system.cpu.dtb.read_accesses 941977 # DTB read accesses +system.cpu.dtb.write_hits 6601888 # DTB write hits +system.cpu.dtb.write_misses 10414 # DTB write misses +system.cpu.dtb.write_acv 409 # DTB write access violations +system.cpu.dtb.write_accesses 338180 # DTB write accesses +system.cpu.dtb.data_hits 16524778 # DTB hits +system.cpu.dtb.data_misses 51840 # DTB misses +system.cpu.dtb.data_acv 946 # DTB access violations +system.cpu.dtb.data_accesses 1280157 # DTB accesses +system.cpu.itb.fetch_hits 1306702 # ITB hits +system.cpu.itb.fetch_misses 37996 # ITB misses +system.cpu.itb.fetch_acv 1078 # ITB acv +system.cpu.itb.fetch_accesses 1344698 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -506,268 +505,268 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 120145786 # number of cpu cycles simulated +system.cpu.numCycles 120724090 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28059248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70722559 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13839600 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6712111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13258692 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1994060 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38168658 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32286 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254324 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364483 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8570347 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266679 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81425482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.868556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28054756 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70765698 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13856452 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6731557 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13261846 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1996538 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38180961 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33921 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253688 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 362223 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8553305 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264520 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81438491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.868947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211995 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68166790 83.72% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854823 1.05% 84.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1706158 2.10% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 819634 1.01% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2757548 3.39% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 561946 0.69% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 649151 0.80% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1013766 1.25% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4895666 6.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68176645 83.72% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 854498 1.05% 84.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1700203 2.09% 86.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 823613 1.01% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2757448 3.39% 91.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 566024 0.70% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 644448 0.79% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011541 1.24% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4904071 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81425482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115190 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.588640 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29284437 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37811275 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12102091 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 982484 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1245194 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 583690 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42726 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69419384 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129751 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1245194 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30419678 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14066203 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19996824 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11337239 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4360342 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65632842 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7067 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 503743 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1590486 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43821413 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79676034 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79196502 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479532 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38182467 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5638938 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682867 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239802 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12252220 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10440672 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6902467 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1316833 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 861587 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58171642 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2051698 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56802904 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 100593 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6885118 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3554028 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1390714 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81425482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359574 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81438491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114778 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.586177 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29237679 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37865551 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12126902 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 959687 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1248671 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585551 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42601 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69445978 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129475 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1248671 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30384491 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14146796 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20012830 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11334710 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4310991 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65667162 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7173 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505660 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79230933 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479363 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240064 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12233478 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10440283 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6900737 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1318689 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 855517 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58206235 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050936 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56823082 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 100209 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6920159 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3549975 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389936 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81438491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697742 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56719527 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10865996 13.34% 83.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5212450 6.40% 89.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3349939 4.11% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2634366 3.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1460723 1.79% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 752656 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 333424 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96401 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56732960 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10881055 13.36% 83.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5157432 6.33% 89.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3394617 4.17% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2629816 3.23% 96.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1458992 1.79% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 753848 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332168 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 97603 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81425482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81438491 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 93250 11.76% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372953 47.03% 58.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326761 41.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91824 11.60% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372747 47.08% 58.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 327090 41.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38720727 68.17% 68.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61725 0.11% 68.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10357561 18.23% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6677285 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38740473 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61726 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10354642 18.22% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6680643 11.76% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949069 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56802904 # Type of FU issued -system.cpu.iq.rate 0.472783 # Inst issue rate -system.cpu.iq.fu_busy_cnt 792964 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013960 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195231977 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66785301 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55558093 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692869 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336906 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327947 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57227049 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361533 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597916 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56823082 # Type of FU issued +system.cpu.iq.rate 0.470686 # Inst issue rate +system.cpu.iq.fu_busy_cnt 791661 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013932 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195283781 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66854445 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55585028 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692743 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336682 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327940 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57245966 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361491 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598566 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1347952 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3269 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524235 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1347977 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14180 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 522824 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17914 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 199705 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17906 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 181081 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1245194 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10207267 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 699182 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63757422 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 685568 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10440672 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6902467 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1806514 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512114 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18348 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 200766 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410779 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 611545 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56334870 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9992999 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 468033 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1248671 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10233873 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 701956 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63782733 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684936 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10440283 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6900737 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1806230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512408 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17686 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14180 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202063 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410564 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 612627 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56356224 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9992501 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466857 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3534082 # number of nop insts executed -system.cpu.iew.exec_refs 16617553 # number of memory reference insts executed -system.cpu.iew.exec_branches 8923539 # Number of branches executed -system.cpu.iew.exec_stores 6624554 # Number of stores executed -system.cpu.iew.exec_rate 0.468888 # Inst execution rate -system.cpu.iew.wb_sent 55999832 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55886040 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27701007 # num instructions producing a value -system.cpu.iew.wb_consumers 37529982 # num instructions consuming a value +system.cpu.iew.exec_nop 3525562 # number of nop insts executed +system.cpu.iew.exec_refs 16620030 # number of memory reference insts executed +system.cpu.iew.exec_branches 8925380 # Number of branches executed +system.cpu.iew.exec_stores 6627529 # Number of stores executed +system.cpu.iew.exec_rate 0.466818 # Inst execution rate +system.cpu.iew.wb_sent 56027730 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55912968 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27713014 # num instructions producing a value +system.cpu.iew.wb_consumers 37524402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.465152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738103 # average fanout of values written-back +system.cpu.iew.wb_rate 0.463147 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7465540 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660984 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 567902 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80180288 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700591 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629829 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7495675 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661000 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 567647 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80189820 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700468 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629642 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59372363 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8630775 10.76% 84.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4656269 5.81% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2498281 3.12% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1510890 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 609736 0.76% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522635 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 527296 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1852043 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59377156 74.05% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8657171 10.80% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4615541 5.76% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2519398 3.14% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1507686 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611065 0.76% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 523948 0.65% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 528681 0.66% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1849174 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80180288 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56173622 # Number of instructions committed -system.cpu.commit.committedOps 56173622 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80189820 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170363 # Number of instructions committed +system.cpu.commit.committedOps 56170363 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470952 # Number of memory references committed -system.cpu.commit.loads 9092720 # Number of loads committed -system.cpu.commit.membars 226359 # Number of memory barriers committed -system.cpu.commit.branches 8440448 # Number of branches committed +system.cpu.commit.refs 15470219 # Number of memory references committed +system.cpu.commit.loads 9092306 # Number of loads committed +system.cpu.commit.membars 226376 # Number of memory barriers committed +system.cpu.commit.branches 8439998 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52023156 # Number of committed integer instructions. -system.cpu.commit.function_calls 740622 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1852043 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52019946 # Number of committed integer instructions. +system.cpu.commit.function_calls 740578 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1849174 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141717845 # The number of ROB reads -system.cpu.rob.rob_writes 128525319 # The number of ROB writes -system.cpu.timesIdled 1192872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38720304 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598287306 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52982774 # Number of Instructions Simulated -system.cpu.committedOps 52982774 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52982774 # Number of Instructions Simulated -system.cpu.cpi 2.267639 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.267639 # CPI: Total CPI of All Threads -system.cpu.ipc 0.440987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.440987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73877727 # number of integer regfile reads -system.cpu.int_regfile_writes 40299404 # number of integer regfile writes -system.cpu.fp_regfile_reads 166073 # number of floating regfile reads -system.cpu.fp_regfile_writes 167447 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985193 # number of misc regfile reads +system.cpu.rob.rob_reads 141757103 # The number of ROB reads +system.cpu.rob.rob_writes 128582546 # The number of ROB writes +system.cpu.timesIdled 1193264 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 39285599 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599670846 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979577 # Number of Instructions Simulated +system.cpu.committedOps 52979577 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979577 # Number of Instructions Simulated +system.cpu.cpi 2.278691 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.278691 # CPI: Total CPI of All Threads +system.cpu.ipc 0.438848 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.438848 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73899188 # number of integer regfile reads +system.cpu.int_regfile_writes 40322867 # number of integer regfile writes +system.cpu.fp_regfile_reads 166085 # number of floating regfile reads +system.cpu.fp_regfile_writes 167427 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985758 # number of misc regfile reads system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -800,7 +799,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1455318 # Throughput (bytes/s) +system.iobus.throughput 1454551 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51150 # Transaction distribution @@ -886,233 +885,225 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378262152 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378268160 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43098759 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 112025274 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2118762 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2118660 # Transaction distribution +system.cpu.toL2Bus.throughput 111927083 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2117675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2117578 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840831 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 68 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3678751 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 5699466 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64659008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143612852 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 208271860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208261812 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17792 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480878498 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2019865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3677460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 5697325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64631872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143567348 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 208199220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1516366019 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2115023448 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.replacements 1009685 # number of replacements -system.cpu.icache.tagsinuse 509.751691 # Cycle average of tags in use -system.cpu.icache.total_refs 7503411 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1010193 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.427700 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 25536785000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.751691 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995609 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995609 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7503412 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7503412 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7503412 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7503412 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7503412 # number of overall hits -system.cpu.icache.overall_hits::total 7503412 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1066934 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066934 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1066934 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066934 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1066934 # number of overall misses -system.cpu.icache.overall_misses::total 1066934 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15003433992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15003433992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15003433992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15003433992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15003433992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15003433992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8570346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8570346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8570346 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8570346 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8570346 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8570346 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124491 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124491 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124491 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124491 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124491 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124491 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14062.195030 # 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average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1202,161 +1185,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1401615 # number of replacements -system.cpu.dcache.tagsinuse 511.994565 # Cycle average of tags in use -system.cpu.dcache.total_refs 11806786 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1402127 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.420625 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25214000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994565 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7200855 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7200855 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204221 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204221 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 185946 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 185946 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215517 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15152920 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15152920 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15152920 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15152920 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200341 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200341 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316165 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316165 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109002 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109002 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247335 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247335 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247335 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247335 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21903.622225 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21903.622225 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38964.588594 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38964.588594 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14152.848602 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14152.848602 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30752.145439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30752.145439 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2955693 # number of cycles access was blocked +system.cpu.dcache.tags.replacements 1401048 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203713 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186169 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186169 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11406177 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11406177 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11406177 # number of overall hits +system.cpu.dcache.overall_hits::total 11406177 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1806828 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1806828 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943975 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943975 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22707 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22707 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3750803 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3750803 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3750803 # number of overall misses +system.cpu.dcache.overall_misses::total 3750803 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39803546178 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39803546178 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76325479834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76325479834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321955499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 321955499 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 116129026012 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 116129026012 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 116129026012 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 116129026012 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9009292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9009292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208876 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208876 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215522 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215522 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15156980 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15156980 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15156980 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15156980 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200552 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200552 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316212 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316212 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108710 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108710 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247464 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247464 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247464 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247464 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22029.515913 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22029.515913 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39262.583024 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39262.583024 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14178.689347 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14178.689347 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30961.110464 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30961.110464 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2958985 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 101444 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 97398 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.136203 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.380347 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840976 # number of writebacks -system.cpu.dcache.writebacks::total 840976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719736 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 719736 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643409 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643409 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5171 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5171 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2363145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2363145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2363145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2363145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084321 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084321 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300378 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300378 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17577 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17577 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384699 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384699 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384699 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384699 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26518641540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26518641540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11550001786 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11550001786 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 202636005 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 202636005 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 57000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 57000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38068643326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38068643326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38068643326 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38068643326 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424047000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424047000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997793498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997793498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421840498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421840498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120414 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120414 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048858 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084224 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084224 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091382 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091382 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24456.449280 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24456.449280 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38451.556992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38451.556992 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11528.474996 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11528.474996 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840831 # number of writebacks +system.cpu.dcache.writebacks::total 840831 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 723109 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 723109 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5191 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5191 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366614 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366614 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366614 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366614 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083719 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083719 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300470 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300470 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17516 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17516 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384189 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384189 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384189 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384189 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26582228002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26582228002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11613303338 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11613303338 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201814751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201814751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38195531340 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38195531340 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38195531340 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38195531340 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424015000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424015000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997805998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997805998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421820998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421820998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048875 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048875 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083858 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083858 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24528.709012 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24528.709012 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38650.458741 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38650.458741 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11521.737326 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11521.737326 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1365,28 +1348,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182247 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817988566000 97.78% 97.78% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64092000 0.00% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554660500 0.03% 97.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40611610500 2.18% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859218929000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818706968000 97.77% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64176500 0.00% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554827000 0.03% 97.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 40873882000 2.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860199853500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694268 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815393 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1425,8 +1408,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175130 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed @@ -1436,18 +1419,18 @@ system.cpu.kern.callpal::callsys 515 0.27% 99.91% # nu system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191976 # number of callpals executed system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326328 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326158 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29661883000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2771562000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826785476000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29671097000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2774842500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827753906000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 936d08062..feb99cd9c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842698 # Number of seconds simulated -sim_ticks 1842697801000 # Number of ticks simulated -final_tick 1842697801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842705 # Number of seconds simulated +sim_ticks 1842705252000 # Number of ticks simulated +final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215096 # Simulator instruction rate (inst/s) -host_op_rate 215096 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5452418287 # Simulator tick rate (ticks/s) -host_mem_usage 309280 # Number of bytes of host memory used -host_seconds 337.96 # Real time elapsed on the host -sim_insts 72693799 # Number of instructions simulated -sim_ops 72693799 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 487424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20019264 # Number of bytes read from this memory +host_inst_rate 221595 # Simulator instruction rate (inst/s) +host_op_rate 221595 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5621199023 # Simulator tick rate (ticks/s) +host_mem_usage 308252 # Number of bytes of host memory used +host_seconds 327.81 # Real time elapsed on the host +sim_insts 72641883 # Number of instructions simulated +sim_ops 72641883 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20049216 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2316480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 282624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2529216 # Number of bytes read from this memory -system.physmem.bytes_read::total 28435264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 487424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 282624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 917952 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2290432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 282112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2525760 # Number of bytes read from this memory +system.physmem.bytes_read::total 28435648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 282112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 917888 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 312801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313269 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2311 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 36195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39519 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2302 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35788 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39465 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444307 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 264517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10864106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1257113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 153375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1372561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15431322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 264517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 153375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498157 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 264517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10864106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1257113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 153375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1372561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19479509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 99716 # Total number of read requests seen -system.physmem.writeReqs 44920 # Total number of write requests seen -system.physmem.cpureqs 144680 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6381824 # Total number of bytes read from memory -system.physmem.bytesWritten 2874880 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6381824 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2874880 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_read::cpu0.inst 265071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10880316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1242973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 153097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1370680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15431468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79952 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 153097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10880316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1242973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 99238 # Total number of read requests seen +system.physmem.writeReqs 44800 # Total number of write requests seen +system.physmem.cpureqs 144082 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6351232 # Total number of bytes read from memory +system.physmem.bytesWritten 2867200 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6258 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6348 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6492 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6415 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6017 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6146 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2882 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2846 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2624 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3004 # Track writes on a per bank basis +system.physmem.perBankRdReqs::5 6398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6152 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6059 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6045 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2861 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2670 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2847 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3000 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2707 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3022 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2472 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2709 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2853 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2760 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2703 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2468 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2705 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2852 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2761 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1841685476500 # Total gap between requests +system.physmem.totGap 1841692926500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 99716 # Categorize read packet sizes +system.physmem.readPktSize::6 99238 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 44920 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 68031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 42 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44800 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 67489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -148,369 +148,367 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 15781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 586.280717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.240853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1929.214074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 6626 41.99% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2550 16.16% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1431 9.07% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 896 5.68% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 638 4.04% 76.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 562 3.56% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 391 2.48% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 301 1.91% 84.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 260 1.65% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 205 1.30% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 214 1.36% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 213 1.35% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 77 0.49% 91.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 70 0.44% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 80 0.51% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 90 0.57% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 36 0.23% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 39 0.25% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 57 0.36% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 48 0.30% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 35 0.22% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 177 1.12% 95.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 87 0.55% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 34 0.22% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 15760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 584.832487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.909397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1926.760563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 6603 41.90% 41.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2572 16.32% 58.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1454 9.23% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 899 5.70% 73.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 642 4.07% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 535 3.39% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 370 2.35% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 312 1.98% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 250 1.59% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 195 1.24% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 235 1.49% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 190 1.21% 90.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 101 0.64% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 71 0.45% 91.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 63 0.40% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 80 0.51% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 51 0.32% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 28 0.18% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 74 0.47% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 51 0.32% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 34 0.22% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 173 1.10% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 86 0.55% 95.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 27 0.17% 95.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 7 0.04% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 18 0.11% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 14 0.09% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 8 0.05% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 12 0.08% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 22 0.14% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 10 0.06% 96.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 4 0.03% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 6 0.04% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 4 0.03% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 1 0.01% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.01% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 1 0.01% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 1 0.01% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.01% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 7 0.04% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 1 0.01% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 3 0.02% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 2 0.01% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 1 0.01% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 2 0.01% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 1 0.01% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 1 0.01% 96.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 1 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.01% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.01% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.01% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 2 0.01% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.01% 96.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 384 2.43% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 8 0.05% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 383 2.43% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 1 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 6 0.04% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.01% 99.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 2 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 15781 # Bytes accessed per row activation -system.physmem.totQLat 1934459750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3605914750 # Sum of mem lat for all requests -system.physmem.totBusLat 498525000 # Total cycles spent in databus access -system.physmem.totBankLat 1172930000 # Total cycles spent in bank access -system.physmem.avgQLat 19401.83 # Average queueing delay per request -system.physmem.avgBankLat 11764.00 # Average bank access latency per request +system.physmem.bytesPerActivate::total 15760 # Bytes accessed per row activation +system.physmem.totQLat 1910826000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3572864750 # Sum of mem lat for all requests +system.physmem.totBusLat 496135000 # Total cycles spent in databus access +system.physmem.totBankLat 1165903750 # Total cycles spent in bank access +system.physmem.avgQLat 19257.12 # Average queueing delay per request +system.physmem.avgBankLat 11749.86 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 36165.84 # Average memory access latency -system.physmem.avgRdBW 3.46 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 36006.98 # Average memory access latency +system.physmem.avgRdBW 3.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.46 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.45 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.17 # Average write queue length over time -system.physmem.readRowHits 93388 # Number of row buffer hits during reads -system.physmem.writeRowHits 35434 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.88 # Row buffer hit rate for writes -system.physmem.avgGap 12733243.98 # Average gap between requests -system.membus.throughput 19523449 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46002 # Transaction distribution -system.membus.trans_dist::ReadResp 45972 # Transaction distribution -system.membus.trans_dist::WriteReq 3749 # Transaction distribution -system.membus.trans_dist::WriteResp 3749 # Transaction distribution -system.membus.trans_dist::Writeback 44920 # Transaction distribution +system.physmem.readRowHits 92920 # Number of row buffer hits during reads +system.physmem.writeRowHits 35346 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.90 # Row buffer hit rate for writes +system.physmem.avgGap 12786160.09 # Average gap between requests +system.membus.throughput 19523578 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 45592 # Transaction distribution +system.membus.trans_dist::ReadResp 45560 # Transaction distribution +system.membus.trans_dist::WriteReq 3756 # Transaction distribution +system.membus.trans_dist::WriteResp 3756 # Transaction distribution +system.membus.trans_dist::Writeback 44800 # Transaction distribution system.membus.trans_dist::UpgradeReq 46 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 47 # Transaction distribution -system.membus.trans_dist::ReadExReq 56809 # Transaction distribution -system.membus.trans_dist::ReadExResp 56809 # Transaction distribution -system.membus.trans_dist::BadAddressError 30 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 192737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 206111 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51863 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 51863 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 244600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 257974 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7047808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 7063555 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2208896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 9256704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9272451 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35965768 # Total data (bytes) -system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12475000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadExReq 56741 # Transaction distribution +system.membus.trans_dist::ReadExResp 56741 # Transaction distribution +system.membus.trans_dist::BadAddressError 32 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 191660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 13322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 243525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 9218432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35966088 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12465000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 520545500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 516080000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 35000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 39000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 777595953 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 771793954 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 156419750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 156435750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 337378 # number of replacements -system.l2c.tagsinuse 65422.722236 # Cycle average of tags in use -system.l2c.total_refs 2472063 # Total number of references to valid blocks. -system.l2c.sampled_refs 402541 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.141146 # Average number of references to valid blocks. -system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54907.432737 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2460.754948 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2679.156770 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 579.419963 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 590.394247 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2099.377178 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2106.186392 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.837821 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.037548 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040881 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.008841 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.009009 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.032034 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032138 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998272 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 520270 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493307 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124051 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83977 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 292923 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239241 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1753769 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835411 # number of Writeback hits -system.l2c.Writeback_hits::total 835411 # number of Writeback hits +system.l2c.tags.replacements 337384 # number of replacements +system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use +system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009052 # 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average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 52882.386480 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71118.606859 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62506.162049 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69139.659022 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52766.589659 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73945.878623 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62303.576116 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58932.120503 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69139.659022 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52766.589659 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73945.878623 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62303.576116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58932.120503 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 52973.119058 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69247.635118 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61636.983112 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52996.560876 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61314.775248 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58544.707135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52996.560876 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61314.775248 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58544.707135 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -628,15 +626,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.254871 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1694871315000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.254871 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078429 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078429 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -645,14 +643,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9512963 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9512963 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4344125507 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4344125507 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4353638470 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4353638470 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4353638470 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4353638470 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9629212 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9629212 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4353407559 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4353407559 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4363036771 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4363036771 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4363036771 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4363036771 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -669,56 +667,56 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54988.225434 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54988.225434 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104546.724755 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104546.724755 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104341.245536 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104341.245536 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 113861 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55660.184971 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 55660.184971 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104770.108755 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 104770.108755 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 104566.489419 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 104566.489419 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 114649 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11412 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11461 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.977305 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.003403 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17349 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5924213 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5924213 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3445287507 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3445287507 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3451211720 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3451211720 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3451211720 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3451211720 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17350 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17350 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5987712 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5987712 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3454277559 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3454277559 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3460265271 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3460265271 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3460265271 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3460265271 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85858.159420 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 85858.159420 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199380.064062 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199380.064062 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.415818 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.415818 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85538.742857 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 85538.742857 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199900.321701 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199900.321701 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -736,22 +734,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4916475 # DTB read hits -system.cpu0.dtb.read_misses 6063 # DTB read misses +system.cpu0.dtb.read_hits 4909978 # DTB read hits +system.cpu0.dtb.read_misses 6100 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 427415 # DTB read accesses -system.cpu0.dtb.write_hits 3510632 # DTB write hits -system.cpu0.dtb.write_misses 668 # DTB write misses +system.cpu0.dtb.read_accesses 428319 # DTB read accesses +system.cpu0.dtb.write_hits 3504299 # DTB write hits +system.cpu0.dtb.write_misses 671 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 162993 # DTB write accesses -system.cpu0.dtb.data_hits 8427107 # DTB hits -system.cpu0.dtb.data_misses 6731 # DTB misses +system.cpu0.dtb.write_accesses 163761 # DTB write accesses +system.cpu0.dtb.data_hits 8414277 # DTB hits +system.cpu0.dtb.data_misses 6771 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 590408 # DTB accesses -system.cpu0.itb.fetch_hits 2754785 # ITB hits -system.cpu0.itb.fetch_misses 3015 # ITB misses +system.cpu0.dtb.data_accesses 592080 # DTB accesses +system.cpu0.itb.fetch_hits 2758234 # ITB hits +system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2757800 # ITB accesses +system.cpu0.itb.fetch_accesses 2761268 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -764,51 +762,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928378822 # number of cpu cycles simulated +system.cpu0.numCycles 928316891 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33851772 # Number of instructions committed -system.cpu0.committedOps 33851772 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31712153 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169925 # Number of float alu accesses -system.cpu0.num_func_calls 812668 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4695347 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31712153 # number of integer instructions -system.cpu0.num_fp_insts 169925 # number of float instructions -system.cpu0.num_int_register_reads 44553309 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23136473 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87700 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89305 # number of times the floating registers were written -system.cpu0.num_mem_refs 8457205 # number of memory refs -system.cpu0.num_load_insts 4937806 # Number of load instructions -system.cpu0.num_store_insts 3519399 # Number of store instructions -system.cpu0.num_idle_cycles 213007832176.448029 # Number of idle cycles -system.cpu0.num_busy_cycles -212079453354.448029 # Number of busy cycles -system.cpu0.not_idle_fraction -228.440641 # Percentage of non-idle cycles -system.cpu0.idle_fraction 229.440641 # Percentage of idle cycles +system.cpu0.committedInsts 33736461 # Number of instructions committed +system.cpu0.committedOps 33736461 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31599588 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169686 # Number of float alu accesses +system.cpu0.num_func_calls 810809 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4665593 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31599588 # number of integer instructions +system.cpu0.num_fp_insts 169686 # number of float instructions +system.cpu0.num_int_register_reads 44374544 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23060255 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87629 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89168 # number of times the floating registers were written +system.cpu0.num_mem_refs 8444409 # number of memory refs +system.cpu0.num_load_insts 4931349 # Number of load instructions +system.cpu0.num_store_insts 3513060 # Number of store instructions +system.cpu0.num_idle_cycles 212988700365.392029 # Number of idle cycles +system.cpu0.num_busy_cycles -212060383474.392029 # Number of busy cycles +system.cpu0.not_idle_fraction -228.435339 # Percentage of non-idle cycles +system.cpu0.idle_fraction 229.435339 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182586 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819523663000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39251000 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365640000 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22768477500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842697031500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819515680500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39349500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365678500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22783774000 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842704482500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694800 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815835 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -844,10 +842,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175327 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -856,21 +854,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192238 # number of callpals executed +system.cpu0.kern.callpal::total 192242 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1738 -system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321965 # fraction of useful protection mode switches +system.cpu0.kern.mode_good::idle 170 +system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29806042000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2607375500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810283609500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29786026000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2614250500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810304201500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -902,73 +900,73 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110454960 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 786209 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 786164 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371427 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150852 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133572 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 847417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1371009 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 2218426 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27116864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55346243 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 82463107 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203524040 # Total data (bytes) +system.toL2Bus.throughput 110422039 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 786602 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 786555 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3756 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3756 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371447 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 15 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 849315 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1370344 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 2219659 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27177600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55325386 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 82502986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203464200 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2135036000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1907460021 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1913139810 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2223763109 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2237602233 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469142 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2977 # Transaction distribution -system.iobus.trans_dist::ReadResp 2977 # Transaction distribution -system.iobus.trans_dist::WriteReq 21029 # Transaction distribution -system.iobus.trans_dist::WriteResp 21029 # Transaction distribution +system.iobus.throughput 1469136 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2975 # Transaction distribution +system.iobus.trans_dist::ReadResp 2975 # Transaction distribution +system.iobus.trans_dist::WriteReq 21036 # Transaction distribution +system.iobus.trans_dist::WriteResp 21036 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13314 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 48012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15747 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1123115 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -976,384 +974,384 @@ system.iobus.reqLayer1.occupancy 105000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6219000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6200000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1797000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1827000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 157278470 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 157303021 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9565000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9566000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17530000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17990250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.replacements 950939 # number of replacements -system.cpu0.icache.tagsinuse 511.192426 # Cycle average of tags in use -system.cpu0.icache.total_refs 43369559 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 951450 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 45.582594 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10375508000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 249.451681 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 99.242283 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 162.498462 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.487210 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.193833 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.317380 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998423 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 33330806 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7798498 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2240255 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43369559 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33330806 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7798498 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2240255 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43369559 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33330806 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7798498 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2240255 # number of overall hits -system.cpu0.icache.overall_hits::total 43369559 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 527907 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 126362 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 313908 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 968177 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 527907 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 126362 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 313908 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 968177 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 527907 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 126362 # 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number of replacements -system.cpu0.dcache.tagsinuse 511.997813 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13288463 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1392330 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.544047 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 250.572227 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 130.318836 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 131.106750 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.489399 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.254529 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.256068 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4079887 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1087384 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2393640 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7560911 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3214191 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 837673 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1292223 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5344087 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117280 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19306 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47521 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184107 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126439 # 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number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 533191 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1353062 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 45123 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 589200 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 803394 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9725 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2154 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6827 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18706 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 889560 # 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number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19416401172 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28461500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102597000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 131058500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 25000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 25000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3878253500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27163807672 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31042061172 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3878253500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27163807672 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31042061172 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4800376 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1186766 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2926831 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8913973 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383262 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 882796 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1881423 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6147481 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127005 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21460 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54348 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 202813 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126439 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21329 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199287 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8183638 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2069562 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4808254 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15061454 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8183638 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2069562 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4808254 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15061454 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150090 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083742 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182173 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151791 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049973 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051114 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.313167 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.130687 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076572 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100373 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.125616 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092233 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108700 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069824 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233430 # 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average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13213.324048 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15028.123627 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7006.227948 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 25000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26838.195910 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24201.733328 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14394.942986 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26838.195910 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24201.733328 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14394.942986 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 565985 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1720 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 17882 # number of cycles access was blocked +system.cpu0.dcache.tags.replacements 1391525 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 250.196143 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.348399 # 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number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150352 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182019 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.151874 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049979 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051014 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.313580 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131075 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076802 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100646 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124142 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092101 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000039 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108868 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069604 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233532 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.143384 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108868 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069604 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233532 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.143384 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22865.260790 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17532.447166 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8586.573010 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35987.650956 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 29883.416150 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23964.755770 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13202.078522 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15091.143004 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7017.120486 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 19000.500000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26969.443214 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24026.159590 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14324.784127 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26969.443214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24026.159590 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14324.784127 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 557875 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 852 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 17918 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 31.651102 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 245.714286 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 31.134892 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 121.714286 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835411 # number of writebacks -system.cpu0.dcache.writebacks::total 835411 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280380 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 280380 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 500979 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 500979 # 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number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 23000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3589243500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6842155525 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10431399025 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3589243500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6842155525 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10431399025 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295697000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311546500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607243500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 363354500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427379500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790734000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 659051500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 738926000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397977500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083742 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086377 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039510 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051114 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046891 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021691 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100373 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099599 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037310 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032237 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032237 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20733.659013 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16820.503202 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17924.719500 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33878.310396 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29355.224833 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30885.816310 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11213.324048 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12230.925919 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11941.258359 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 23000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835257 # number of writebacks +system.cpu0.dcache.writebacks::total 835257 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 281255 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 281255 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 503456 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 503456 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1394 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1394 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 784711 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 784711 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 143953 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 341236 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 485189 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 143953 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341236 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 485189 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2055649750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4240939408 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6296589158 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1521155991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2563125747 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4084281738 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24249500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66698251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90947751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3576805741 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6804065155 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10380870896 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3576805741 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6804065155 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10380870896 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 294283500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312003000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 606286500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 361937500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429433000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791370500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 656221000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 741436000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397657000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083444 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086144 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051014 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046894 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098681 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037292 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032215 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032215 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20778.830992 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16781.975276 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17906.452539 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33786.197965 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28952.712667 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30582.187614 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11200.692841 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12344.669813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12017.408959 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16999.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1368,22 +1366,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1206143 # DTB read hits -system.cpu1.dtb.read_misses 1395 # DTB read misses -system.cpu1.dtb.read_acv 35 # DTB read access violations -system.cpu1.dtb.read_accesses 142828 # DTB read accesses -system.cpu1.dtb.write_hits 904590 # DTB write hits -system.cpu1.dtb.write_misses 190 # DTB write misses +system.cpu1.dtb.read_hits 1205047 # DTB read hits +system.cpu1.dtb.read_misses 1367 # DTB read misses +system.cpu1.dtb.read_acv 34 # DTB read access violations +system.cpu1.dtb.read_accesses 142944 # DTB read accesses +system.cpu1.dtb.write_hits 904403 # DTB write hits +system.cpu1.dtb.write_misses 185 # DTB write misses system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58592 # DTB write accesses -system.cpu1.dtb.data_hits 2110733 # DTB hits -system.cpu1.dtb.data_misses 1585 # DTB misses -system.cpu1.dtb.data_acv 58 # DTB access violations -system.cpu1.dtb.data_accesses 201420 # DTB accesses -system.cpu1.itb.fetch_hits 862559 # ITB hits -system.cpu1.itb.fetch_misses 707 # ITB misses -system.cpu1.itb.fetch_acv 34 # ITB acv -system.cpu1.itb.fetch_accesses 863266 # ITB accesses +system.cpu1.dtb.write_accesses 58533 # DTB write accesses +system.cpu1.dtb.data_hits 2109450 # DTB hits +system.cpu1.dtb.data_misses 1552 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 201477 # DTB accesses +system.cpu1.itb.fetch_hits 861634 # ITB hits +system.cpu1.itb.fetch_misses 693 # ITB misses +system.cpu1.itb.fetch_acv 30 # ITB acv +system.cpu1.itb.fetch_accesses 862327 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1396,28 +1394,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953614983 # number of cpu cycles simulated +system.cpu1.numCycles 953630418 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7923216 # Number of instructions committed -system.cpu1.committedOps 7923216 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7378774 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44696 # Number of float alu accesses -system.cpu1.num_func_calls 212761 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1003934 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7378774 # number of integer instructions -system.cpu1.num_fp_insts 44696 # number of float instructions -system.cpu1.num_int_register_reads 10322317 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5366754 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24140 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24473 # number of times the floating registers were written -system.cpu1.num_mem_refs 2118035 # number of memory refs -system.cpu1.num_load_insts 1211092 # Number of load instructions -system.cpu1.num_store_insts 906943 # Number of store instructions -system.cpu1.num_idle_cycles -710985323.015638 # Number of idle cycles -system.cpu1.num_busy_cycles 1664600306.015638 # Number of busy cycles -system.cpu1.not_idle_fraction 1.745569 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.745569 # Percentage of idle cycles +system.cpu1.committedInsts 7889245 # Number of instructions committed +system.cpu1.committedOps 7889245 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7344952 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44937 # Number of float alu accesses +system.cpu1.num_func_calls 213049 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 993802 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7344952 # number of integer instructions +system.cpu1.num_fp_insts 44937 # number of float instructions +system.cpu1.num_int_register_reads 10269748 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5343251 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24271 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24577 # number of times the floating registers were written +system.cpu1.num_mem_refs 2116682 # number of memory refs +system.cpu1.num_load_insts 1209934 # Number of load instructions +system.cpu1.num_store_insts 906748 # Number of store instructions +system.cpu1.num_idle_cycles -715527638.238183 # Number of idle cycles +system.cpu1.num_busy_cycles 1669158056.238183 # Number of busy cycles +system.cpu1.not_idle_fraction 1.750320 # Percentage of non-idle cycles +system.cpu1.idle_fraction -0.750320 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1435,35 +1433,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8997247 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8318296 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 124435 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7453298 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6389224 # Number of BTB hits +system.cpu2.branchPred.lookups 9022316 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8342315 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 122648 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7529449 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6410701 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.723448 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 282371 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13443 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.141702 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 283187 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 12478 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3184667 # DTB read hits -system.cpu2.dtb.read_misses 11563 # DTB read misses -system.cpu2.dtb.read_acv 122 # DTB read access violations -system.cpu2.dtb.read_accesses 218108 # DTB read accesses -system.cpu2.dtb.write_hits 2003168 # DTB write hits -system.cpu2.dtb.write_misses 2582 # DTB write misses -system.cpu2.dtb.write_acv 105 # DTB write access violations -system.cpu2.dtb.write_accesses 82984 # DTB write accesses -system.cpu2.dtb.data_hits 5187835 # DTB hits -system.cpu2.dtb.data_misses 14145 # DTB misses +system.cpu2.dtb.read_hits 3192037 # DTB read hits +system.cpu2.dtb.read_misses 11608 # DTB read misses +system.cpu2.dtb.read_acv 121 # DTB read access violations +system.cpu2.dtb.read_accesses 216573 # DTB read accesses +system.cpu2.dtb.write_hits 2009173 # DTB write hits +system.cpu2.dtb.write_misses 2522 # DTB write misses +system.cpu2.dtb.write_acv 106 # DTB write access violations +system.cpu2.dtb.write_accesses 81978 # DTB write accesses +system.cpu2.dtb.data_hits 5201210 # DTB hits +system.cpu2.dtb.data_misses 14130 # DTB misses system.cpu2.dtb.data_acv 227 # DTB access violations -system.cpu2.dtb.data_accesses 301092 # DTB accesses -system.cpu2.itb.fetch_hits 370432 # ITB hits -system.cpu2.itb.fetch_misses 5697 # ITB misses -system.cpu2.itb.fetch_acv 245 # ITB acv -system.cpu2.itb.fetch_accesses 376129 # ITB accesses +system.cpu2.dtb.data_accesses 298551 # DTB accesses +system.cpu2.itb.fetch_hits 369667 # ITB hits +system.cpu2.itb.fetch_misses 5681 # ITB misses +system.cpu2.itb.fetch_acv 262 # ITB acv +system.cpu2.itb.fetch_accesses 375348 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1476,270 +1474,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31194709 # number of cpu cycles simulated +system.cpu2.numCycles 31245078 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8336463 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36595534 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8997247 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6671595 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8714180 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 607609 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9678498 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 11323 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1980 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 64467 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 86613 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2554168 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 86055 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27288913 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.341040 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.295561 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8348883 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36663716 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9022316 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6693888 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8736568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 602984 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9694630 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11222 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1957 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63711 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 86195 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2553880 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 85053 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27335965 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.341226 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.294449 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18574733 68.07% 68.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269160 0.99% 69.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 428961 1.57% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4866915 17.83% 88.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 754326 2.76% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 165422 0.61% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 191254 0.70% 92.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 429367 1.57% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1608775 5.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18599397 68.04% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269863 0.99% 69.03% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 429102 1.57% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4885317 17.87% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 756803 2.77% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 166340 0.61% 91.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 191609 0.70% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 429140 1.57% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1608394 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27288913 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288422 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.173133 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8484758 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9763089 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8105885 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 306526 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 382761 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165822 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12764 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36197990 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39851 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 382761 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8844170 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2798398 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5770090 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7975185 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1272419 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35047656 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 232046 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 447152 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23489226 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 43822690 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43659490 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 163200 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21694214 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1795012 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 501276 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59320 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3724979 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3343402 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2093050 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 368261 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 257932 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32557394 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 620599 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32107794 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34091 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2143269 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1080696 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 438167 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27288913 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.176588 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.573888 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27335965 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288760 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.173424 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8495766 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9778515 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8128034 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 307242 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 380496 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165135 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12538 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36269918 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39153 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 380496 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8853799 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2797423 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5789351 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7998658 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1270334 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35131949 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2438 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 231189 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 444117 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23541427 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43931372 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43768405 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 162967 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21760313 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1781114 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 501831 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59191 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3719256 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3350609 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2097879 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 369762 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 260934 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32641753 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 622044 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32196803 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 34835 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2138258 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1073109 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 438824 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27335965 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.177818 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.573987 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15150790 55.52% 55.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3070151 11.25% 66.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1548988 5.68% 72.45% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5689584 20.85% 93.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 903005 3.31% 96.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480338 1.76% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 283929 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 143393 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18735 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15167963 55.49% 55.49% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3067850 11.22% 66.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1557003 5.70% 72.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5712284 20.90% 93.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 903378 3.30% 96.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480833 1.76% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 285081 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 142652 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18921 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27288913 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27335965 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33803 13.75% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 111727 45.45% 59.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100297 40.80% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33684 13.60% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 113022 45.64% 59.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100957 40.76% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26449669 82.38% 82.39% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20147 0.06% 82.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8446 0.03% 82.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3312033 10.32% 92.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2025467 6.31% 99.10% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 288360 0.90% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26526068 82.39% 82.39% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20082 0.06% 82.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8432 0.03% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3318552 10.31% 92.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2030927 6.31% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 289082 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32107794 # Type of FU issued -system.cpu2.iq.rate 1.029271 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 245827 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 91550157 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35210267 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 31710626 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234262 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114809 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110859 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32229265 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121908 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186278 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32196803 # Type of FU issued +system.cpu2.iq.rate 1.030460 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 247663 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007692 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 91777621 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35291242 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 31803164 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234448 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114643 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110912 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32319915 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122111 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186470 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 409987 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1098 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3916 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 156672 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 409308 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1087 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 154806 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4171 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 28368 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4179 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28515 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 382761 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2017515 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 205037 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34446466 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224960 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3343402 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2093050 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 551127 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 142834 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3916 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63764 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127616 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 191380 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 31948816 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3204490 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 158978 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 380496 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2018433 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 205280 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34533473 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 223572 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3350609 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2097879 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 552418 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 143005 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2030 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3940 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 62474 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127218 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 189692 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32041792 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3211958 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 155011 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1268473 # number of nop insts executed -system.cpu2.iew.exec_refs 5214665 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7427208 # Number of branches executed -system.cpu2.iew.exec_stores 2010175 # Number of stores executed -system.cpu2.iew.exec_rate 1.024174 # Inst execution rate -system.cpu2.iew.wb_sent 31853816 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31821485 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18500784 # num instructions producing a value -system.cpu2.iew.wb_consumers 21694431 # num instructions consuming a value +system.cpu2.iew.exec_nop 1269676 # number of nop insts executed +system.cpu2.iew.exec_refs 5228104 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7451179 # Number of branches executed +system.cpu2.iew.exec_stores 2016146 # Number of stores executed +system.cpu2.iew.exec_rate 1.025499 # Inst execution rate +system.cpu2.iew.wb_sent 31946323 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31914076 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18560539 # num instructions producing a value +system.cpu2.iew.wb_consumers 21756623 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.020092 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.852790 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.021411 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.853098 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2318994 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 182432 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 176935 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26906152 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.192355 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846387 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2307107 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 183220 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 175579 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26955469 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.193861 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846623 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16157542 60.05% 60.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2331595 8.67% 68.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1218913 4.53% 73.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5433463 20.19% 93.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503772 1.87% 95.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185469 0.69% 96.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 177448 0.66% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 178843 0.66% 97.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 719107 2.67% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16175286 60.01% 60.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2330504 8.65% 68.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1226068 4.55% 73.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5456953 20.24% 93.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 503178 1.87% 95.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186113 0.69% 96.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 177622 0.66% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179384 0.67% 97.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 720361 2.67% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26906152 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32081688 # Number of instructions committed -system.cpu2.commit.committedOps 32081688 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26955469 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32181084 # Number of instructions committed +system.cpu2.commit.committedOps 32181084 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4869793 # Number of memory references committed -system.cpu2.commit.loads 2933415 # Number of loads committed -system.cpu2.commit.membars 63859 # Number of memory barriers committed -system.cpu2.commit.branches 7280639 # Number of branches committed -system.cpu2.commit.fp_insts 109636 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30638732 # Number of committed integer instructions. -system.cpu2.commit.function_calls 228563 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 719107 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4884374 # Number of memory references committed +system.cpu2.commit.loads 2941301 # Number of loads committed +system.cpu2.commit.membars 64148 # Number of memory barriers committed +system.cpu2.commit.branches 7305681 # Number of branches committed +system.cpu2.commit.fp_insts 109768 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30735120 # Number of committed integer instructions. +system.cpu2.commit.function_calls 229363 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 720361 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60513787 # The number of ROB reads -system.cpu2.rob.rob_writes 69183653 # The number of ROB writes -system.cpu2.timesIdled 245794 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3905796 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746583104 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 30918811 # Number of Instructions Simulated -system.cpu2.committedOps 30918811 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 30918811 # Number of Instructions Simulated -system.cpu2.cpi 1.008923 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.008923 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.991156 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.991156 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42017360 # number of integer regfile reads -system.cpu2.int_regfile_writes 22376128 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67819 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67985 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5215792 # number of misc regfile reads -system.cpu2.misc_regfile_writes 257331 # number of misc regfile writes +system.cpu2.rob.rob_reads 60649307 # The number of ROB reads +system.cpu2.rob.rob_writes 69356385 # The number of ROB writes +system.cpu2.timesIdled 245741 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3909113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746532644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31016177 # Number of Instructions Simulated +system.cpu2.committedOps 31016177 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31016177 # Number of Instructions Simulated +system.cpu2.cpi 1.007380 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.007380 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.992674 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.992674 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42141472 # number of integer regfile reads +system.cpu2.int_regfile_writes 22438304 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67749 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68082 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5235386 # number of misc regfile reads +system.cpu2.misc_regfile_writes 258296 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |