diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
4 files changed, 4969 insertions, 4897 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 9abb1e987..1996e7f30 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.883224 # Number of seconds simulated -sim_ticks 1883223940000 # Number of ticks simulated -final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1883224346500 # Number of ticks simulated +final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180615 # Simulator instruction rate (inst/s) -host_op_rate 180615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6060637883 # Simulator tick rate (ticks/s) -host_mem_usage 316396 # Number of bytes of host memory used -host_seconds 310.73 # Real time elapsed on the host -sim_insts 56122642 # Number of instructions simulated -sim_ops 56122642 # Number of ops (including micro ops) simulated +host_inst_rate 283997 # Simulator instruction rate (inst/s) +host_op_rate 283997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9530044697 # Simulator tick rate (ticks/s) +host_mem_usage 369276 # Number of bytes of host memory used +host_seconds 197.61 # Real time elapsed on the host +sim_insts 56120453 # Number of instructions simulated +sim_ops 56120453 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory +system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4903936 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7563264 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 405182 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory +system.physmem.num_reads::total 405197 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 76624 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 118176 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13769813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13770323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 559041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 559041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2604011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1412114 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4016125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2604011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13769813 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 405186 # Number of read requests accepted -system.physmem.writeReqs 118157 # Number of write requests accepted -system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue -system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17786448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 405197 # Number of read requests accepted +system.physmem.writeReqs 118176 # Number of write requests accepted +system.physmem.readBursts 405197 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118176 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25920704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11904 # Total number of bytes read from write queue +system.physmem.bytesWritten 7562112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25932608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7563264 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 186 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25480 # Per bank write bursts -system.physmem.perBankRdBursts::1 25741 # Per bank write bursts -system.physmem.perBankRdBursts::2 25855 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25484 # Per bank write bursts +system.physmem.perBankRdBursts::1 25740 # Per bank write bursts +system.physmem.perBankRdBursts::2 25857 # Per bank write bursts system.physmem.perBankRdBursts::3 25788 # Per bank write bursts -system.physmem.perBankRdBursts::4 25233 # Per bank write bursts -system.physmem.perBankRdBursts::5 24956 # Per bank write bursts -system.physmem.perBankRdBursts::6 24811 # Per bank write bursts +system.physmem.perBankRdBursts::4 25237 # Per bank write bursts +system.physmem.perBankRdBursts::5 24959 # Per bank write bursts +system.physmem.perBankRdBursts::6 24814 # Per bank write bursts system.physmem.perBankRdBursts::7 24586 # Per bank write bursts system.physmem.perBankRdBursts::8 25127 # Per bank write bursts -system.physmem.perBankRdBursts::9 25280 # Per bank write bursts -system.physmem.perBankRdBursts::10 25532 # Per bank write bursts +system.physmem.perBankRdBursts::9 25284 # Per bank write bursts +system.physmem.perBankRdBursts::10 25531 # Per bank write bursts system.physmem.perBankRdBursts::11 24857 # Per bank write bursts -system.physmem.perBankRdBursts::12 24547 # Per bank write bursts -system.physmem.perBankRdBursts::13 25588 # Per bank write bursts -system.physmem.perBankRdBursts::14 25870 # Per bank write bursts +system.physmem.perBankRdBursts::12 24549 # Per bank write bursts +system.physmem.perBankRdBursts::13 25592 # Per bank write bursts +system.physmem.perBankRdBursts::14 25866 # Per bank write bursts system.physmem.perBankRdBursts::15 25740 # Per bank write bursts system.physmem.perBankWrBursts::0 7812 # Per bank write bursts -system.physmem.perBankWrBursts::1 7677 # Per bank write bursts +system.physmem.perBankWrBursts::1 7680 # Per bank write bursts system.physmem.perBankWrBursts::2 8067 # Per bank write bursts -system.physmem.perBankWrBursts::3 7744 # Per bank write bursts -system.physmem.perBankWrBursts::4 7318 # Per bank write bursts -system.physmem.perBankWrBursts::5 6954 # Per bank write bursts -system.physmem.perBankWrBursts::6 6788 # Per bank write bursts -system.physmem.perBankWrBursts::7 6406 # Per bank write bursts -system.physmem.perBankWrBursts::8 7235 # Per bank write bursts -system.physmem.perBankWrBursts::9 6889 # Per bank write bursts -system.physmem.perBankWrBursts::10 7393 # Per bank write bursts -system.physmem.perBankWrBursts::11 6865 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts +system.physmem.perBankWrBursts::4 7320 # Per bank write bursts +system.physmem.perBankWrBursts::5 6957 # Per bank write bursts +system.physmem.perBankWrBursts::6 6792 # Per bank write bursts +system.physmem.perBankWrBursts::7 6401 # Per bank write bursts +system.physmem.perBankWrBursts::8 7236 # Per bank write bursts +system.physmem.perBankWrBursts::9 6892 # Per bank write bursts +system.physmem.perBankWrBursts::10 7391 # Per bank write bursts +system.physmem.perBankWrBursts::11 6866 # Per bank write bursts system.physmem.perBankWrBursts::12 7045 # Per bank write bursts -system.physmem.perBankWrBursts::13 8007 # Per bank write bursts +system.physmem.perBankWrBursts::13 8010 # Per bank write bursts system.physmem.perBankWrBursts::14 7989 # Per bank write bursts -system.physmem.perBankWrBursts::15 7937 # Per bank write bursts +system.physmem.perBankWrBursts::15 7955 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 1883215178500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 1883215617500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 405186 # Read request sizes (log2) +system.physmem.readPktSize::6 405197 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118157 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118176 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -147,125 +147,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 530.294837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 322.585016 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.640457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14650 23.20% 23.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10589 16.77% 39.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5075 8.04% 48.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3003 4.76% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2370 3.75% 56.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2105 3.33% 59.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1364 2.16% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1607 2.55% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22377 35.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63140 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5316 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.186983 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2896.748549 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5313 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5316 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5316 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.226862 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.933757 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.590348 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4662 87.70% 87.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 15 0.28% 87.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 21 0.40% 88.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 225 4.23% 92.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 46 0.87% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 10 0.19% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 7 0.13% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.13% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.36% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.04% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 12 0.23% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.11% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 29 0.55% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.26% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 12 0.23% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 164 3.09% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.09% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.06% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.08% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.06% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 8 0.15% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.11% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.23% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.06% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads -system.physmem.totQLat 2131293750 # Total ticks spent queuing -system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5316 # Writes before turning the bus around for reads +system.physmem.totQLat 2156220500 # Total ticks spent queuing +system.physmem.totMemAccLat 9750176750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2025055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5323.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24073.86 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -273,108 +274,113 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 364467 # Number of row buffer hits during reads -system.physmem.writeRowHits 95695 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes -system.physmem.avgGap 3598433.87 # Average gap between requests -system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states +system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing +system.physmem.readRowHits 364400 # Number of row buffer hits during reads +system.physmem.writeRowHits 95629 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes +system.physmem.avgGap 3598228.45 # Average gap between requests +system.physmem.pageHitRate 87.93 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1774012993500 # Time in different power states system.physmem.memoryStateTime::REF 62884900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states +system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 17814330 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295751 # Transaction distribution -system.membus.trans_dist::ReadResp 295735 # Transaction distribution +system.membus.trans_dist::ReadReq 295760 # Transaction distribution +system.membus.trans_dist::ReadResp 295744 # Transaction distribution system.membus.trans_dist::WriteReq 9618 # Transaction distribution system.membus.trans_dist::WriteResp 9618 # Transaction distribution -system.membus.trans_dist::Writeback 76605 # Transaction distribution +system.membus.trans_dist::Writeback 76624 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 157 # Transaction distribution -system.membus.trans_dist::UpgradeResp 157 # Transaction distribution -system.membus.trans_dist::ReadExReq 116539 # Transaction distribution -system.membus.trans_dist::ReadExResp 116539 # Transaction distribution +system.membus.trans_dist::UpgradeReq 154 # Transaction distribution +system.membus.trans_dist::UpgradeResp 154 # Transaction distribution +system.membus.trans_dist::ReadExReq 116541 # Transaction distribution +system.membus.trans_dist::ReadExResp 116541 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887296 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920424 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33538260 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks) +system.membus.pkt_count::total 1003716 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30835584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30879892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33540180 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 158 # Total snoops (count) +system.membus.snoop_fanout::samples 523708 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 523708 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 523708 # Request fanout histogram +system.membus.reqLayer0.occupancy 30927500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1547261750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3825161596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43114249 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.288180 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1728025257000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.288180 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080511 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080511 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375533 # Number of tag accesses -system.iocache.tags.data_accesses 375533 # Number of data accesses +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,30 +397,30 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -428,36 +434,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14964215 # Number of BP lookups -system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits +system.cpu.branchPred.lookups 14964931 # Number of BP lookups +system.cpu.branchPred.condPredicted 12983118 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 374694 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9691016 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5184483 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.497827 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807557 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32108 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9238395 # DTB read hits -system.cpu.dtb.read_misses 17814 # DTB read misses +system.cpu.dtb.read_hits 9237824 # DTB read hits +system.cpu.dtb.read_misses 17804 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766068 # DTB read accesses -system.cpu.dtb.write_hits 6385066 # DTB write hits -system.cpu.dtb.write_misses 2311 # DTB write misses +system.cpu.dtb.read_accesses 766148 # DTB read accesses +system.cpu.dtb.write_hits 6384867 # DTB write hits +system.cpu.dtb.write_misses 2306 # DTB write misses system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298441 # DTB write accesses -system.cpu.dtb.data_hits 15623461 # DTB hits -system.cpu.dtb.data_misses 20125 # DTB misses +system.cpu.dtb.write_accesses 298467 # DTB write accesses +system.cpu.dtb.data_hits 15622691 # DTB hits +system.cpu.dtb.data_misses 20110 # DTB misses system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064509 # DTB accesses -system.cpu.itb.fetch_hits 4000795 # ITB hits -system.cpu.itb.fetch_misses 6874 # ITB misses -system.cpu.itb.fetch_acv 703 # ITB acv -system.cpu.itb.fetch_accesses 4007669 # ITB accesses +system.cpu.dtb.data_accesses 1064615 # DTB accesses +system.cpu.itb.fetch_hits 3999749 # ITB hits +system.cpu.itb.fetch_misses 6851 # ITB misses +system.cpu.itb.fetch_acv 647 # ITB acv +system.cpu.itb.fetch_accesses 4006600 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -470,39 +476,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 176776474 # number of cpu cycles simulated +system.cpu.numCycles 174888375 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56122642 # Number of instructions committed -system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.149825 # CPI: cycles per instruction -system.cpu.ipc 0.317478 # IPC: instructions per cycle +system.cpu.committedInsts 56120453 # Number of instructions committed +system.cpu.committedOps 56120453 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2530516 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5527 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3591560318 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.116304 # CPI: cycles per instruction +system.cpu.ipc 0.320893 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211459 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105855 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182673 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148871 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1832868777500 97.33% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80360500 0.00% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 672864500 0.04% 97.37% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 49601349000 2.63% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1883223351500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693590 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814959 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -541,7 +547,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175516 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -550,23 +556,23 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192390 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches +system.cpu.kern.callpal::total 192398 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5867 # number of protection mode switches system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325550 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 36222818500 1.92% 1.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4061127000 0.22% 2.14% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842939396000 97.86% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked -system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 83840328 # Number of cycles that the object actually ticked +system.cpu.idleCycles 91048047 # Total number of cycles that the object has spent stopped system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -598,12 +604,10 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1436853 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51169 # Transaction distribution +system.iobus.trans_dist::WriteReq 51170 # Transaction distribution system.iobus.trans_dist::WriteResp 51170 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -620,23 +624,22 @@ system.iobus.pkt_count_system.bridge.master::total 33096 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705916 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) @@ -659,66 +662,66 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42013751 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1458007 # number of replacements -system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.627041 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 1457910 # number of replacements +system.cpu.icache.tags.tagsinuse 509.626980 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18940924 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1458421 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.987281 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31560714250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.626980 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21867553 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21867553 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18950163 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18950163 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18950163 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18950163 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18950163 # number of overall hits -system.cpu.icache.overall_hits::total 18950163 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458695 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458695 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458695 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458695 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458695 # number of overall misses -system.cpu.icache.overall_misses::total 1458695 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20021954296 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20021954296 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20021954296 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20021954296 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20021954296 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20021954296 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20408858 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20408858 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20408858 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20408858 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20408858 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20408858 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071474 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071474 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071474 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13725.936057 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13725.936057 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21858119 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21858119 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18940927 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18940927 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18940927 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18940927 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18940927 # number of overall hits +system.cpu.icache.overall_hits::total 18940927 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1458596 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1458596 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1458596 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1458596 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1458596 # number of overall misses +system.cpu.icache.overall_misses::total 1458596 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20022164568 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20022164568 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20022164568 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20022164568 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20022164568 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20022164568 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20399523 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20399523 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20399523 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20399523 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20399523 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20399523 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071501 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071501 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071501 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071501 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071501 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071501 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.011844 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13727.011844 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13727.011844 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13727.011844 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -727,143 +730,152 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458695 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1458695 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1458695 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1458695 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1458695 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1458695 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097209704 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17097209704 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097209704 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17097209704 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097209704 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17097209704 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071474 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071474 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071474 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458596 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1458596 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1458596 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1458596 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1458596 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1458596 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097663432 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17097663432 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097663432 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17097663432 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097663432 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17097663432 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071501 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071501 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071501 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.000768 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.000768 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2557139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2557106 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304253 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6580813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143044180 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917133 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6579924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93346368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143016724 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236363092 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41947 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3734153 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011176 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105123 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3692421 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41732 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3734153 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2697404999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 232500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191719796 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2191548568 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194901157 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194491404 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 339412 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65326.749870 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2981869 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404575 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.370374 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 339424 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65327.181695 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2981337 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.368859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54484.622776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10842.127094 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.831369 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165438 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996807 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1459 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 54492.967363 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10834.214332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.831497 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165317 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996814 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1457 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2777 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30252211 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30252211 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2261673 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2261673 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 838282 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 838282 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 30247978 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 30247978 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2261320 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2261320 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 838111 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 838111 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 187588 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187588 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2449261 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2449261 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2449261 # number of overall hits -system.cpu.l2cache.overall_hits::total 2449261 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 288648 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288648 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 20 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 116676 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116676 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 405324 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405324 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 405324 # number of overall misses -system.cpu.l2cache.overall_misses::total 405324 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18909912500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18909912500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_hits::cpu.inst 187575 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187575 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2448895 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2448895 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2448895 # number of overall hits +system.cpu.l2cache.overall_hits::total 2448895 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 288657 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288657 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 116678 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116678 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 405335 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405335 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 405335 # number of overall misses +system.cpu.l2cache.overall_misses::total 405335 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918279000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18918279000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 115495 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 115495 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8088441363 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8088441363 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 26998353863 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26998353863 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 26998353863 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26998353863 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550321 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2550321 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 838282 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 838282 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 24 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304264 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304264 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2854585 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2854585 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2854585 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2854585 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113181 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.113181 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.833333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383470 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383470 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141991 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141991 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141991 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141991 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65512.016366 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65512.016366 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 5774.750000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5774.750000 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69323.951481 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69323.951481 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66609.314679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66609.314679 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8105432113 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8105432113 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27023711113 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27023711113 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27023711113 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27023711113 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 2549977 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2549977 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 838111 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 838111 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304253 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304253 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2854230 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2854230 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2854230 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2854230 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113200 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.113200 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383490 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383490 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142012 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.142012 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142012 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.142012 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65538.958002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65538.958002 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 6793.823529 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6793.823529 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69468.384040 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69468.384040 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66670.065780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66670.065780 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,54 +884,54 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76605 # number of writebacks -system.cpu.l2cache.writebacks::total 76605 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288648 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288648 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 20 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116676 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 405324 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405324 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 405324 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405324 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15301161000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15301161000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 201018 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201018 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6587763637 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6587763637 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21888924637 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21888924637 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21888924637 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21888924637 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333222000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333222000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887374000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887374000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220596000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220596000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.833333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383470 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383470 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141991 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141991 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53009.759292 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53009.759292 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10050.900000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10050.900000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56462.028498 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56462.028498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 76624 # number of writebacks +system.cpu.l2cache.writebacks::total 76624 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288657 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288657 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116678 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116678 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 405335 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405335 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 405335 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405335 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15309425000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15309425000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 170516 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 170516 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6604759387 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6604759387 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21914184387 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21914184387 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21914184387 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21914184387 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333304000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333304000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1888377500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1888377500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221681500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221681500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383490 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383490 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.142012 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.142012 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53036.735641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53036.735641 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10030.352941 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.352941 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56606.724378 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56606.724378 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -927,86 +939,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1395422 # number of replacements +system.cpu.dcache.tags.replacements 1395163 # number of replacements system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13764943 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395934 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.860741 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13764370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395675 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.862160 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982303 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63626016 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63626016 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 7806784 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7806784 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 5576432 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576432 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182707 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182707 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 198983 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198983 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 13383216 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13383216 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 13383216 # number of overall hits -system.cpu.dcache.overall_hits::total 13383216 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1201616 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201616 # number of ReadReq misses +system.cpu.dcache.tags.tag_accesses 63622669 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63622669 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 7806418 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7806418 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 5576177 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576177 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182756 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182756 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 198986 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198986 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 13382595 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13382595 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 13382595 # number of overall hits +system.cpu.dcache.overall_hits::total 13382595 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1201460 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201460 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 573699 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 573699 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17299 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17299 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 1775315 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775315 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1775315 # number of overall misses -system.cpu.dcache.overall_misses::total 1775315 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31018318500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31018318500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20748316044 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20748316044 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231689250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 231689250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 51766634544 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51766634544 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 51766634544 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51766634544 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 9008400 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9008400 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 6150131 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150131 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200006 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200006 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198983 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198983 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 15158531 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15158531 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 15158531 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15158531 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133388 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133388 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093282 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093282 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086492 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086492 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.117117 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117117 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.117117 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117117 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25813.836117 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25813.836117 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36165.857085 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36165.857085 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13393.216371 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13393.216371 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29159.126433 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29159.126433 # average overall miss latency +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17252 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17252 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.inst 1775159 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1775159 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1775159 # number of overall misses +system.cpu.dcache.overall_misses::total 1775159 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31026314750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31026314750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20775588791 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20775588791 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 230892000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 230892000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 51801903541 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51801903541 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 51801903541 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51801903541 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 9007878 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9007878 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 6149876 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149876 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200008 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200008 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198986 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198986 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 15157754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15157754 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 15157754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15157754 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133379 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133379 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093286 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093286 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086257 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086257 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.117112 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117112 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.117112 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117112 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25823.843282 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25823.843282 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36213.395511 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36213.395511 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.491769 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.491769 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29181.556999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29181.556999 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1015,64 +1027,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838282 # number of writebacks -system.cpu.dcache.writebacks::total 838282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127187 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127187 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269448 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269448 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838111 # number of writebacks +system.cpu.dcache.writebacks::total 838111 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127232 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127232 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269462 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269462 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 396635 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396635 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 396635 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396635 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074429 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304251 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304251 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17296 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17296 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1378680 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378680 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1378680 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378680 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26906996250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26906996250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10272860843 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10272860843 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196930250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196930250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179857093 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37179857093 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179857093 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37179857093 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423313500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423313500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002790500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002790500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426104000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426104000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086477 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086477 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090951 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.inst 396694 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396694 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 396694 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396694 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074228 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074228 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304237 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304237 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17249 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1378465 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378465 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1378465 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378465 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26911701750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26911701750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10289625346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10289625346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196226500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196226500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37201327096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37201327096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37201327096 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37201327096 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003794000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003794000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3427189500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427189500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086242 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086242 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090941 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090941 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25052.132089 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25052.132089 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33821.084700 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33821.084700 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11376.108760 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 683e407e9..05acb9522 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,126 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903124 # Number of seconds simulated -sim_ticks 1903123778500 # Number of ticks simulated -final_tick 1903123778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.905068 # Number of seconds simulated +sim_ticks 1905067807000 # Number of ticks simulated +final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 103415 # Simulator instruction rate (inst/s) -host_op_rate 103415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3505224116 # Simulator tick rate (ticks/s) -host_mem_usage 322696 # Number of bytes of host memory used -host_seconds 542.94 # Real time elapsed on the host -sim_insts 56148221 # Number of instructions simulated -sim_ops 56148221 # Number of ops (including micro ops) simulated +host_inst_rate 162284 # Simulator instruction rate (inst/s) +host_op_rate 162284 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5403466257 # Simulator tick rate (ticks/s) +host_mem_usage 375680 # Number of bytes of host memory used +host_seconds 352.56 # Real time elapsed on the host +sim_insts 57215334 # Number of instructions simulated +sim_ops 57215334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 744192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24296448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 865344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24709248 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 238144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1067328 # Number of bytes read from this memory -system.physmem.bytes_read::total 26347072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 744192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 238144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5275328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 118912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 545600 # Number of bytes read from this memory +system.physmem.bytes_read::total 26240064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 865344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 118912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 984256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5157696 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7934656 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 379632 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7817024 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386082 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16677 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411673 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82427 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8525 # Number of read requests responded to by this memory +system.physmem.num_reads::total 410001 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 80589 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123979 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 391037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12766615 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 122141 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 454233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12970272 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 125133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 560830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13844119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 391037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 125133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2771931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1397349 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4169280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2771931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 391037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12766615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 125133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 560830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18013399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411673 # Number of read requests accepted -system.physmem.writeReqs 123979 # Number of write requests accepted -system.physmem.readBursts 411673 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123979 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26335040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue -system.physmem.bytesWritten 7932928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26347072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7934656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_read::cpu1.inst 62419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 286394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13773822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 454233 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 62419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2707356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1395923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4103279 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2707356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 454233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12970272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1396427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 62419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 286394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17877100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410001 # Number of read requests accepted +system.physmem.writeReqs 122141 # Number of write requests accepted +system.physmem.readBursts 410001 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122141 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26227648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12416 # Total number of bytes read from write queue +system.physmem.bytesWritten 7815104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26240064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7817024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3444 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25632 # Per bank write bursts -system.physmem.perBankRdBursts::1 25720 # Per bank write bursts -system.physmem.perBankRdBursts::2 26346 # Per bank write bursts -system.physmem.perBankRdBursts::3 25660 # Per bank write bursts -system.physmem.perBankRdBursts::4 25672 # Per bank write bursts -system.physmem.perBankRdBursts::5 25150 # Per bank write bursts -system.physmem.perBankRdBursts::6 25568 # Per bank write bursts -system.physmem.perBankRdBursts::7 25491 # Per bank write bursts -system.physmem.perBankRdBursts::8 25973 # Per bank write bursts -system.physmem.perBankRdBursts::9 26167 # Per bank write bursts -system.physmem.perBankRdBursts::10 25812 # Per bank write bursts -system.physmem.perBankRdBursts::11 25687 # Per bank write bursts -system.physmem.perBankRdBursts::12 26023 # Per bank write bursts -system.physmem.perBankRdBursts::13 25844 # Per bank write bursts -system.physmem.perBankRdBursts::14 25108 # Per bank write bursts -system.physmem.perBankRdBursts::15 25632 # Per bank write bursts -system.physmem.perBankWrBursts::0 8431 # Per bank write bursts -system.physmem.perBankWrBursts::1 7989 # Per bank write bursts -system.physmem.perBankWrBursts::2 8275 # Per bank write bursts -system.physmem.perBankWrBursts::3 7382 # Per bank write bursts -system.physmem.perBankWrBursts::4 7684 # Per bank write bursts -system.physmem.perBankWrBursts::5 7400 # Per bank write bursts -system.physmem.perBankWrBursts::6 7193 # Per bank write bursts -system.physmem.perBankWrBursts::7 7021 # Per bank write bursts -system.physmem.perBankWrBursts::8 7374 # Per bank write bursts -system.physmem.perBankWrBursts::9 7755 # Per bank write bursts -system.physmem.perBankWrBursts::10 7777 # Per bank write bursts -system.physmem.perBankWrBursts::11 7454 # Per bank write bursts -system.physmem.perBankWrBursts::12 8052 # Per bank write bursts -system.physmem.perBankWrBursts::13 8097 # Per bank write bursts -system.physmem.perBankWrBursts::14 7762 # Per bank write bursts -system.physmem.perBankWrBursts::15 8306 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6364 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25988 # Per bank write bursts +system.physmem.perBankRdBursts::1 25697 # Per bank write bursts +system.physmem.perBankRdBursts::2 25753 # Per bank write bursts +system.physmem.perBankRdBursts::3 25768 # Per bank write bursts +system.physmem.perBankRdBursts::4 25192 # Per bank write bursts +system.physmem.perBankRdBursts::5 25524 # Per bank write bursts +system.physmem.perBankRdBursts::6 25779 # Per bank write bursts +system.physmem.perBankRdBursts::7 25095 # Per bank write bursts +system.physmem.perBankRdBursts::8 25528 # Per bank write bursts +system.physmem.perBankRdBursts::9 25751 # Per bank write bursts +system.physmem.perBankRdBursts::10 25719 # Per bank write bursts +system.physmem.perBankRdBursts::11 25446 # Per bank write bursts +system.physmem.perBankRdBursts::12 25795 # Per bank write bursts +system.physmem.perBankRdBursts::13 25643 # Per bank write bursts +system.physmem.perBankRdBursts::14 25930 # Per bank write bursts +system.physmem.perBankRdBursts::15 25199 # Per bank write bursts +system.physmem.perBankWrBursts::0 8301 # Per bank write bursts +system.physmem.perBankWrBursts::1 7506 # Per bank write bursts +system.physmem.perBankWrBursts::2 7807 # Per bank write bursts +system.physmem.perBankWrBursts::3 7337 # Per bank write bursts +system.physmem.perBankWrBursts::4 6902 # Per bank write bursts +system.physmem.perBankWrBursts::5 7063 # Per bank write bursts +system.physmem.perBankWrBursts::6 7447 # Per bank write bursts +system.physmem.perBankWrBursts::7 6982 # Per bank write bursts +system.physmem.perBankWrBursts::8 7245 # Per bank write bursts +system.physmem.perBankWrBursts::9 7339 # Per bank write bursts +system.physmem.perBankWrBursts::10 7570 # Per bank write bursts +system.physmem.perBankWrBursts::11 7510 # Per bank write bursts +system.physmem.perBankWrBursts::12 8378 # Per bank write bursts +system.physmem.perBankWrBursts::13 8362 # Per bank write bursts +system.physmem.perBankWrBursts::14 8512 # Per bank write bursts +system.physmem.perBankWrBursts::15 7850 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 1903119235000 # Total gap between requests +system.physmem.totGap 1905063366000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411673 # Read request sizes (log2) +system.physmem.readPktSize::6 410001 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123979 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -161,357 +161,367 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64910 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 527.930488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.008348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.202697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14944 23.02% 23.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11454 17.65% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5213 8.03% 48.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2920 4.50% 53.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2279 3.51% 56.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1787 2.75% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1551 2.39% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1716 2.64% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23046 35.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64910 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5635 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.021650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2812.727565 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5632 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64430 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 528.357101 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.789036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.784578 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14909 23.14% 23.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11361 17.63% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5102 7.92% 48.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2869 4.45% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2286 3.55% 56.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1687 2.62% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1558 2.42% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1655 2.57% 64.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23003 35.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64430 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.305712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2843.118152 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5512 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5635 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.996806 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.958563 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.289473 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4843 85.94% 85.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 143 2.54% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.18% 88.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 227 4.03% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 45 0.80% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.07% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 10 0.18% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.18% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 34 0.60% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.11% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.16% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 41 0.73% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 13 0.23% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.04% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 176 3.12% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.09% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.05% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.11% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 6 0.11% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 10 0.18% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.11% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5635 # Writes before turning the bus around for reads -system.physmem.totQLat 3887945250 # Total ticks spent queuing -system.physmem.totMemAccLat 11603289000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2057425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9448.57 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5515 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5515 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.141614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.970992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.024334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4751 86.15% 86.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 123 2.23% 88.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.27% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 231 4.19% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 39 0.71% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 12 0.22% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 8 0.15% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.07% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.42% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.05% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 94.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 28 0.51% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 10 0.18% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 17 0.31% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 177 3.21% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.05% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.07% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.04% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.09% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.09% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.15% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5515 # Writes before turning the bus around for reads +system.physmem.totQLat 3875472500 # Total ticks spent queuing +system.physmem.totMemAccLat 11559353750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9456.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28198.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28206.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing -system.physmem.readRowHits 371100 # Number of row buffer hits during reads -system.physmem.writeRowHits 99427 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.20 # Row buffer hit rate for writes -system.physmem.avgGap 3552902.32 # Average gap between requests -system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1802319562500 # Time in different power states -system.physmem.memoryStateTime::REF 63549460000 # Time in different power states +system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.10 # Average write queue length when enqueuing +system.physmem.readRowHits 369467 # Number of row buffer hits during reads +system.physmem.writeRowHits 98020 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.25 # Row buffer hit rate for writes +system.physmem.avgGap 3579990.62 # Average gap between requests +system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1804432107750 # Time in different power states +system.physmem.memoryStateTime::REF 63614200000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37254262500 # Time in different power states +system.physmem.memoryStateTime::ACT 37016700250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18054612 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296849 # Transaction distribution -system.membus.trans_dist::ReadResp 296569 # Transaction distribution -system.membus.trans_dist::WriteReq 12351 # Transaction distribution -system.membus.trans_dist::WriteResp 12351 # Transaction distribution -system.membus.trans_dist::Writeback 82427 # Transaction distribution +system.membus.trans_dist::ReadReq 296853 # Transaction distribution +system.membus.trans_dist::ReadResp 296773 # Transaction distribution +system.membus.trans_dist::WriteReq 13665 # Transaction distribution +system.membus.trans_dist::WriteResp 13665 # Transaction distribution +system.membus.trans_dist::Writeback 80589 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5284 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1479 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3444 # Transaction distribution -system.membus.trans_dist::ReadExReq 122594 # Transaction distribution -system.membus.trans_dist::ReadExResp 122459 # Transaction distribution -system.membus.trans_dist::BadAddressError 280 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 916085 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 955737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1039031 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68194 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31621440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31689634 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34349922 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34349922 # Total data (bytes) -system.membus.snoop_data_through_bus 10240 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35504996 # Layer occupancy (ticks) +system.membus.trans_dist::UpgradeReq 14563 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9639 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6364 # Transaction distribution +system.membus.trans_dist::ReadExReq 121274 # Transaction distribution +system.membus.trans_dist::ReadExResp 120582 # Transaction distribution +system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1056989 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78682 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31396800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31475482 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34135770 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 18692 # Total snoops (count) +system.membus.snoop_fanout::samples 557285 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 557285 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 557285 # Request fanout histogram +system.membus.reqLayer0.occupancy 40450499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1560042750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1545398747 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 374000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 102000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3834491323 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3825672402 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43141738 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43153245 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 345839 # number of replacements -system.l2c.tags.tagsinuse 65302.356632 # Cycle average of tags in use -system.l2c.tags.total_refs 2646364 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411006 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.438748 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7093732750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53566.898021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4193.415796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5564.276304 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1386.450480 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 591.316031 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.817366 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063986 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.084904 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021156 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996435 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2289 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6029 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50524 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27707761 # Number of tag accesses -system.l2c.tags.data_accesses 27707761 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 751132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 546267 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 350558 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 278844 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1926801 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 841911 # number of Writeback hits -system.l2c.Writeback_hits::total 841911 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 128 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 75 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 203 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 140399 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48308 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 188707 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 751132 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 686666 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 350558 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 327152 # number of demand (read+write) hits -system.l2c.demand_hits::total 2115508 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 751132 # number of overall hits -system.l2c.overall_hits::cpu0.data 686666 # number of overall hits -system.l2c.overall_hits::cpu1.inst 350558 # number of overall hits -system.l2c.overall_hits::cpu1.data 327152 # number of overall hits -system.l2c.overall_hits::total 2115508 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11641 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272205 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3725 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1926 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289497 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2575 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 542 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3117 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 63 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 103 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 107603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15017 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122620 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11641 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 379808 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3725 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16943 # number of demand (read+write) misses -system.l2c.demand_misses::total 412117 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11641 # number of overall misses -system.l2c.overall_misses::cpu0.data 379808 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3725 # number of overall misses -system.l2c.overall_misses::cpu1.data 16943 # number of overall misses -system.l2c.overall_misses::total 412117 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 889120500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17862600250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 290708250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 148179250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19190608250 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 882962 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1281445 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2164407 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 245491 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187992 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 433483 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8878273882 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1456523709 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10334797591 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 889120500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26740874132 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 290708250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1604702959 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29525405841 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 889120500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26740874132 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 290708250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1604702959 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29525405841 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 762773 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 818472 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 354283 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 280770 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2216298 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 841911 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 841911 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2703 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 617 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3320 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 99 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 140 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 239 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 248002 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 63325 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 311327 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 762773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1066474 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 354283 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 344095 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2527625 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 762773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1066474 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 354283 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 344095 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2527625 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015261 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.332577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006860 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.130622 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952645 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.878444 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.938855 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636364 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.735714 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.694561 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.433880 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.237142 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.393862 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015261 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.356134 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010514 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.049239 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.163045 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015261 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.356134 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010514 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.049239 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.163045 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76378.360966 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65621.866792 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78042.483221 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76936.266874 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 66289.489183 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 342.897864 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2364.289668 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 694.387873 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3896.682540 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1825.165049 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2611.343373 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82509.538600 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96991.656722 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84283.131553 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76378.360966 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70406.295107 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78042.483221 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 94711.854984 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71643.261115 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76378.360966 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70406.295107 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78042.483221 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 94711.854984 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71643.261115 # average overall miss latency +system.l2c.tags.replacements 344236 # number of replacements +system.l2c.tags.tagsinuse 65255.823465 # Cycle average of tags in use +system.l2c.tags.total_refs 2587778 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 409374 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.321305 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53392.763161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5322.213179 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6227.888257 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 220.740542 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 92.218326 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.814709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081211 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.095030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003368 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001407 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995725 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65138 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3694 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4797 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4255 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52162 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.993927 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27098951 # Number of tag accesses +system.l2c.tags.data_accesses 27098951 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 802459 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 696077 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 311437 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 94339 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1904312 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 804733 # number of Writeback hits +system.l2c.Writeback_hits::total 804733 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 597 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 138280 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 34809 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173089 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 802459 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 834357 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 311437 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 129148 # number of demand (read+write) hits +system.l2c.demand_hits::total 2077401 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 802459 # number of overall hits +system.l2c.overall_hits::cpu0.data 834357 # number of overall hits +system.l2c.overall_hits::cpu1.inst 311437 # number of overall hits +system.l2c.overall_hits::cpu1.data 129148 # number of overall hits +system.l2c.overall_hits::total 2077401 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13534 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273199 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1862 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 907 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289502 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2870 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1562 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4432 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 736 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 745 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1481 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113374 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7659 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121033 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13534 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 386573 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1862 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8566 # number of demand (read+write) misses +system.l2c.demand_misses::total 410535 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13534 # number of overall misses +system.l2c.overall_misses::cpu0.data 386573 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1862 # number of overall misses +system.l2c.overall_misses::cpu1.data 8566 # number of overall misses +system.l2c.overall_misses::total 410535 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1040639500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17951579250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 147621500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 80108498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19219948748 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1096455 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 8459610 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9556065 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1292445 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162993 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1455438 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9386780343 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 797590458 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10184370801 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1040639500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 27338359593 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 147621500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 877698956 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 29404319549 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1040639500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 27338359593 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 147621500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 877698956 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29404319549 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 815993 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 969276 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 313299 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 95246 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2193814 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 804733 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 804733 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3036 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1993 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5029 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 788 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 771 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1559 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 251654 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 42468 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 294122 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 815993 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1220930 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 313299 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 137714 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2487936 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 815993 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1220930 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 313299 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 137714 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2487936 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016586 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.281859 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005943 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.009523 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.131963 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945323 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783743 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.881289 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934010 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.966278 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.949968 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.450515 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.180348 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.411506 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016586 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.316622 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005943 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.062201 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.165010 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016586 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.316622 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005943 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.062201 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.165010 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76890.756613 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 65708.802924 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79281.149302 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 88322.489526 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 66389.692465 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 382.040070 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5415.883483 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2156.151850 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1756.039402 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 218.782550 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 982.740041 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82794.823707 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 104137.675676 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84145.404980 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76890.756613 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70719.785378 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 79281.149302 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 102463.104833 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71624.391462 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76890.756613 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70719.785378 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 79281.149302 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 102463.104833 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71624.391462 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,8 +530,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 82427 # number of writebacks -system.l2c.writebacks::total 82427 # number of writebacks +system.l2c.writebacks::writebacks 80589 # number of writebacks +system.l2c.writebacks::total 80589 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits @@ -534,111 +544,111 @@ system.l2c.overall_mshr_hits::cpu0.inst 13 # nu system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 11628 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 272204 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3721 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1926 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289479 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2575 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 542 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3117 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 63 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 103 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 166 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 107603 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 15017 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122620 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 11628 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 379807 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3721 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 16943 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 412099 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 11628 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 379807 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3721 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 16943 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 412099 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 741621000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14467164750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 243575500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 151890250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15604251500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25805570 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5431039 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 31236609 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 646561 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1036098 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1682659 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7566064618 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1272103789 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8838168407 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 741621000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 22033229368 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 243575500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1423994039 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 24442419907 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 741621000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 22033229368 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 243575500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1423994039 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 24442419907 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 930400500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 458814500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389215000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1575945000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 887867500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2463812500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2506345500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1346682000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3853027500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.332576 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006860 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.130614 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.952645 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.878444 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.938855 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636364 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.694561 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.433880 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.237142 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.393862 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.356133 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.049239 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.163038 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.356133 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.049239 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.163038 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53148.244515 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78863.058152 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 53904.606206 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.580583 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.367159 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.369586 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10262.873016 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10059.203883 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10136.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70314.625224 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84710.913565 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72077.706793 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58011.646357 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84046.157056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59312.009753 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58011.646357 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84046.157056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59312.009753 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13521 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273198 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1858 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 907 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289484 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2870 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1562 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4432 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 736 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 745 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1481 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 113374 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7659 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121033 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13521 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 386572 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1858 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8566 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 410517 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13521 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 386572 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1858 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8566 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 410517 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 869263000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14546768250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 123935250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 68927498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15608893998 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 28724364 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15649033 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 44373397 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7383232 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 7461237 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 14844469 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8003168657 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 703372040 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8706540697 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 869263000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 22549936907 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 123935250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 772299538 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24315434695 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 869263000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 22549936907 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 123935250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 772299538 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24315434695 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1361646000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27086000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1388732000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2074085500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 667819500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2741905000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3435731500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 694905500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4130637000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.281858 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.009523 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.131955 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945323 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783743 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.881289 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934010 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966278 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.949968 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.450515 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.180348 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.411506 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.316621 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.062201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165003 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.316621 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.062201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165003 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53246.247227 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75995.036384 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53919.712309 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.489199 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.587068 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.048060 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.565217 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.083221 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10023.274139 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70590.864369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91836.015146 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71935.263085 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58333.083894 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 90158.713285 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59231.249120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58333.083894 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 90158.713285 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59231.249120 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -649,54 +659,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.219567 # Cycle average of tags in use +system.iocache.tags.replacements 41697 # number of replacements +system.iocache.tags.tagsinuse 0.496947 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710336549000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.219567 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.013723 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.013723 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710336805000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.496947 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031059 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031059 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.tags.tag_accesses 375577 # Number of tag accesses +system.iocache.tags.data_accesses 375577 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21364383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21364383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21364383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21364383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21364383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21364383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 2 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 2 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses +system.iocache.demand_misses::total 177 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 177 # number of overall misses +system.iocache.overall_misses::total 177 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21586383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21586383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21586383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21586383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21586383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21586383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41554 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41554 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000048 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000048 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122082.188571 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122082.188571 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122082.188571 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121956.966102 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121956.966102 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121956.966102 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121956.966102 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,38 +719,38 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12263383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12263383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2507056568 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2507056568 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12263383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12263383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12263383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12263383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12381383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12381383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512854560 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512854560 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12381383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12381383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -750,35 +764,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 13702956 # Number of BP lookups -system.cpu0.branchPred.condPredicted 11991857 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 276088 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8588922 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4683455 # Number of BTB hits +system.cpu0.branchPred.lookups 14962614 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13045209 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 300344 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9143692 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5116520 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 54.529020 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 677984 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 15448 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 55.956828 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 756655 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 14726 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7950804 # DTB read hits -system.cpu0.dtb.read_misses 30543 # DTB read misses -system.cpu0.dtb.read_acv 546 # DTB read access violations -system.cpu0.dtb.read_accesses 683229 # DTB read accesses -system.cpu0.dtb.write_hits 5159026 # DTB write hits -system.cpu0.dtb.write_misses 6845 # DTB write misses -system.cpu0.dtb.write_acv 353 # DTB write access violations -system.cpu0.dtb.write_accesses 234573 # DTB write accesses -system.cpu0.dtb.data_hits 13109830 # DTB hits -system.cpu0.dtb.data_misses 37388 # DTB misses -system.cpu0.dtb.data_acv 899 # DTB access violations -system.cpu0.dtb.data_accesses 917802 # DTB accesses -system.cpu0.itb.fetch_hits 1312718 # ITB hits -system.cpu0.itb.fetch_misses 29261 # ITB misses -system.cpu0.itb.fetch_acv 629 # ITB acv -system.cpu0.itb.fetch_accesses 1341979 # ITB accesses +system.cpu0.dtb.read_hits 8668714 # DTB read hits +system.cpu0.dtb.read_misses 31568 # DTB read misses +system.cpu0.dtb.read_acv 533 # DTB read access violations +system.cpu0.dtb.read_accesses 683834 # DTB read accesses +system.cpu0.dtb.write_hits 5507711 # DTB write hits +system.cpu0.dtb.write_misses 6832 # DTB write misses +system.cpu0.dtb.write_acv 377 # DTB write access violations +system.cpu0.dtb.write_accesses 235007 # DTB write accesses +system.cpu0.dtb.data_hits 14176425 # DTB hits +system.cpu0.dtb.data_misses 38400 # DTB misses +system.cpu0.dtb.data_acv 910 # DTB access violations +system.cpu0.dtb.data_accesses 918841 # DTB accesses +system.cpu0.itb.fetch_hits 1355401 # ITB hits +system.cpu0.itb.fetch_misses 29256 # ITB misses +system.cpu0.itb.fetch_acv 621 # ITB acv +system.cpu0.itb.fetch_accesses 1384657 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -791,304 +805,305 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 99665250 # number of cpu cycles simulated +system.cpu0.numCycles 108456707 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 22511576 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 60582407 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13702956 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5361439 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 70984108 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 933480 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 621 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 27412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1463366 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 292819 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7109889 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 200075 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 95746858 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.632735 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.928110 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24325754 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 66694894 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 14962614 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5873175 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 76828249 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1001726 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 825 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30281 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1454626 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 459540 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 204 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7777949 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 213350 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103600342 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.643771 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.943909 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 84335489 88.08% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 757900 0.79% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1598110 1.67% 90.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 658612 0.69% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2290747 2.39% 93.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 510807 0.53% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 540667 0.56% 94.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 744782 0.78% 95.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4309744 4.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 91056774 87.89% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 810107 0.78% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1760430 1.70% 90.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 739408 0.71% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2516394 2.43% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557837 0.54% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 633248 0.61% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 717698 0.69% 95.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4808446 4.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 95746858 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.137490 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.607859 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18154184 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 68366814 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7221268 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1568077 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 436514 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 432928 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 30567 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53177978 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 98719 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 436514 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18925396 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 44877173 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16564638 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 7942906 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7000229 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 51314401 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 200370 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1702156 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 121650 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3596195 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 34369689 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 62476617 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 62360377 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 107565 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30276917 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4092764 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1298231 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 191875 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11393500 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8037568 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5366781 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1135735 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 800748 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 45795204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1644687 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 45103865 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 41971 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5328763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2477826 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1134880 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 95746858 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.471074 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.201865 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103600342 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.137959 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614945 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19762809 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 73625982 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8017389 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1725855 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 468306 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 492047 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33030 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 58728782 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 102789 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 468306 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 20585060 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48251734 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17899835 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8819055 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7576350 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56729728 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 201548 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2018005 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 142949 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3756211 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 38050244 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 69305662 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69181835 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 114815 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33467059 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4583177 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1358842 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 197413 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12487165 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8791454 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5770533 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1295730 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 947864 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50680779 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1726956 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49798033 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52306 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5972660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2859786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1187974 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103600342 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.480674 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.214257 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 76985468 80.41% 80.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8252195 8.62% 89.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3430688 3.58% 92.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2350675 2.46% 95.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2374207 2.48% 97.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1175968 1.23% 98.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 779493 0.81% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 300669 0.31% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 97495 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 83011266 80.13% 80.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8965198 8.65% 88.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3720190 3.59% 92.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2652497 2.56% 94.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2683429 2.59% 97.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1272361 1.23% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 837773 0.81% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 348219 0.34% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109409 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 95746858 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103600342 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 143906 17.61% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 398143 48.73% 66.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 274956 33.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 174041 19.05% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 435557 47.67% 66.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 304020 33.28% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30829458 68.35% 68.36% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46395 0.10% 68.46% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 26948 0.06% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8252345 18.30% 86.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5217820 11.57% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 725236 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34383436 69.05% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54432 0.11% 69.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 27661 0.06% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8987932 18.05% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5577936 11.20% 98.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 760973 1.53% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 45103865 # Type of FU issued -system.cpu0.iq.rate 0.452554 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 817005 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018114 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 186342910 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 52562719 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43916640 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 470653 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 221373 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 216432 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 45663938 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 253152 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 522094 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49798033 # Type of FU issued +system.cpu0.iq.rate 0.459151 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 913618 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018346 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203658933 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 58161397 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48529720 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 503398 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 236532 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 231367 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50437037 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 270834 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 558638 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 946690 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4799 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15752 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 387148 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1034329 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17854 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 485625 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13610 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 357638 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18828 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348593 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 436514 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 41413967 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1424350 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50298451 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 103444 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8037568 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5366781 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1456887 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 31578 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1238658 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15752 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 134081 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 309122 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 443203 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 44677716 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8001376 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 426148 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 468306 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 44263410 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1515089 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 55600538 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 120472 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8791454 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5770533 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1526368 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 47186 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1245112 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17854 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151677 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 326896 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 478573 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49327282 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8721913 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 470750 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2858560 # number of nop insts executed -system.cpu0.iew.exec_refs 13178604 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7039370 # Number of branches executed -system.cpu0.iew.exec_stores 5177228 # Number of stores executed -system.cpu0.iew.exec_rate 0.448278 # Inst execution rate -system.cpu0.iew.wb_sent 44227196 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44133072 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22691402 # num instructions producing a value -system.cpu0.iew.wb_consumers 31140086 # num instructions consuming a value +system.cpu0.iew.exec_nop 3192803 # number of nop insts executed +system.cpu0.iew.exec_refs 14249477 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7854369 # Number of branches executed +system.cpu0.iew.exec_stores 5527564 # Number of stores executed +system.cpu0.iew.exec_rate 0.454811 # Inst execution rate +system.cpu0.iew.wb_sent 48871282 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48761087 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25232648 # num instructions producing a value +system.cpu0.iew.wb_consumers 34850080 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.442813 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.728688 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.724034 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5846321 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 509807 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 407712 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 94708833 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.468364 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.405169 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6529157 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 538982 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 437949 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102449449 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.477940 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.411753 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 79035549 83.45% 83.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6314508 6.67% 90.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3292930 3.48% 93.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1802282 1.90% 95.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1366338 1.44% 96.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 489382 0.52% 97.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 366889 0.39% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 390234 0.41% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1650721 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 85074848 83.04% 83.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6905483 6.74% 89.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3794087 3.70% 93.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1998795 1.95% 95.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1509892 1.47% 96.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 553563 0.54% 97.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 413229 0.40% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 408476 0.40% 98.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1791076 1.75% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 94708833 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 44358216 # Number of instructions committed -system.cpu0.commit.committedOps 44358216 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102449449 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48964739 # Number of instructions committed +system.cpu0.commit.committedOps 48964739 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12070511 # Number of memory references committed -system.cpu0.commit.loads 7090878 # Number of loads committed -system.cpu0.commit.membars 170277 # Number of memory barriers committed -system.cpu0.commit.branches 6663650 # Number of branches committed -system.cpu0.commit.fp_insts 213529 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 41141903 # Number of committed integer instructions. -system.cpu0.commit.function_calls 549728 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2498518 5.63% 5.63% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 28814427 64.96% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 45393 0.10% 70.69% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 26477 0.06% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7261155 16.37% 87.13% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 4985127 11.24% 98.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 725236 1.63% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13042033 # Number of memory references committed +system.cpu0.commit.loads 7757125 # Number of loads committed +system.cpu0.commit.membars 182252 # Number of memory barriers committed +system.cpu0.commit.branches 7421354 # Number of branches committed +system.cpu0.commit.fp_insts 228314 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45387875 # Number of committed integer instructions. +system.cpu0.commit.function_calls 614232 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2794177 5.71% 5.71% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32097051 65.55% 71.26% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 53183 0.11% 71.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 27190 0.06% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7939377 16.21% 87.64% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5290905 10.81% 98.45% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 760973 1.55% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 44358216 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1650721 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 48964739 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1791076 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 143064224 # The number of ROB reads -system.cpu0.rob.rob_writes 101447849 # The number of ROB writes -system.cpu0.timesIdled 414726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3918392 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3706577488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41863465 # Number of Instructions Simulated -system.cpu0.committedOps 41863465 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.380721 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.380721 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.420041 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.420041 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 58777310 # number of integer regfile reads -system.cpu0.int_regfile_writes 31962259 # number of integer regfile writes -system.cpu0.fp_regfile_reads 106639 # number of floating regfile reads -system.cpu0.fp_regfile_writes 106808 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1588469 # number of misc regfile reads -system.cpu0.misc_regfile_writes 729535 # number of misc regfile writes +system.cpu0.rob.rob_reads 155949601 # The number of ROB reads +system.cpu0.rob.rob_writes 112132496 # The number of ROB writes +system.cpu0.timesIdled 444606 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4856365 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3701678908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46174329 # Number of Instructions Simulated +system.cpu0.committedOps 46174329 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.348853 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.348853 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.425740 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.425740 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65048250 # number of integer regfile reads +system.cpu0.int_regfile_writes 35377381 # number of integer regfile writes +system.cpu0.fp_regfile_reads 113752 # number of floating regfile reads +system.cpu0.fp_regfile_writes 114375 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1675774 # number of misc regfile reads +system.cpu0.misc_regfile_writes 759002 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1120,50 +1135,61 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 115690704 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2250904 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2250609 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 841911 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2231724 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2231628 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13665 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13665 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 804733 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5326 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6878 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 312265 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 312265 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 280 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1525692 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2740000 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 708608 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1000724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5975024 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48817472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 104660497 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22674112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39558737 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 215710818 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 215700578 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4473152 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5085967365 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeReq 14709 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9717 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 24426 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295921 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295921 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1632137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3219560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 626624 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 407513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5885834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52223552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123671600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20051136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14868394 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 210814682 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 92075 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3391171 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012307 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110253 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3349435 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41736 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3391171 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4911486557 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 720000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3437989936 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3677796473 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4906988127 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5655554210 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1597018302 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1411093549 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1654443775 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1434388 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7370 # Transaction distribution -system.iobus.trans_dist::ReadResp 7370 # Transaction distribution -system.iobus.trans_dist::WriteReq 53903 # Transaction distribution -system.iobus.trans_dist::WriteResp 53903 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 701201756 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 55215 # Transaction distribution +system.iobus.trans_dist::WriteResp 55217 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 2 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 464 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1174,30 +1200,29 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39092 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122546 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68194 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729818 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729818 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9847000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 41714 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 78682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2740322 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12481000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 347000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1217,267 +1242,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374411689 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374418188 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26741000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28049000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42019262 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42021755 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 762211 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.848890 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6309809 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 762721 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.272762 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26485928250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.848890 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993845 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7872808 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7872808 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6309809 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6309809 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6309809 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6309809 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6309809 # number of overall hits -system.cpu0.icache.overall_hits::total 6309809 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 800080 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 800080 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 800080 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 800080 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 800080 # number of overall misses -system.cpu0.icache.overall_misses::total 800080 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11341096711 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11341096711 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11341096711 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11341096711 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11341096711 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11341096711 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7109889 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7109889 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7109889 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7109889 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7109889 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7109889 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112531 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.112531 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112531 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.112531 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112531 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.112531 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14174.953393 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14174.953393 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3387 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 815495 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.595712 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6922237 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 816007 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.483061 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485869250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.595712 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995304 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995304 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 411 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8594091 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8594091 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6922237 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6922237 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6922237 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6922237 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6922237 # number of overall hits +system.cpu0.icache.overall_hits::total 6922237 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 855710 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 855710 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 855710 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 855710 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 855710 # number of overall misses +system.cpu0.icache.overall_misses::total 855710 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12231378721 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12231378721 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12231378721 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12231378721 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12231378721 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12231378721 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7777947 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7777947 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7777947 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7777947 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7777947 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7777947 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110017 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110017 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110017 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110017 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110017 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110017 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14293.836371 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14293.836371 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14293.836371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14293.836371 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4554 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 181 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.907407 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.160221 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37161 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 37161 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37161 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 37161 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37161 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 37161 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 762919 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 762919 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 762919 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 762919 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 762919 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 762919 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9350852559 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9350852559 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9350852559 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9350852559 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9350852559 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9350852559 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.107304 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.107304 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.107304 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39566 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 39566 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 39566 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 39566 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 39566 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 39566 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 816144 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 816144 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 816144 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 816144 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 816144 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 816144 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10088624022 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10088624022 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10088624022 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10088624022 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10088624022 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10088624022 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104931 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.104931 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.104931 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12361.328420 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1069035 # number of replacements -system.cpu0.dcache.tags.tagsinuse 482.779727 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9141371 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1069547 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.546956 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1223787 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.953471 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9930066 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1224299 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.110818 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.779727 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942929 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.942929 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.953471 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988190 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988190 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 49546788 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 49546788 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5665393 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5665393 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3152024 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3152024 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147109 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147109 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 170256 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 170256 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8817417 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8817417 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8817417 # number of overall hits -system.cpu0.dcache.overall_hits::total 8817417 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1322171 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1322171 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1644281 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1644281 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16610 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16610 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2966452 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2966452 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2966452 # number of overall misses -system.cpu0.dcache.overall_misses::total 2966452 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36169344894 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36169344894 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74324803897 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 74324803897 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 267182493 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 267182493 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4788059 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4788059 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 110494148791 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 110494148791 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6987564 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6987564 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4796305 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4796305 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 163719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 171022 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 171022 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11783869 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11783869 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11783869 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11783869 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.189218 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.189218 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342822 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.342822 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101454 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101454 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004479 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004479 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251738 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.251738 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251738 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.251738 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27356.026485 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6250.729765 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6250.729765 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3702426 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3454 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 160595 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 88 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.054429 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 39.250000 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 53654077 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 53654077 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6167393 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6167393 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3426848 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3426848 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 149101 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 149101 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171294 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171294 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9594241 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9594241 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9594241 # number of overall hits +system.cpu0.dcache.overall_hits::total 9594241 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1498647 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1498647 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1667216 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1667216 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19081 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19081 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4721 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4721 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3165863 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3165863 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3165863 # number of overall misses +system.cpu0.dcache.overall_misses::total 3165863 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39188841077 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39188841077 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77581958562 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77581958562 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288599741 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 288599741 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35650235 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 35650235 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 116770799639 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 116770799639 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 116770799639 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 116770799639 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7666040 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7666040 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5094064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5094064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168182 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 168182 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 176015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12760104 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12760104 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12760104 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12760104 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195492 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.195492 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327286 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.327286 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026822 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026822 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248106 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248106 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248106 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248106 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26149.480883 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26149.480883 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46533.837584 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46533.837584 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15124.979875 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15124.979875 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7551.416014 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7551.416014 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36884.350220 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36884.350220 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3791444 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2983 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 159835 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.720987 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 34.287356 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 568073 # number of writebacks -system.cpu0.dcache.writebacks::total 568073 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 499697 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 499697 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1402831 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1402831 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1902528 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1902528 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1902528 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1902528 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 822474 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 822474 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 241450 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 241450 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12284 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12284 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1063924 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1063924 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1063924 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1063924 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24909734008 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24909734008 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10782476086 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10782476086 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 145144507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145144507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3254941 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3254941 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35692210094 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35692210094 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35692210094 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35692210094 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 992378000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 992378000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1672126998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1672126998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2664504998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2664504998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117705 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117705 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075031 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075031 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004479 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004479 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090286 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090286 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4249.270235 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4249.270235 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 710527 # number of writebacks +system.cpu0.dcache.writebacks::total 710527 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 518299 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 518299 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1417662 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1417662 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4443 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4443 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1935961 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1935961 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1935961 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1935961 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 980348 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 980348 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249554 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249554 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1229902 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1229902 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1229902 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1229902 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27067717433 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27067717433 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11277928082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11277928082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147839258 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147839258 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26206765 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26206765 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38345645515 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38345645515 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38345645515 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38345645515 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1453124500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1453124500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2199080998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2199080998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3652205498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3652205498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127882 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127882 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026822 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026822 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096387 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096387 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27610.315350 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27610.315350 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45192.335454 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45192.335454 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10099.689712 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10099.689712 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5551.104639 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5551.104639 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1485,35 +1510,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 5770916 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5004196 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 122577 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3556553 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1526133 # Number of BTB hits +system.cpu1.branchPred.lookups 4639832 # Number of BP lookups +system.cpu1.branchPred.condPredicted 4063901 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 82203 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2874870 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1132301 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 42.910453 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 301064 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7748 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 39.386164 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 224009 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7064 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3015540 # DTB read hits -system.cpu1.dtb.read_misses 12269 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 293761 # DTB read accesses -system.cpu1.dtb.write_hits 1836726 # DTB write hits -system.cpu1.dtb.write_misses 2353 # DTB write misses -system.cpu1.dtb.write_acv 39 # DTB write access violations -system.cpu1.dtb.write_accesses 109652 # DTB write accesses -system.cpu1.dtb.data_hits 4852266 # DTB hits -system.cpu1.dtb.data_misses 14622 # DTB misses -system.cpu1.dtb.data_acv 44 # DTB access violations -system.cpu1.dtb.data_accesses 403413 # DTB accesses -system.cpu1.itb.fetch_hits 632341 # ITB hits -system.cpu1.itb.fetch_misses 5352 # ITB misses -system.cpu1.itb.fetch_acv 51 # ITB acv -system.cpu1.itb.fetch_accesses 637693 # ITB accesses +system.cpu1.dtb.read_hits 2413283 # DTB read hits +system.cpu1.dtb.read_misses 10075 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 292262 # DTB read accesses +system.cpu1.dtb.write_hits 1597058 # DTB write hits +system.cpu1.dtb.write_misses 2093 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 110264 # DTB write accesses +system.cpu1.dtb.data_hits 4010341 # DTB hits +system.cpu1.dtb.data_misses 12168 # DTB misses +system.cpu1.dtb.data_acv 43 # DTB access violations +system.cpu1.dtb.data_accesses 402526 # DTB accesses +system.cpu1.itb.fetch_hits 608432 # ITB hits +system.cpu1.itb.fetch_misses 5602 # ITB misses +system.cpu1.itb.fetch_acv 65 # ITB acv +system.cpu1.itb.fetch_accesses 614034 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1526,554 +1551,552 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 26335588 # number of cpu cycles simulated +system.cpu1.numCycles 19085086 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9800268 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 22981944 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5770916 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1827197 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14019681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 419510 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 307 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 208449 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 196331 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2522136 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 89875 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 24458620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.939626 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.331670 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8490084 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17874574 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4639832 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1356310 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9216388 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 327612 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 219924 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 67319 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1967111 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 67009 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 18184335 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.982966 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.394246 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20375648 83.31% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 230665 0.94% 84.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 464859 1.90% 86.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 295118 1.21% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 600413 2.45% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 204861 0.84% 90.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 257669 1.05% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 270860 1.11% 92.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1758527 7.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15065350 82.85% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 205923 1.13% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 307986 1.69% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 226074 1.24% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 391185 2.15% 89.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151633 0.83% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 170482 0.94% 90.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 296956 1.63% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1368746 7.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 24458620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.219130 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.872657 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8213195 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 12716086 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2925937 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 406668 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 196733 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 189397 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 13167 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 19294426 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 40930 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 196733 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8443455 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3954170 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 7253500 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 3074788 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1535972 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 18421784 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 5378 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 385976 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 36959 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 551165 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 12165906 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 21959681 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 21890085 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 63650 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 10221482 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1944424 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 582778 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 59316 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3316426 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3128488 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1940399 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 395849 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 259099 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 16224994 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 722304 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 15758531 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 26415 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2553169 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1203962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 524576 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 24458620 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644294 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.366216 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 18184335 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.243113 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.936573 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6979571 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8518725 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2274233 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 256003 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 155802 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 137194 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8084 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14619784 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 26597 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 155802 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7159934 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 614392 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6924569 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2350603 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 979033 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13886683 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 9133 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 71770 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16856 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 365854 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9047331 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16422939 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16337871 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 78141 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7835755 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1211576 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 562751 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 58900 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2353285 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2494844 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1679253 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 277357 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 156260 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12201401 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 661557 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11978627 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22551 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1735034 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 788886 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 473891 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 18184335 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.658733 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.375592 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 17964380 73.45% 73.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2773024 11.34% 84.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1191873 4.87% 89.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 895755 3.66% 93.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 840464 3.44% 96.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 400907 1.64% 98.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 238226 0.97% 99.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 113179 0.46% 99.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 40812 0.17% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 13164849 72.40% 72.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2231541 12.27% 84.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 929377 5.11% 89.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 639609 3.52% 93.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 582340 3.20% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 317160 1.74% 98.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 211313 1.16% 99.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 78701 0.43% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 29445 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 24458620 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 18184335 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 56470 15.54% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 184321 50.72% 66.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 122598 33.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24291 8.14% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 162499 54.43% 62.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 111756 37.43% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 10371294 65.81% 65.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 24284 0.15% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11773 0.07% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3139820 19.92% 86.00% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1865147 11.84% 97.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 340936 2.16% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7464610 62.32% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 20078 0.17% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 12377 0.10% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2524426 21.07% 83.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1623488 13.55% 97.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 328371 2.74% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 15758531 # Type of FU issued -system.cpu1.iq.rate 0.598374 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 363389 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023060 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 56111313 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 19387392 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 15262127 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 254173 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 119441 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 117263 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 15982004 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 136398 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 157695 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11978627 # Type of FU issued +system.cpu1.iq.rate 0.627643 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 298546 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.024923 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 42145115 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14453685 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11556214 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 317571 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 148430 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 146304 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12102736 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 170919 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 117615 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 453605 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1302 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 6552 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 197079 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 314973 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1097 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4259 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 145447 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5589 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 74646 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 424 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 56672 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 196733 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 3102898 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 407577 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 17959821 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 47400 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3128488 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1940399 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 647154 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 24325 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 312873 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 6552 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 58721 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 143362 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 202083 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 15559963 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3035862 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 198568 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 155802 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 328818 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 249531 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13597003 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 38106 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2494844 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1679253 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 593871 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4649 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 243688 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4259 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 37580 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 120039 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 157619 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11824953 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2433073 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 153674 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1012523 # number of nop insts executed -system.cpu1.iew.exec_refs 4881099 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2446532 # Number of branches executed -system.cpu1.iew.exec_stores 1845237 # Number of stores executed -system.cpu1.iew.exec_rate 0.590834 # Inst execution rate -system.cpu1.iew.wb_sent 15420680 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 15379390 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 7566791 # num instructions producing a value -system.cpu1.iew.wb_consumers 10761562 # num instructions consuming a value +system.cpu1.iew.exec_nop 734045 # number of nop insts executed +system.cpu1.iew.exec_refs 4040076 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1766091 # Number of branches executed +system.cpu1.iew.exec_stores 1607003 # Number of stores executed +system.cpu1.iew.exec_rate 0.619591 # Inst execution rate +system.cpu1.iew.wb_sent 11733612 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11702518 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5498346 # num instructions producing a value +system.cpu1.iew.wb_consumers 7839453 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.583977 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.703131 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.613176 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.701369 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2776166 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 197728 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 185190 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 23976589 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.630910 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.597118 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1874564 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 187666 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 145503 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 17835799 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.653281 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.639800 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 18550941 77.37% 77.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2272481 9.48% 86.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1151381 4.80% 91.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 578443 2.41% 94.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 385291 1.61% 95.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 189866 0.79% 96.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 157998 0.66% 97.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 143488 0.60% 97.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 546700 2.28% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 13664737 76.61% 76.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1906046 10.69% 87.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 699754 3.92% 91.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 424730 2.38% 93.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 316948 1.78% 95.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133544 0.75% 96.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 114109 0.64% 96.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 155571 0.87% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 420360 2.36% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 23976589 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 15127070 # Number of instructions committed -system.cpu1.commit.committedOps 15127070 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 17835799 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 11651787 # Number of instructions committed +system.cpu1.commit.committedOps 11651787 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4418203 # Number of memory references committed -system.cpu1.commit.loads 2674883 # Number of loads committed -system.cpu1.commit.membars 66521 # Number of memory barriers committed -system.cpu1.commit.branches 2263870 # Number of branches committed -system.cpu1.commit.fp_insts 115331 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 13957396 # Number of committed integer instructions. -system.cpu1.commit.function_calls 240978 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 845832 5.59% 5.59% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 9417463 62.26% 67.85% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 23911 0.16% 68.01% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.01% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 11769 0.08% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 2741404 18.12% 86.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1743996 11.53% 97.75% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 340936 2.25% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3713677 # Number of memory references committed +system.cpu1.commit.loads 2179871 # Number of loads committed +system.cpu1.commit.membars 62781 # Number of memory barriers committed +system.cpu1.commit.branches 1664922 # Number of branches committed +system.cpu1.commit.fp_insts 144632 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 10748857 # Number of committed integer instructions. +system.cpu1.commit.function_calls 187454 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 614300 5.27% 5.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6897823 59.20% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 19873 0.17% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 12372 0.11% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2242652 19.25% 84.01% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1534637 13.17% 97.18% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 328371 2.82% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 15127070 # Class of committed instruction -system.cpu1.commit.bw_lim_events 546700 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 11651787 # Class of committed instruction +system.cpu1.commit.bw_lim_events 420360 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 41251186 # The number of ROB reads -system.cpu1.rob.rob_writes 36287802 # The number of ROB writes -system.cpu1.timesIdled 194891 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1876968 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3779240330 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 14284756 # Number of Instructions Simulated -system.cpu1.committedOps 14284756 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.843615 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.843615 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.542413 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.542413 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20099122 # number of integer regfile reads -system.cpu1.int_regfile_writes 11015819 # number of integer regfile writes -system.cpu1.fp_regfile_reads 63024 # number of floating regfile reads -system.cpu1.fp_regfile_writes 62672 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1065455 # number of misc regfile reads -system.cpu1.misc_regfile_writes 283847 # number of misc regfile writes -system.cpu1.icache.tags.replacements 353746 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.553851 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 2153244 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 354258 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.078180 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 47615844250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.553851 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985457 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.985457 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 30855147 # The number of ROB reads +system.cpu1.rob.rob_writes 27397116 # The number of ROB writes +system.cpu1.timesIdled 166983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 900751 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3790431319 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11041005 # Number of Instructions Simulated +system.cpu1.committedOps 11041005 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.728564 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.728564 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.578515 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.578515 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 15169687 # number of integer regfile reads +system.cpu1.int_regfile_writes 8276758 # number of integer regfile writes +system.cpu1.fp_regfile_reads 77475 # number of floating regfile reads +system.cpu1.fp_regfile_writes 77542 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1124646 # number of misc regfile reads +system.cpu1.misc_regfile_writes 280447 # number of misc regfile writes +system.cpu1.icache.tags.replacements 312757 # number of replacements +system.cpu1.icache.tags.tagsinuse 471.042243 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1644085 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 313269 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.248157 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1879134143250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.042243 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920004 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.920004 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2876460 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2876460 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 2153244 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2153244 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2153244 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2153244 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2153244 # number of overall hits -system.cpu1.icache.overall_hits::total 2153244 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 368891 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 368891 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 368891 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 368891 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 368891 # number of overall misses -system.cpu1.icache.overall_misses::total 368891 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5137931940 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5137931940 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5137931940 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5137931940 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5137931940 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5137931940 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2522135 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2522135 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2522135 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2522135 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2522135 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2522135 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146261 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.146261 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146261 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.146261 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146261 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.146261 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13928.049044 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13928.049044 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13928.049044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13928.049044 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1327 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2280436 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2280436 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1644085 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1644085 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1644085 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1644085 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1644085 # number of overall hits +system.cpu1.icache.overall_hits::total 1644085 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 323026 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 323026 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 323026 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 323026 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 323026 # number of overall misses +system.cpu1.icache.overall_misses::total 323026 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4370273976 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4370273976 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4370273976 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4370273976 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4370273976 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4370273976 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1967111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1967111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1967111 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1967111 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1967111 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1967111 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164213 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.164213 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164213 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.164213 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.164213 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.164213 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.170952 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.170952 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.170952 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13529.170952 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.170952 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.170952 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 24.127273 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14566 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 14566 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 14566 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 14566 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 14566 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 14566 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 354325 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 354325 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 354325 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 354325 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 354325 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 354325 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4259071697 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4259071697 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4259071697 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4259071697 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4259071697 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4259071697 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140486 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.140486 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.140486 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9701 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 9701 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 9701 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 9701 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 9701 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 9701 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 313325 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 313325 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 313325 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 313325 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 313325 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 313325 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3639863451 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3639863451 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3639863451 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3639863451 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3639863451 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3639863451 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.159282 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.159282 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.159282 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11616.894442 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360788 # number of replacements -system.cpu1.dcache.tags.tagsinuse 496.086183 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3613456 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 361109 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 10.006552 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 40126349500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.086183 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968918 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.968918 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18510307 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18510307 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220866 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2220866 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1307515 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1307515 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45364 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 45364 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48883 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 48883 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3528381 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3528381 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3528381 # number of overall hits -system.cpu1.dcache.overall_hits::total 3528381 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 524895 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 524895 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 378889 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 378889 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8897 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8897 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 903784 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 903784 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 903784 # number of overall misses -system.cpu1.dcache.overall_misses::total 903784 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8191623763 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8191623763 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 14087810149 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 14087810149 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 135761491 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 135761491 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5726098 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5726098 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 22279433912 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 22279433912 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 22279433912 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 22279433912 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2745761 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2745761 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1686404 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1686404 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54261 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 54261 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 49669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4432165 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4432165 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4432165 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4432165 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.191166 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.191166 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224673 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.224673 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.163967 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.163967 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015825 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015825 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.203915 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.203915 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.203915 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.203915 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7285.111959 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7285.111959 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 560522 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 381 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 27149 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.646138 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 20.052632 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 140166 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.227589 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3241153 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 140473 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.073139 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 39570817000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.227589 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.961382 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.961382 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15302146 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15302146 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1936775 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1936775 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1212075 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1212075 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45668 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 45668 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44613 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 44613 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3148850 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3148850 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3148850 # number of overall hits +system.cpu1.dcache.overall_hits::total 3148850 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 269383 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 269383 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 265424 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 265424 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8139 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8139 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4996 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 4996 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 534807 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 534807 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 534807 # number of overall misses +system.cpu1.dcache.overall_misses::total 534807 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4084517434 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4084517434 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8552113041 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8552113041 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77678496 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77678496 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 36778735 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 36778735 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12636630475 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12636630475 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12636630475 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12636630475 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2206158 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2206158 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1477499 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1477499 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 53807 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 53807 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49609 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 49609 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3683657 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3683657 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3683657 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3683657 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.122105 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.122105 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179644 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.179644 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.151263 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.151263 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100708 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100708 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.145184 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.145184 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.145184 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.145184 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15162.491449 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15162.491449 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32220.571768 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32220.571768 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9543.985256 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9543.985256 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.636309 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.636309 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23628.393935 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23628.393935 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23628.393935 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23628.393935 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 376916 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 344 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 18544 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.325496 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 31.272727 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 273838 # number of writebacks -system.cpu1.dcache.writebacks::total 273838 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229504 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 229504 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 313811 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 313811 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1705 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1705 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 543315 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 543315 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 543315 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 543315 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 295391 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 295391 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65078 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65078 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7192 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7192 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 360469 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 360469 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 360469 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 360469 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3818838154 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3818838154 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2138006676 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2138006676 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81043507 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81043507 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4153902 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4153902 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5956844830 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5956844830 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5956844830 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5956844830 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 490391500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 490391500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 941927000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 941927000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1432318500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1432318500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038590 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038590 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132545 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.132545 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015825 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015825 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.081330 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.081330 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5284.862595 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5284.862595 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 94206 # number of writebacks +system.cpu1.dcache.writebacks::total 94206 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165989 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 165989 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 215339 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 215339 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 381328 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 381328 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 381328 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 381328 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 103394 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 103394 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 50085 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 50085 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7484 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7484 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4996 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 4996 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 153479 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 153479 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 153479 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 153479 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1212902508 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1212902508 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1317911046 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1317911046 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54853004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54853004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26784265 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26784265 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2530813554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2530813554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2530813554 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2530813554 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29140000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29140000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 708818500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 708818500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737958500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737958500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046866 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046866 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033899 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.139090 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.139090 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100708 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100708 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041665 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.041665 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041665 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.041665 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11730.879045 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11730.879045 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26313.487990 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26313.487990 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7329.369856 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7329.369856 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.141914 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.141914 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2082,32 +2105,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4820 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 161850 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55184 39.67% 39.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 39.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.38% 41.15% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.16% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81844 58.84% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139099 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 54289 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54273 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 110633 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865924468000 98.05% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 60967000 0.00% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 531593000 0.03% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8367000 0.00% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36597541500 1.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903122936500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983782 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6701 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 170162 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 59106 40.33% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.42% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.31% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 339 0.23% 41.96% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 85060 58.04% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 146561 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 58406 49.14% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.62% 50.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 339 0.29% 51.15% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 58067 48.85% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 118868 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864755925000 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61031500 0.00% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 543238000 0.03% 97.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 152147500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39554606000 2.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1905066948000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988157 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.663127 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.795354 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682659 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811048 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed @@ -2139,60 +2162,60 @@ system.cpu0.kern.syscall::144 2 0.89% 99.11% # nu system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 105 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2905 1.98% 2.05% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132721 90.43% 92.52% # number of callpals executed -system.cpu0.kern.callpal::rdps 6135 4.18% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rti 4306 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 439 0.28% 0.28% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3223 2.08% 2.37% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 139738 90.30% 92.70% # number of callpals executed +system.cpu0.kern.callpal::rdps 6333 4.09% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.80% # number of callpals executed +system.cpu0.kern.callpal::rti 4427 2.86% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 146768 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6331 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches +system.cpu0.kern.callpal::total 154756 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6973 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1341 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1341 -system.cpu0.kern.mode_good::user 1342 +system.cpu0.kern.mode_good::kernel 1340 +system.cpu0.kern.mode_good::user 1341 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.211815 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.192170 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.349668 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901148119000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1974809500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.322468 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1903068198000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1998742000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2906 # number of times the context was actually changed +system.cpu0.kern.swap_context 3224 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3853 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 75635 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26441 39.26% 39.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 2.85% 42.12% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 105 0.16% 42.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 38878 57.73% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 67346 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25959 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 3.57% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.20% 51.98% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25854 48.02% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53840 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1868834322000 98.22% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532397000 0.03% 98.24% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 48831000 0.00% 98.25% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33374320500 1.75% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1902789870500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981771 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2621 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 71304 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23839 38.11% 38.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.08% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 439 0.70% 41.89% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 36346 58.11% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 62548 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 23162 48.01% 48.01% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 3.99% 51.99% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 439 0.91% 52.90% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22723 47.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 48248 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872982420000 98.33% 98.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531501500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 197949500 0.01% 98.37% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31046317000 1.63% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904758188000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.971601 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.665003 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.799454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.625186 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771376 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed @@ -2208,35 +2231,35 @@ system.cpu1.kern.syscall::74 10 9.90% 97.03% # nu system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1334 1.92% 1.95% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 1.95% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 1.96% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62422 89.83% 91.80% # number of callpals executed -system.cpu1.kern.callpal::rdps 2621 3.77% 95.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.57% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.58% # number of callpals executed -system.cpu1.kern.callpal::rti 2896 4.17% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 339 0.52% 0.52% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1674 2.58% 3.11% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.11% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.13% # number of callpals executed +system.cpu1.kern.callpal::swpipl 56749 87.55% 90.68% # number of callpals executed +system.cpu1.kern.callpal::rdps 2425 3.74% 94.42% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.42% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.43% # number of callpals executed +system.cpu1.kern.callpal::rti 3435 5.30% 99.73% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.21% 99.93% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 69486 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1712 # number of protection mode switches +system.cpu1.kern.callpal::total 64819 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1725 # number of protection mode switches system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2056 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 462 +system.cpu1.kern.mode_switch::idle 2719 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 758 system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 67 -system.cpu1.kern.mode_switch_good::kernel 0.269860 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 363 +system.cpu1.kern.mode_switch_good::kernel 0.439420 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.032588 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.221955 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 38841912000 2.04% 2.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 712477500 0.04% 2.08% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862932175500 97.92% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1335 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.133505 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.313288 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6292990000 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 709362000 0.04% 0.37% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1897439269000 99.63% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1675 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 6fda1994e..fe03695e1 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,115 +1,115 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860009 # Number of seconds simulated -sim_ticks 1860008936000 # Number of ticks simulated -final_tick 1860008936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859039 # Number of seconds simulated +sim_ticks 1859038679000 # Number of ticks simulated +final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106543 # Simulator instruction rate (inst/s) -host_op_rate 106543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3740252336 # Simulator tick rate (ticks/s) -host_mem_usage 320492 # Number of bytes of host memory used -host_seconds 497.30 # Real time elapsed on the host -sim_insts 52983264 # Number of instructions simulated -sim_ops 52983264 # Number of ops (including micro ops) simulated +host_inst_rate 164972 # Simulator instruction rate (inst/s) +host_op_rate 164972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5794497034 # Simulator tick rate (ticks/s) +host_mem_usage 371088 # Number of bytes of host memory used +host_seconds 320.83 # Real time elapsed on the host +sim_insts 52927600 # Number of instructions simulated +sim_ops 52927600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24900352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25869824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4866048 # Number of bytes written to this memory +system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4860032 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7525376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15133 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 389068 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7519360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388947 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404216 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 76032 # Number of write requests responded to by this memory +system.physmem.num_reads::total 404091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 75938 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117584 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13387222 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 117490 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13390043 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13908441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2616142 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1429739 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045882 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2616142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13387222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17954322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404216 # Number of read requests accepted -system.physmem.writeReqs 117584 # Number of write requests accepted -system.physmem.readBursts 404216 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117584 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25858752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue -system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25869824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7525376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_read::total 13911396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2614272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1430486 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4044757 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2614272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13390043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1431002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17956154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404091 # Number of read requests accepted +system.physmem.writeReqs 117490 # Number of write requests accepted +system.physmem.readBursts 404091 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117490 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25850368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue +system.physmem.bytesWritten 7517888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25861824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7519360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 213 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25622 # Per bank write bursts -system.physmem.perBankRdBursts::1 25451 # Per bank write bursts -system.physmem.perBankRdBursts::2 25608 # Per bank write bursts -system.physmem.perBankRdBursts::3 25528 # Per bank write bursts -system.physmem.perBankRdBursts::4 25399 # Per bank write bursts -system.physmem.perBankRdBursts::5 24757 # Per bank write bursts -system.physmem.perBankRdBursts::6 24940 # Per bank write bursts -system.physmem.perBankRdBursts::7 25074 # Per bank write bursts -system.physmem.perBankRdBursts::8 24966 # Per bank write bursts -system.physmem.perBankRdBursts::9 25053 # Per bank write bursts -system.physmem.perBankRdBursts::10 25586 # Per bank write bursts -system.physmem.perBankRdBursts::11 24884 # Per bank write bursts -system.physmem.perBankRdBursts::12 24485 # Per bank write bursts -system.physmem.perBankRdBursts::13 25285 # Per bank write bursts -system.physmem.perBankRdBursts::14 25789 # Per bank write bursts -system.physmem.perBankRdBursts::15 25616 # Per bank write bursts -system.physmem.perBankWrBursts::0 7925 # Per bank write bursts -system.physmem.perBankWrBursts::1 7509 # Per bank write bursts -system.physmem.perBankWrBursts::2 7974 # Per bank write bursts -system.physmem.perBankWrBursts::3 7525 # Per bank write bursts -system.physmem.perBankWrBursts::4 7335 # Per bank write bursts -system.physmem.perBankWrBursts::5 6682 # Per bank write bursts -system.physmem.perBankWrBursts::6 6769 # Per bank write bursts -system.physmem.perBankWrBursts::7 6701 # Per bank write bursts -system.physmem.perBankWrBursts::8 7135 # Per bank write bursts -system.physmem.perBankWrBursts::9 6719 # Per bank write bursts -system.physmem.perBankWrBursts::10 7431 # Per bank write bursts -system.physmem.perBankWrBursts::11 6970 # Per bank write bursts -system.physmem.perBankWrBursts::12 7113 # Per bank write bursts -system.physmem.perBankWrBursts::13 7882 # Per bank write bursts -system.physmem.perBankWrBursts::14 8065 # Per bank write bursts -system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 193 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25747 # Per bank write bursts +system.physmem.perBankRdBursts::1 25572 # Per bank write bursts +system.physmem.perBankRdBursts::2 25523 # Per bank write bursts +system.physmem.perBankRdBursts::3 25355 # Per bank write bursts +system.physmem.perBankRdBursts::4 25392 # Per bank write bursts +system.physmem.perBankRdBursts::5 24811 # Per bank write bursts +system.physmem.perBankRdBursts::6 25029 # Per bank write bursts +system.physmem.perBankRdBursts::7 25134 # Per bank write bursts +system.physmem.perBankRdBursts::8 24968 # Per bank write bursts +system.physmem.perBankRdBursts::9 25052 # Per bank write bursts +system.physmem.perBankRdBursts::10 25439 # Per bank write bursts +system.physmem.perBankRdBursts::11 24779 # Per bank write bursts +system.physmem.perBankRdBursts::12 24568 # Per bank write bursts +system.physmem.perBankRdBursts::13 25250 # Per bank write bursts +system.physmem.perBankRdBursts::14 25688 # Per bank write bursts +system.physmem.perBankRdBursts::15 25605 # Per bank write bursts +system.physmem.perBankWrBursts::0 8041 # Per bank write bursts +system.physmem.perBankWrBursts::1 7603 # Per bank write bursts +system.physmem.perBankWrBursts::2 7894 # Per bank write bursts +system.physmem.perBankWrBursts::3 7385 # Per bank write bursts +system.physmem.perBankWrBursts::4 7327 # Per bank write bursts +system.physmem.perBankWrBursts::5 6730 # Per bank write bursts +system.physmem.perBankWrBursts::6 6858 # Per bank write bursts +system.physmem.perBankWrBursts::7 6765 # Per bank write bursts +system.physmem.perBankWrBursts::8 7133 # Per bank write bursts +system.physmem.perBankWrBursts::9 6722 # Per bank write bursts +system.physmem.perBankWrBursts::10 7301 # Per bank write bursts +system.physmem.perBankWrBursts::11 6871 # Per bank write bursts +system.physmem.perBankWrBursts::12 7190 # Per bank write bursts +system.physmem.perBankWrBursts::13 7853 # Per bank write bursts +system.physmem.perBankWrBursts::14 7964 # Per bank write bursts +system.physmem.perBankWrBursts::15 7830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 1860003602000 # Total gap between requests +system.physmem.totGap 1859033424000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404216 # Read request sizes (log2) +system.physmem.readPktSize::6 404091 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117584 # Write request sizes (log2) +system.physmem.writePktSize::6 117490 # Write request sizes (log2) system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -151,201 +151,215 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 546.434703 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 336.353089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.871718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13232 21.66% 21.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10443 17.09% 38.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4742 7.76% 46.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2710 4.44% 50.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2446 4.00% 54.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1597 2.61% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1401 2.29% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1610 2.64% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22909 37.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61090 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.868151 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2912.510758 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5253 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 544.521149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 334.160448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 418.029082 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13483 22.00% 22.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10372 16.93% 38.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4758 7.76% 46.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2785 4.54% 51.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2293 3.74% 54.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1673 2.73% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1477 2.41% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1592 2.60% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22847 37.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.198394 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2919.153555 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5229 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5256 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5256 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.365297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.103318 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.103778 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4494 85.50% 85.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 124 2.36% 87.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 9 0.17% 88.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 232 4.41% 92.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 40 0.76% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 6 0.11% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 12 0.23% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 93.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 27 0.51% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 15 0.29% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.10% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.06% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 31 0.59% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.15% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.08% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 5 0.10% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 188 3.58% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.10% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.06% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.21% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.13% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5256 # Writes before turning the bus around for reads -system.physmem.totQLat 3626109250 # Total ticks spent queuing -system.physmem.totMemAccLat 11201915500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2020215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8974.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5232 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.451644 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.067800 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.155033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4469 85.42% 85.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 138 2.64% 88.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 12 0.23% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 232 4.43% 92.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 44 0.84% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.04% 93.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.10% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.19% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.32% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.04% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.08% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 28 0.54% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 15 0.29% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 15 0.29% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 171 3.27% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.11% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.04% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.11% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.08% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.21% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 7 0.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5232 # Writes before turning the bus around for reads +system.physmem.totQLat 3681492750 # Total ticks spent queuing +system.physmem.totMemAccLat 11254842750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2019560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9114.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27724.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27864.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.05 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing -system.physmem.readRowHits 364992 # Number of row buffer hits during reads -system.physmem.writeRowHits 95512 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.23 # Row buffer hit rate for writes -system.physmem.avgGap 3564591.03 # Average gap between requests -system.physmem.pageHitRate 88.28 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1761923491250 # Time in different power states -system.physmem.memoryStateTime::REF 62109580000 # Time in different power states +system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing +system.physmem.readRowHits 364830 # Number of row buffer hits during reads +system.physmem.writeRowHits 95269 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.09 # Row buffer hit rate for writes +system.physmem.avgGap 3564227.65 # Average gap between requests +system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761056207000 # Time in different power states +system.physmem.memoryStateTime::REF 62077340000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 35970256750 # Time in different power states +system.physmem.memoryStateTime::ACT 35903990500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 17983494 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296097 # Transaction distribution -system.membus.trans_dist::ReadResp 296008 # Transaction distribution -system.membus.trans_dist::WriteReq 9598 # Transaction distribution -system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 76032 # Transaction distribution +system.membus.trans_dist::ReadReq 296046 # Transaction distribution +system.membus.trans_dist::ReadResp 295957 # Transaction distribution +system.membus.trans_dist::WriteReq 9597 # Transaction distribution +system.membus.trans_dist::WriteResp 9597 # Transaction distribution +system.membus.trans_dist::Writeback 75938 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 207 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 213 # Transaction distribution -system.membus.trans_dist::ReadExReq 115296 # Transaction distribution -system.membus.trans_dist::ReadExResp 115296 # Transaction distribution +system.membus.trans_dist::UpgradeReq 188 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 193 # Transaction distribution +system.membus.trans_dist::ReadExReq 115222 # Transaction distribution +system.membus.trans_dist::ReadExResp 115222 # Transaction distribution system.membus.trans_dist::BadAddressError 89 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884476 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 918094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917708 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1001386 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30734912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30779060 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 33439348 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33439348 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29284000 # Layer occupancy (ticks) +system.membus.pkt_count::total 1001000 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30720896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30765036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33425324 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 158 # Total snoops (count) +system.membus.snoop_fanout::samples 522030 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 522030 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 522030 # Request fanout histogram +system.membus.reqLayer0.occupancy 31457000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1484965250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1484421249 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 112000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 110500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3755505039 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3754388311 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.268186 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.260487 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709354954000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.268186 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.079262 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.079262 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1709355301000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260487 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078780 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078780 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 376037 # Number of tag accesses -system.iocache.tags.data_accesses 376037 # Number of data accesses +system.iocache.tags.tag_accesses 376213 # Number of tag accesses +system.iocache.tags.data_accesses 376213 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 64 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 64 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 86 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 86 # number of WriteInvalidateReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses @@ -358,16 +372,16 @@ system.iocache.overall_miss_latency::tsunami.ide 21133383 system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41616 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41616 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41638 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41638 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.001538 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.001538 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.002065 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.002065 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -396,24 +410,24 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2528134047 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2528134047 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.998462 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.998462 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency @@ -431,36 +445,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 17833670 # Number of BP lookups -system.cpu.branchPred.condPredicted 15506350 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381114 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12104225 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5926115 # Number of BTB hits +system.cpu.branchPred.lookups 17804968 # Number of BP lookups +system.cpu.branchPred.condPredicted 15499600 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 379466 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11923628 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5932721 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.959062 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 921355 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21398 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 49.756005 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 914118 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10317598 # DTB read hits -system.cpu.dtb.read_misses 42841 # DTB read misses -system.cpu.dtb.read_acv 498 # DTB read access violations -system.cpu.dtb.read_accesses 968680 # DTB read accesses -system.cpu.dtb.write_hits 6661505 # DTB write hits -system.cpu.dtb.write_misses 9470 # DTB write misses -system.cpu.dtb.write_acv 409 # DTB write access violations -system.cpu.dtb.write_accesses 342844 # DTB write accesses -system.cpu.dtb.data_hits 16979103 # DTB hits -system.cpu.dtb.data_misses 52311 # DTB misses -system.cpu.dtb.data_acv 907 # DTB access violations -system.cpu.dtb.data_accesses 1311524 # DTB accesses -system.cpu.itb.fetch_hits 1772041 # ITB hits -system.cpu.itb.fetch_misses 34420 # ITB misses -system.cpu.itb.fetch_acv 658 # ITB acv -system.cpu.itb.fetch_accesses 1806461 # ITB accesses +system.cpu.dtb.read_hits 10302215 # DTB read hits +system.cpu.dtb.read_misses 41309 # DTB read misses +system.cpu.dtb.read_acv 513 # DTB read access violations +system.cpu.dtb.read_accesses 965594 # DTB read accesses +system.cpu.dtb.write_hits 6646492 # DTB write hits +system.cpu.dtb.write_misses 9371 # DTB write misses +system.cpu.dtb.write_acv 419 # DTB write access violations +system.cpu.dtb.write_accesses 342338 # DTB write accesses +system.cpu.dtb.data_hits 16948707 # DTB hits +system.cpu.dtb.data_misses 50680 # DTB misses +system.cpu.dtb.data_acv 932 # DTB access violations +system.cpu.dtb.data_accesses 1307932 # DTB accesses +system.cpu.itb.fetch_hits 1774610 # ITB hits +system.cpu.itb.fetch_misses 34401 # ITB misses +system.cpu.itb.fetch_acv 653 # ITB acv +system.cpu.itb.fetch_accesses 1809011 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -473,259 +487,259 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118354133 # number of cpu cycles simulated +system.cpu.numCycles 118301061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29610053 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78304025 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17833670 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6847470 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80574615 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1256858 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1099 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26263 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1650622 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 440507 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9057340 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 272482 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112931823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.693374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.013486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29562966 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78094807 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17804968 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6846839 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80553195 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1252096 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1416 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1649882 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 450417 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9025532 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 274121 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 112872082 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.691888 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.011514 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98319716 87.06% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 938849 0.83% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1975725 1.75% 89.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 910849 0.81% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2798510 2.48% 92.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 647409 0.57% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 732146 0.65% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011734 0.90% 95.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5596885 4.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98296528 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 933530 0.83% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1975700 1.75% 89.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 908755 0.81% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2800334 2.48% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 638924 0.57% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 725896 0.64% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007040 0.89% 95.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5585375 4.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112931823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150681 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661608 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24101711 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76820135 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9519710 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1904377 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 585889 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 591731 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42945 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68430953 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 130896 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 585889 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25024532 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47243324 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20763433 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10413926 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8900717 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65988448 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204336 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2037147 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 141186 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4759131 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 44017538 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79991288 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79809724 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169111 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38182266 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5835264 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1692739 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 242112 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13540611 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10451547 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6960595 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1482211 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1061862 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58727790 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2141622 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57666213 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7541795 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3548748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1480432 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112931823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.510629 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.253101 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 112872082 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150506 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.660136 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24068860 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76820836 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9500551 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1898196 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 583638 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 588301 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42850 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68299285 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 133126 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 583638 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24994916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 47249741 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20742683 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10385328 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8915774 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65865702 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 202022 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2036806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 141544 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4770005 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43944287 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79812474 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79631676 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168345 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38137411 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5806868 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1690855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241233 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13548292 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10425085 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6927485 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1490397 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1054253 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58626057 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2139161 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57592696 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7502337 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3486338 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1478017 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 112872082 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.510247 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.252928 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89418441 79.18% 79.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10028401 8.88% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4312192 3.82% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2973812 2.63% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3078524 2.73% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1589541 1.41% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1010242 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 396621 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124049 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89394835 79.20% 79.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10016384 8.87% 88.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4304507 3.81% 91.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2950730 2.61% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3082787 2.73% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1592384 1.41% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1013037 0.90% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 395526 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 121892 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112931823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 112872082 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 207021 18.24% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 552834 48.70% 66.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375297 33.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 212963 18.82% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 545078 48.16% 66.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373836 33.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39135351 67.87% 67.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61883 0.11% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38374 0.07% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10730394 18.61% 86.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6740242 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949047 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39097776 67.89% 67.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61804 0.11% 68.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38376 0.07% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10712581 18.60% 86.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722276 11.67% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948961 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57666213 # Type of FU issued -system.cpu.iq.rate 0.487234 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1135152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019685 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228740415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68094123 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55977641 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 715091 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336647 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329707 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58410087 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 383992 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 639401 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57592696 # Type of FU issued +system.cpu.iq.rate 0.486832 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1131877 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019653 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228528169 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67952558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55916727 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712410 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334609 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328997 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58334880 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382407 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 639606 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1358213 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20004 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 581979 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1340629 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4088 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 553798 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18257 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 542602 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18287 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 539247 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 585889 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44309531 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 608680 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64580146 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145680 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10451547 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6960595 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1891521 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42330 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 362520 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20004 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 191994 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411566 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 603560 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57078103 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10388088 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 588109 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 583638 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44307486 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616008 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64468948 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145079 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10425085 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6927485 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1890835 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42893 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 369751 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 190429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410127 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 600556 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57009373 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10371242 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 583322 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3710734 # number of nop insts executed -system.cpu.iew.exec_refs 17074164 # number of memory reference insts executed -system.cpu.iew.exec_branches 8987700 # Number of branches executed -system.cpu.iew.exec_stores 6686076 # Number of stores executed -system.cpu.iew.exec_rate 0.482265 # Inst execution rate -system.cpu.iew.wb_sent 56446206 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56307348 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28961590 # num instructions producing a value -system.cpu.iew.wb_consumers 40346871 # num instructions consuming a value +system.cpu.iew.exec_nop 3703730 # number of nop insts executed +system.cpu.iew.exec_refs 17042240 # number of memory reference insts executed +system.cpu.iew.exec_branches 8981920 # Number of branches executed +system.cpu.iew.exec_stores 6670998 # Number of stores executed +system.cpu.iew.exec_rate 0.481901 # Inst execution rate +system.cpu.iew.wb_sent 56380366 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56245724 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28936691 # num instructions producing a value +system.cpu.iew.wb_consumers 40310167 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475753 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717815 # average fanout of values written-back +system.cpu.iew.wb_rate 0.475446 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8290413 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661190 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 549582 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111493844 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503831 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.456125 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8239182 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661144 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 548042 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111437316 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.503568 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.455315 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91848046 82.38% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7822356 7.02% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4123652 3.70% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2157766 1.94% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1851713 1.66% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 614180 0.55% 97.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 473259 0.42% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 509141 0.46% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2093731 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91810154 82.39% 82.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7802563 7.00% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4132031 3.71% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2155493 1.93% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1853584 1.66% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 616181 0.55% 97.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 467348 0.42% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 515869 0.46% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2084093 1.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111493844 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56174099 # Number of instructions committed -system.cpu.commit.committedOps 56174099 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111437316 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56116260 # Number of instructions committed +system.cpu.commit.committedOps 56116260 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471950 # Number of memory references committed -system.cpu.commit.loads 9093334 # Number of loads committed -system.cpu.commit.membars 226345 # Number of memory barriers committed -system.cpu.commit.branches 8441019 # Number of branches committed -system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52023449 # Number of committed integer instructions. -system.cpu.commit.function_calls 740634 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198108 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36220301 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60671 0.11% 70.28% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.refs 15458143 # Number of memory references committed +system.cpu.commit.loads 9084456 # Number of loads committed +system.cpu.commit.membars 226334 # Number of memory barriers committed +system.cpu.commit.branches 8434463 # Number of branches committed +system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. +system.cpu.commit.int_insts 51967854 # Number of committed integer instructions. +system.cpu.commit.function_calls 739911 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3195933 5.70% 5.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36178550 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.27% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction @@ -748,30 +762,30 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319679 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384570 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949047 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9310790 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6379639 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948960 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56174099 # Class of committed instruction -system.cpu.commit.bw_lim_events 2093731 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56116260 # Class of committed instruction +system.cpu.commit.bw_lim_events 2084093 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173614429 # The number of ROB reads -system.cpu.rob.rob_writes 130369620 # The number of ROB writes -system.cpu.timesIdled 576556 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5422310 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3601657297 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52983264 # Number of Instructions Simulated -system.cpu.committedOps 52983264 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.233802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.233802 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447667 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447667 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74755796 # number of integer regfile reads -system.cpu.int_regfile_writes 40630218 # number of integer regfile writes -system.cpu.fp_regfile_reads 167440 # number of floating regfile reads -system.cpu.fp_regfile_writes 167913 # number of floating regfile writes -system.cpu.misc_regfile_reads 2030226 # number of misc regfile reads -system.cpu.misc_regfile_writes 939431 # number of misc regfile writes +system.cpu.rob.rob_reads 173459156 # The number of ROB reads +system.cpu.rob.rob_writes 130141826 # The number of ROB writes +system.cpu.timesIdled 576115 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5428979 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599776298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52927600 # Number of Instructions Simulated +system.cpu.committedOps 52927600 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.235149 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.235149 # CPI: Total CPI of All Threads +system.cpu.ipc 0.447398 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.447398 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74648651 # number of integer regfile reads +system.cpu.int_regfile_writes 40584029 # number of integer regfile writes +system.cpu.fp_regfile_reads 166982 # number of floating regfile reads +system.cpu.fp_regfile_writes 167600 # number of floating regfile writes +system.cpu.misc_regfile_reads 2029015 # number of misc regfile reads +system.cpu.misc_regfile_writes 939371 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -803,13 +817,12 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454701 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51086 # Transaction distribution -system.iobus.trans_dist::WriteResp 51150 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 64 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51063 # Transaction distribution +system.iobus.trans_dist::WriteResp 51149 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 86 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -821,28 +834,27 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705756 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) +system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -864,250 +876,259 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374510641 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374547621 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 114654995 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2149538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2149432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 845214 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2147499 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2147393 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 842679 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 94 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 302210 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 302210 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301934 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074480 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3693292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5767772 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66377344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144210036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 210587380 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 210577396 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2681920 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2503268997 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686339 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5760593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66370688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143907436 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210278124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42060 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3326850 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111298 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3285116 98.75% 98.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41734 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3326850 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2498300996 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1560084006 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1559854344 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2193039668 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2189806641 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1036559 # number of replacements -system.cpu.icache.tags.tagsinuse 509.401978 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7968978 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1037067 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.684150 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26427286250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.401978 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 1036451 # number of replacements +system.cpu.icache.tags.tagsinuse 509.402237 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7937240 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1036959 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.654343 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.402237 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10094673 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10094673 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7968979 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7968979 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7968979 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7968979 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7968979 # number of overall hits -system.cpu.icache.overall_hits::total 7968979 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1088360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1088360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1088360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1088360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1088360 # number of overall misses -system.cpu.icache.overall_misses::total 1088360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15140469933 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15140469933 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15140469933 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15140469933 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15140469933 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15140469933 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9057339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9057339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9057339 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9057339 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9057339 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9057339 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120163 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120163 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120163 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120163 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120163 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120163 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13911.270106 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13911.270106 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13911.270106 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13911.270106 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4471 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10062742 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10062742 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7937241 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7937241 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7937241 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7937241 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7937241 # number of overall hits +system.cpu.icache.overall_hits::total 7937241 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1088289 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1088289 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1088289 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1088289 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1088289 # number of overall misses +system.cpu.icache.overall_misses::total 1088289 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15130440508 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15130440508 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15130440508 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15130440508 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15130440508 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15130440508 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9025530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9025530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9025530 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9025530 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9025530 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9025530 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120579 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120579 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120579 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120579 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120579 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120579 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13902.961904 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13902.961904 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13902.961904 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13902.961904 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4627 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 200 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.355000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.793103 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51026 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 51026 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 51026 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 51026 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 51026 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 51026 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037334 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1037334 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1037334 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1037334 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1037334 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1037334 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12446794989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12446794989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12446794989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12446794989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12446794989 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12446794989 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114530 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114530 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.830646 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.830646 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51077 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 51077 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 51077 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 51077 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 51077 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 51077 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037212 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1037212 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1037212 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1037212 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1037212 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1037212 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12445124401 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12445124401 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12445124401 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12445124401 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12445124401 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12445124401 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114920 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114920 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114920 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.631332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.631332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338424 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65337.415563 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2581710 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403590 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.396863 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5538438750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53805.196085 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5357.724352 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6174.495125 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.821002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081752 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094215 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996970 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55433 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 27024459 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 27024459 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1022012 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 831240 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1853252 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 845214 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 845214 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186775 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186775 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1022012 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1018015 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2040027 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1022012 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1018015 # number of overall hits -system.cpu.l2cache.overall_hits::total 2040027 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15134 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273861 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288995 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 68 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 68 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115435 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115435 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389296 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404430 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15134 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389296 # number of overall misses -system.cpu.l2cache.overall_misses::total 404430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158853750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17990415250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19149269000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 271990 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 271990 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647831862 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9647831862 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1158853750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27638247112 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28797100862 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1158853750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27638247112 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28797100862 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1037146 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1105101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2142247 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 845214 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 845214 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 94 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 94 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 302210 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 302210 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1037146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1407311 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2444457 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1037146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1407311 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2444457 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014592 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.247815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.134903 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.723404 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.723404 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.381969 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.381969 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014592 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276624 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165448 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014592 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276624 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165448 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76572.865733 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65691.775207 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66261.592761 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3999.852941 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3999.852941 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 7833 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 7833 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83578.047057 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83578.047057 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76572.865733 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70995.456188 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71204.166016 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76572.865733 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70995.456188 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71204.166016 # average overall miss latency +system.cpu.l2cache.tags.replacements 338311 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65336.723406 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2577279 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403479 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.387641 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53740.150485 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.296148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.276773 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.820010 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081502 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095448 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2421 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26985288 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26985288 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1021912 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 829370 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1851282 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 842679 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 842679 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 21 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 21 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186572 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186572 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1021912 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1015942 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2037854 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1021912 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1015942 # number of overall hits +system.cpu.l2cache.overall_hits::total 2037854 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15130 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288944 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115362 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115362 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15130 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389176 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404306 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15130 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389176 # number of overall misses +system.cpu.l2cache.overall_misses::total 404306 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158124750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17992143250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19150268000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 194993 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 194993 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 69497 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 69497 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9692879611 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9692879611 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1158124750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27685022861 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28843147611 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1158124750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27685022861 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28843147611 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1037042 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1103184 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2140226 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 842679 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 842679 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 81 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301934 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301934 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1037042 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1405118 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2442160 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1037042 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1405118 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2442160 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248203 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.135006 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.592593 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.592593 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.192308 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.192308 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382077 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382077 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014590 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.276970 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.165553 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014590 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.276970 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.165553 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76544.927297 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65709.362012 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66276.745667 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4062.354167 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4062.354167 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 13899.400000 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 13899.400000 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84021.424828 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84021.424828 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71339.895057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71339.895057 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1116,80 +1137,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76032 # number of writebacks -system.cpu.l2cache.writebacks::total 76032 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks +system.cpu.l2cache.writebacks::total 75938 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15133 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273861 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288994 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 68 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 68 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115435 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115435 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15133 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404429 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15133 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389296 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967955000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14578847250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15546802250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 698067 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 698067 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 60006 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8240977138 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8240977138 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967955000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22819824388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23787779388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967955000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22819824388 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23787779388 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333197000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333197000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882784000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882784000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3215981000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3215981000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.247815 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.134902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.723404 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.723404 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.381969 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.381969 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276624 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165447 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276624 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165447 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63963.193022 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53234.477527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53796.280373 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10265.691176 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10265.691176 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15129 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288943 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115362 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115362 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15129 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404305 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15129 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404305 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967311000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14580972250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15548283250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 493045 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 493045 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 50005 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 50005 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8286916389 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8286916389 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967311000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22867888639 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23835199639 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967311000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22867888639 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23835199639 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333507000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333507000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884436000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884436000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217943000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217943000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248203 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135006 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.592593 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.592593 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.192308 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.192308 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382077 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382077 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165552 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165552 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63937.537180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53251.375934 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53810.901285 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10271.770833 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10271.770833 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71390.627955 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71390.627955 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63963.193022 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58818.184126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63963.193022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58818.184126 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71834.021506 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71834.021506 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1197,168 +1218,168 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1406709 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994656 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11889160 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1407221 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.448680 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1404516 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994651 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11877087 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1405028 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.453274 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994656 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994651 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 64006618 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 64006618 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7294645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7294645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4192085 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4192085 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186406 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186406 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215722 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215722 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11486730 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11486730 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11486730 # number of overall hits -system.cpu.dcache.overall_hits::total 11486730 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1781450 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1781450 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1956078 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1956078 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23435 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23435 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3737528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3737528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3737528 # number of overall misses -system.cpu.dcache.overall_misses::total 3737528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39460898751 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39460898751 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 77926098572 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 77926098572 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 366682499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 366682499 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 440006 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 440006 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117386997323 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117386997323 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117386997323 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117386997323 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9076095 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9076095 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6148163 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6148163 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209841 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209841 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215750 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215750 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15224258 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15224258 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15224258 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15224258 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196279 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.196279 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318156 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318156 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245498 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245498 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245498 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245498 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22150.999888 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22150.999888 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39837.930068 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39837.930068 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15646.788948 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15646.788948 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15714.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15714.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31407.656966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31407.656966 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3974317 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2076 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 180350 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 21 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.036690 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 98.857143 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 63934725 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63934725 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7287009 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7287009 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4187789 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4187789 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186297 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186297 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215715 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215715 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11474798 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11474798 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11474798 # number of overall hits +system.cpu.dcache.overall_hits::total 11474798 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1776849 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1776849 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1955456 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1955456 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23283 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23283 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3732305 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3732305 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3732305 # number of overall misses +system.cpu.dcache.overall_misses::total 3732305 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39503001495 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39503001495 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 78159072008 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 78159072008 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364867750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 364867750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402005 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 402005 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117662073503 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117662073503 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117662073503 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117662073503 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9063858 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9063858 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6143245 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6143245 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209580 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209580 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215741 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215741 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15207103 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15207103 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15207103 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15207103 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196037 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.196037 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318310 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318310 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111094 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111094 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22232.053199 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22232.053199 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39969.742100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39969.742100 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15670.993858 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15670.993858 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15461.730769 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15461.730769 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31525.310365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31525.310365 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3999248 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1376 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 180044 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.212615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 845214 # number of writebacks -system.cpu.dcache.writebacks::total 845214 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683673 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 683673 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664672 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664672 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5215 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5215 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2348345 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2348345 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2348345 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2348345 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1097777 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1097777 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291406 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291406 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18220 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18220 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389183 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389183 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389183 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389183 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27531600277 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27531600277 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11750999106 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11750999106 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 207629251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 207629251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 383994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 383994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39282599383 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39282599383 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39282599383 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39282599383 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423287000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423287000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997974498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997974498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421261498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421261498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120953 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120953 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047397 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047397 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086828 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086828 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 842679 # number of writebacks +system.cpu.dcache.writebacks::total 842679 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680758 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 680758 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664340 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664340 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5292 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5292 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2345098 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2345098 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2345098 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2345098 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096091 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1096091 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291116 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291116 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17991 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17991 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1387207 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1387207 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1387207 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1387207 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27515724784 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27515724784 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11792803134 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11792803134 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204517750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204517750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 349995 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 349995 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39308527918 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39308527918 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39308527918 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39308527918 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423597000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423597000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999614498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999614498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423211498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423211498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085843 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085843 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1367,28 +1388,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211008 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210986 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74656 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105564 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182238 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105550 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182216 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73289 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818262027500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61927000 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 526143500 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41157993000 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860008091000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73289 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148588 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817327743500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 61881000 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 521765000 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41126450000 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859037839500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694328 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815434 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815450 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1424,32 +1445,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175121 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175101 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191967 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches +system.cpu.kern.callpal::total 191946 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326496 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29080060000 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2655672500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1828272350500 98.29% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_ticks::kernel 29097785000 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2655967500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827284079000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4179 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 6a79f5850..85c742feb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.841612 # Number of seconds simulated -sim_ticks 1841612285000 # Number of ticks simulated -final_tick 1841612285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1841612450000 # Number of ticks simulated +final_tick 1841612450000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168459 # Simulator instruction rate (inst/s) -host_op_rate 168459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4750760669 # Simulator tick rate (ticks/s) -host_mem_usage 319468 # Number of bytes of host memory used -host_seconds 387.65 # Real time elapsed on the host -sim_insts 65302548 # Number of instructions simulated -sim_ops 65302548 # Number of ops (including micro ops) simulated +host_inst_rate 222430 # Simulator instruction rate (inst/s) +host_op_rate 222430 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6273480939 # Simulator tick rate (ticks/s) +host_mem_usage 370816 # Number of bytes of host memory used +host_seconds 293.56 # Real time elapsed on the host +sim_insts 65295558 # Number of instructions simulated +sim_ops 65295558 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 475840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19999104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 476096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20002240 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2248128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 298624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2645376 # Number of bytes read from this memory -system.physmem.bytes_read::total 25815040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 475840 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 2248832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 298304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2641344 # Number of bytes read from this memory +system.physmem.bytes_read::total 25814784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 476096 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 298624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 921472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4825408 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 921408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4825792 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7484736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 312486 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7485120 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7439 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 312535 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4666 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41334 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 75397 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 35138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41271 # Number of read requests responded to by this memory +system.physmem.num_reads::total 403356 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 75403 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116949 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 258382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10859563 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 116955 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 258521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10861265 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1220739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 162154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1436446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14017630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 258382 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1221121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 161980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1434256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14017490 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 258521 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 162154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 500362 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2620208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 161980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 500327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2620417 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::tsunami.ide 1444022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4064230 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2620208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 258382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10859563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 4064438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2620417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 258521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10861265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1444543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1220739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 162154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1436446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18081860 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 83439 # Number of read requests accepted -system.physmem.writeReqs 46740 # Number of write requests accepted -system.physmem.readBursts 83439 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 46740 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5337024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3072 # Total number of bytes read from write queue -system.physmem.bytesWritten 2989888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5340096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2991360 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 48 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.data 1221121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 161980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1434256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18081928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 83382 # Number of read requests accepted +system.physmem.writeReqs 46694 # Number of write requests accepted +system.physmem.readBursts 83382 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 46694 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5333696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue +system.physmem.bytesWritten 2986816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5336448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2988416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 52 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5256 # Per bank write bursts -system.physmem.perBankRdBursts::1 5087 # Per bank write bursts -system.physmem.perBankRdBursts::2 5115 # Per bank write bursts -system.physmem.perBankRdBursts::3 5179 # Per bank write bursts -system.physmem.perBankRdBursts::4 5173 # Per bank write bursts -system.physmem.perBankRdBursts::5 5205 # Per bank write bursts -system.physmem.perBankRdBursts::6 5267 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 55 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5371 # Per bank write bursts +system.physmem.perBankRdBursts::1 5100 # Per bank write bursts +system.physmem.perBankRdBursts::2 5085 # Per bank write bursts +system.physmem.perBankRdBursts::3 5221 # Per bank write bursts +system.physmem.perBankRdBursts::4 5159 # Per bank write bursts +system.physmem.perBankRdBursts::5 5196 # Per bank write bursts +system.physmem.perBankRdBursts::6 5274 # Per bank write bursts system.physmem.perBankRdBursts::7 5273 # Per bank write bursts -system.physmem.perBankRdBursts::8 5423 # Per bank write bursts +system.physmem.perBankRdBursts::8 5416 # Per bank write bursts system.physmem.perBankRdBursts::9 5013 # Per bank write bursts -system.physmem.perBankRdBursts::10 5464 # Per bank write bursts -system.physmem.perBankRdBursts::11 5273 # Per bank write bursts -system.physmem.perBankRdBursts::12 4813 # Per bank write bursts -system.physmem.perBankRdBursts::13 5124 # Per bank write bursts -system.physmem.perBankRdBursts::14 5602 # Per bank write bursts -system.physmem.perBankRdBursts::15 5124 # Per bank write bursts -system.physmem.perBankWrBursts::0 2825 # Per bank write bursts -system.physmem.perBankWrBursts::1 2787 # Per bank write bursts -system.physmem.perBankWrBursts::2 2858 # Per bank write bursts -system.physmem.perBankWrBursts::3 3069 # Per bank write bursts -system.physmem.perBankWrBursts::4 3024 # Per bank write bursts -system.physmem.perBankWrBursts::5 2822 # Per bank write bursts -system.physmem.perBankWrBursts::6 3224 # Per bank write bursts -system.physmem.perBankWrBursts::7 2821 # Per bank write bursts -system.physmem.perBankWrBursts::8 3331 # Per bank write bursts -system.physmem.perBankWrBursts::9 2683 # Per bank write bursts -system.physmem.perBankWrBursts::10 3131 # Per bank write bursts -system.physmem.perBankWrBursts::11 2953 # Per bank write bursts -system.physmem.perBankWrBursts::12 2475 # Per bank write bursts -system.physmem.perBankWrBursts::13 2748 # Per bank write bursts -system.physmem.perBankWrBursts::14 3227 # Per bank write bursts -system.physmem.perBankWrBursts::15 2739 # Per bank write bursts +system.physmem.perBankRdBursts::10 5453 # Per bank write bursts +system.physmem.perBankRdBursts::11 5267 # Per bank write bursts +system.physmem.perBankRdBursts::12 4696 # Per bank write bursts +system.physmem.perBankRdBursts::13 5103 # Per bank write bursts +system.physmem.perBankRdBursts::14 5623 # Per bank write bursts +system.physmem.perBankRdBursts::15 5089 # Per bank write bursts +system.physmem.perBankWrBursts::0 2944 # Per bank write bursts +system.physmem.perBankWrBursts::1 2803 # Per bank write bursts +system.physmem.perBankWrBursts::2 2831 # Per bank write bursts +system.physmem.perBankWrBursts::3 3111 # Per bank write bursts +system.physmem.perBankWrBursts::4 3010 # Per bank write bursts +system.physmem.perBankWrBursts::5 2812 # Per bank write bursts +system.physmem.perBankWrBursts::6 3230 # Per bank write bursts +system.physmem.perBankWrBursts::7 2824 # Per bank write bursts +system.physmem.perBankWrBursts::8 3325 # Per bank write bursts +system.physmem.perBankWrBursts::9 2680 # Per bank write bursts +system.physmem.perBankWrBursts::10 3123 # Per bank write bursts +system.physmem.perBankWrBursts::11 2945 # Per bank write bursts +system.physmem.perBankWrBursts::12 2356 # Per bank write bursts +system.physmem.perBankWrBursts::13 2727 # Per bank write bursts +system.physmem.perBankWrBursts::14 3249 # Per bank write bursts +system.physmem.perBankWrBursts::15 2699 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 1840600008500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 1840600173500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 83439 # Read request sizes (log2) +system.physmem.readPktSize::6 83382 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 46740 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 66354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 46694 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -156,137 +156,124 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 386.758569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 220.447203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 381.120515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7019 32.60% 32.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4847 22.51% 55.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1849 8.59% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1051 4.88% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 911 4.23% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 506 2.35% 75.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 375 1.74% 76.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 418 1.94% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4554 21.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21530 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2040 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 40.873529 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1027.655163 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2038 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 384.870346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 218.868855 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 380.663334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7130 32.98% 32.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4830 22.34% 55.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1852 8.57% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1050 4.86% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 916 4.24% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 498 2.30% 75.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 396 1.83% 77.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 403 1.86% 78.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4544 21.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21619 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2039 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 40.867092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1027.907354 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2037 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2040 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2040 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.900490 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.614282 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.575456 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 33 1.62% 1.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.34% 1.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 2.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.25% 2.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1695 83.09% 85.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 37 1.81% 87.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5 0.25% 87.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 107 5.25% 92.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7 0.34% 92.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.10% 93.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.05% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.15% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.39% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.05% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.05% 93.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 2 0.10% 93.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.05% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.10% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.10% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.39% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.15% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.15% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.10% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 78 3.82% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.05% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.10% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.05% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.34% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.10% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.15% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.05% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.15% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2040 # Writes before turning the bus around for reads -system.physmem.totQLat 869064750 # Total ticks spent queuing -system.physmem.totMemAccLat 2432646000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 416955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10421.57 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2039 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.888180 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.579378 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.470267 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 42 2.06% 2.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 4 0.20% 2.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 1722 84.45% 86.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 114 5.59% 92.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 19 0.93% 93.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3 0.15% 93.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.25% 93.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 2 0.10% 93.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 2 0.10% 93.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 3 0.15% 93.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 15 0.74% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.25% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 79 3.87% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 5 0.25% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.05% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.25% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.25% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 3 0.15% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.05% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2039 # Writes before turning the bus around for reads +system.physmem.totQLat 882163500 # Total ticks spent queuing +system.physmem.totMemAccLat 2444769750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 416695000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10585.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29171.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29335.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s @@ -296,258 +283,267 @@ system.physmem.busUtil 0.04 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 71609 # Number of row buffer hits during reads -system.physmem.writeRowHits 36969 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.09 # Row buffer hit rate for writes -system.physmem.avgGap 14138993.30 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1766589196000 # Time in different power states +system.physmem.avgWrQLen 8.38 # Average write queue length when enqueuing +system.physmem.readRowHits 71513 # Number of row buffer hits during reads +system.physmem.writeRowHits 36876 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.97 # Row buffer hit rate for writes +system.physmem.avgGap 14150190.45 # Average gap between requests +system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1766563042250 # Time in different power states system.physmem.memoryStateTime::REF 61495460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13527240250 # Time in different power states +system.physmem.memoryStateTime::ACT 13553394000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18112095 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44765 # Transaction distribution -system.membus.trans_dist::ReadResp 44760 # Transaction distribution -system.membus.trans_dist::WriteReq 3528 # Transaction distribution -system.membus.trans_dist::WriteResp 3528 # Transaction distribution -system.membus.trans_dist::Writeback 29460 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 17280 # Transaction distribution -system.membus.trans_dist::UpgradeReq 50 # Transaction distribution +system.membus.trans_dist::ReadReq 294949 # Transaction distribution +system.membus.trans_dist::ReadResp 294942 # Transaction distribution +system.membus.trans_dist::WriteReq 9810 # Transaction distribution +system.membus.trans_dist::WriteResp 9810 # Transaction distribution +system.membus.trans_dist::Writeback 75403 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 148 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 52 # Transaction distribution -system.membus.trans_dist::ReadExReq 41656 # Transaction distribution -system.membus.trans_dist::ReadExResp 41656 # Transaction distribution -system.membus.trans_dist::BadAddressError 5 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 12900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196412 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 209322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 34645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 34645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 243967 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15792 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7224576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 7240368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1106880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 1106880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 8347248 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33351936 # Total data (bytes) -system.membus.snoop_data_through_bus 3520 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11434500 # Layer occupancy (ticks) +system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::ReadExReq 115716 # Transaction distribution +system.membus.trans_dist::ReadExResp 115716 # Transaction distribution +system.membus.trans_dist::BadAddressError 7 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 14 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 999702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30639616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30685184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2666880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2666880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33352064 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 55 # Total snoops (count) +system.membus.snoop_fanout::samples 520629 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 520629 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 520629 # Request fanout histogram +system.membus.reqLayer0.occupancy 11839500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 517398750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 516853000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 783386948 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 782820695 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17911250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17912499 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337577 # number of replacements -system.l2c.tags.tagsinuse 65421.096735 # Cycle average of tags in use -system.l2c.tags.total_refs 2486717 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402739 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.174513 # Average number of references to valid blocks. +system.l2c.tags.replacements 337573 # number of replacements +system.l2c.tags.tagsinuse 65418.651212 # Cycle average of tags in use +system.l2c.tags.total_refs 2486411 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402735 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.173814 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54723.362784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2335.935658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2702.236553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 571.913553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 605.884543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2280.035703 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2201.727940 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035644 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041233 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54701.898581 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2338.827583 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2722.708612 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 571.952854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 605.884854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2274.772027 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2202.606700 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.834685 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.035688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041545 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.008727 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.009245 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034791 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033596 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998247 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034710 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.033609 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998209 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 5951 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2686 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55344 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55337 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26259828 # Number of tag accesses -system.l2c.tags.data_accesses 26259828 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 505337 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 482025 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 122124 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 80194 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 322880 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 255461 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1768021 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835818 # number of Writeback hits -system.l2c.Writeback_hits::total 835818 # number of Writeback hits +system.l2c.tags.tag_accesses 26257052 # Number of tag accesses +system.l2c.tags.data_accesses 26257052 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 505398 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 481784 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 121841 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 80801 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 322748 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 255127 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1767699 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835833 # number of Writeback hits +system.l2c.Writeback_hits::total 835833 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 10 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 14 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 7 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 90680 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25236 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 70985 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186901 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 505337 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 572705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 122124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 105430 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 322880 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 326446 # number of demand (read+write) hits -system.l2c.demand_hits::total 1954922 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 505337 # number of overall hits -system.l2c.overall_hits::cpu0.data 572705 # number of overall hits -system.l2c.overall_hits::cpu1.inst 122124 # number of overall hits -system.l2c.overall_hits::cpu1.data 105430 # number of overall hits -system.l2c.overall_hits::cpu2.inst 322880 # number of overall hits -system.l2c.overall_hits::cpu2.data 326446 # number of overall hits -system.l2c.overall_hits::total 1954922 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7435 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238426 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu2.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 90729 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 25227 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 70911 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186867 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 505398 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 572513 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 121841 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 106028 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 322748 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 326038 # number of demand (read+write) hits +system.l2c.demand_hits::total 1954566 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 505398 # number of overall hits +system.l2c.overall_hits::cpu0.data 572513 # number of overall hits +system.l2c.overall_hits::cpu1.inst 121841 # number of overall hits +system.l2c.overall_hits::cpu1.data 106028 # number of overall hits +system.l2c.overall_hits::cpu2.inst 322748 # number of overall hits +system.l2c.overall_hits::cpu2.data 326038 # number of overall hits +system.l2c.overall_hits::total 1954566 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7439 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 238433 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 2297 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16796 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4666 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 18014 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287634 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 13 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 22 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.data 16797 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4661 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 18005 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287632 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 24 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 74147 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 18341 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 23352 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 74189 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 18351 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 23300 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 115840 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7435 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 312573 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7439 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 312622 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 2297 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 35137 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4666 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 41366 # number of demand (read+write) misses -system.l2c.demand_misses::total 403474 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7435 # number of overall misses -system.l2c.overall_misses::cpu0.data 312573 # number of overall misses +system.l2c.demand_misses::cpu1.data 35148 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4661 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 41305 # number of demand (read+write) misses +system.l2c.demand_misses::total 403472 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7439 # number of overall misses +system.l2c.overall_misses::cpu0.data 312622 # number of overall misses system.l2c.overall_misses::cpu1.inst 2297 # number of overall misses -system.l2c.overall_misses::cpu1.data 35137 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4666 # number of overall misses -system.l2c.overall_misses::cpu2.data 41366 # number of overall misses -system.l2c.overall_misses::total 403474 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 172633500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1120486500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 352018500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1205249000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2850387500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 166993 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 166993 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu2.data 45998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 45998 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1259361990 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1949459473 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3208821463 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 172633500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2379848490 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 352018500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3154708473 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6059208963 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 172633500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2379848490 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 352018500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3154708473 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6059208963 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 512772 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 720451 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 124421 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 96990 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 327546 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 273475 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2055655 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835818 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835818 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 12 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.data 35148 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4661 # number of overall misses +system.l2c.overall_misses::cpu2.data 41305 # number of overall misses +system.l2c.overall_misses::total 403472 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 172213000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1123783250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 353640000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1207129000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2856765250 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 175993 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 175993 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu2.data 46498 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1259346740 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1952437723 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3211784463 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 172213000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2383129990 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 353640000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3159566723 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6068549713 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 172213000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2383129990 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 353640000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3159566723 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6068549713 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 512837 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 720217 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 124138 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 97598 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 327409 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 273132 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2055331 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835833 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835833 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 36 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 9 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 164827 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 43577 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 94337 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302741 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 512772 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 885278 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 124421 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 140567 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 327546 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 367812 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2358396 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 512772 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 885278 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 124421 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 140567 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 327546 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 367812 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2358396 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014500 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.330940 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018462 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.173172 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014245 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.065871 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.139923 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.750000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.565217 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.611111 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.222222 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.222222 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.449847 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.420887 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.247538 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382637 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014500 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.353079 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018462 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.249966 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014245 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.112465 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171080 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014500 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.353079 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018462 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.249966 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014245 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.112465 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171080 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75156.073139 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 66711.508693 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75443.313330 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 66906.239591 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9909.772489 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12845.615385 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 7590.590909 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 22999 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 22999 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68663.758247 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83481.477946 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 27700.461525 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75156.073139 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 67730.554401 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 75443.313330 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 76263.319465 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 15017.594598 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75156.073139 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 67730.554401 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 75443.313330 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 76263.319465 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 15017.594598 # average overall miss latency +system.l2c.UpgradeReq_accesses::cpu2.data 26 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 38 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 8 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 164918 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 43578 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 94211 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302707 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 512837 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 885135 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 124138 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 141176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 327409 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 367343 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2358038 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 512837 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 885135 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 124138 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 141176 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 327409 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 367343 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2358038 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014506 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.331057 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.018504 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.172104 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.014236 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.065921 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.139944 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.615385 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.631579 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.449854 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.421107 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.247317 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382680 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014506 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.353191 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.018504 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.248966 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014236 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.112443 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171105 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014506 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.353191 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.018504 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.248966 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014236 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.112443 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171105 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74973.008272 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 66903.807227 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75872.130444 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 67044.098861 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9932.014692 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10999.562500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7333.041667 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 23249 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68625.510326 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83795.610429 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 27726.039908 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 74973.008272 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 67802.719643 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 75872.130444 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 76493.565501 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 15040.819965 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 74973.008272 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 67802.719643 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 75872.130444 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 76493.565501 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 15040.819965 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,105 +552,105 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75397 # number of writebacks -system.l2c.writebacks::total 75397 # number of writebacks +system.l2c.writebacks::writebacks 75403 # number of writebacks +system.l2c.writebacks::total 75403 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu1.inst 2297 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 16796 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4666 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 18014 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41773 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 13 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 16797 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4661 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 18005 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41760 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 18341 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 23352 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 41693 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 18351 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 23300 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 41651 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 2297 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 35137 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4666 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 41366 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 83466 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 35148 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4661 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 41305 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 83411 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 2297 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 35137 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4666 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 41366 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 83466 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 143376000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 910203000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 293289500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 980286500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2327155000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 134513 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 134513 # number of UpgradeReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.data 35148 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4661 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 41305 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 83411 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 142970000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 913492250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 294969000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 982528500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2333959750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 173016 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 173016 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 20002 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1028930510 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1664066027 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2692996537 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 143376000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1939133510 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 293289500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2644352527 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5020151537 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 143376000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1939133510 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 293289500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2644352527 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5020151537 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 234017000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320664000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 554681000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 302737500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 395422000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 698159500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 536754500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 716086000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1252840500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018462 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173172 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014245 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.065871 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020321 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.565217 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.361111 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.222222 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.222222 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420887 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.247538 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.137718 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018462 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.249966 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014245 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.112465 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.035391 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018462 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.249966 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014245 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.112465 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.035391 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62418.807140 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54191.652774 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62856.729533 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54418.035972 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 55709.549230 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10347.153846 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10347.153846 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1028775260 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1667747777 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2696523037 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 142970000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1942267510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 294969000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2650276277 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5030482787 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 142970000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1942267510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 294969000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2650276277 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5030482787 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 233807000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320899000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 554706000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 302174000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 396022500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 698196500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 535981000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 716921500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1252902500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018504 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172104 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014236 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.065921 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020318 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.615385 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.421053 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421107 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.247317 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.137595 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018504 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.248966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014236 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.112443 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035373 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018504 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.248966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.112443 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035373 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62242.054854 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54384.250164 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54569.758400 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 55889.840757 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10813.500000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10813.500000 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56100.022354 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71260.107357 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64591.095316 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62418.807140 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55187.793779 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62856.729533 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63925.748852 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60146.065907 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62418.807140 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55187.793779 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62856.729533 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63925.748852 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60146.065907 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56060.991772 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71577.157811 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64740.895465 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62242.054854 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55259.687891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64163.570439 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60309.584911 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62242.054854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55259.687891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64163.570439 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60309.584911 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -666,14 +662,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254802 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254811 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693889914000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254802 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078425 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078425 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693889963000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254811 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078426 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078426 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -731,8 +727,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 70 system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 1039320090 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1039320090 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 1039517841 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1039517841 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles @@ -747,8 +743,8 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60145.838542 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60145.838542 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60157.282465 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60157.282465 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency @@ -770,22 +766,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4820184 # DTB read hits +system.cpu0.dtb.read_hits 4820532 # DTB read hits system.cpu0.dtb.read_misses 5970 # DTB read misses system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 427969 # DTB read accesses -system.cpu0.dtb.write_hits 3428698 # DTB write hits +system.cpu0.dtb.read_accesses 427970 # DTB read accesses +system.cpu0.dtb.write_hits 3430087 # DTB write hits system.cpu0.dtb.write_misses 674 # DTB write misses system.cpu0.dtb.write_acv 81 # DTB write access violations system.cpu0.dtb.write_accesses 164325 # DTB write accesses -system.cpu0.dtb.data_hits 8248882 # DTB hits +system.cpu0.dtb.data_hits 8250619 # DTB hits system.cpu0.dtb.data_misses 6644 # DTB misses system.cpu0.dtb.data_acv 190 # DTB access violations -system.cpu0.dtb.data_accesses 592294 # DTB accesses -system.cpu0.itb.fetch_hits 2727685 # ITB hits +system.cpu0.dtb.data_accesses 592295 # DTB accesses +system.cpu0.itb.fetch_hits 2728150 # ITB hits system.cpu0.itb.fetch_misses 3015 # ITB misses system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2730700 # ITB accesses +system.cpu0.itb.fetch_accesses 2731165 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -798,87 +794,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 929885466 # number of cpu cycles simulated +system.cpu0.numCycles 929887646 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30965233 # Number of instructions committed -system.cpu0.committedOps 30965233 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28877959 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 164894 # Number of float alu accesses -system.cpu0.num_func_calls 798570 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3871145 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28877959 # number of integer instructions -system.cpu0.num_fp_insts 164894 # number of float instructions -system.cpu0.num_int_register_reads 39995093 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21215374 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85232 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86749 # number of times the floating registers were written -system.cpu0.num_mem_refs 8278255 # number of memory refs -system.cpu0.num_load_insts 4840998 # Number of load instructions -system.cpu0.num_store_insts 3437257 # Number of store instructions -system.cpu0.num_idle_cycles 908001022.276160 # Number of idle cycles -system.cpu0.num_busy_cycles 21884443.723840 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023535 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976465 # Percentage of idle cycles -system.cpu0.Branches 4926958 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1578460 5.10% 5.10% # Class of executed instruction -system.cpu0.op_class::IntAlu 20418617 65.93% 71.02% # Class of executed instruction -system.cpu0.op_class::IntMult 31850 0.10% 71.13% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12902 0.04% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1598 0.01% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::MemRead 4971884 16.05% 87.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 3440357 11.11% 98.33% # Class of executed instruction -system.cpu0.op_class::IprAccess 516399 1.67% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30964546 # Number of instructions committed +system.cpu0.committedOps 30964546 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28877269 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 164895 # Number of float alu accesses +system.cpu0.num_func_calls 798898 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3870413 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28877269 # number of integer instructions +system.cpu0.num_fp_insts 164895 # number of float instructions +system.cpu0.num_int_register_reads 39993375 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21214284 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85263 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86719 # number of times the floating registers were written +system.cpu0.num_mem_refs 8280000 # number of memory refs +system.cpu0.num_load_insts 4841351 # Number of load instructions +system.cpu0.num_store_insts 3438649 # Number of store instructions +system.cpu0.num_idle_cycles 908004121.642144 # Number of idle cycles +system.cpu0.num_busy_cycles 21883524.357856 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023534 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976466 # Percentage of idle cycles +system.cpu0.Branches 4926659 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1578204 5.10% 5.10% # Class of executed instruction +system.cpu0.op_class::IntAlu 20416117 65.92% 71.01% # Class of executed instruction +system.cpu0.op_class::IntMult 31858 0.10% 71.12% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12902 0.04% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1598 0.01% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::MemRead 4972343 16.05% 87.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 3441751 11.11% 98.33% # Class of executed instruction +system.cpu0.op_class::IprAccess 516607 1.67% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30972067 # Class of executed instruction +system.cpu0.op_class::total 30971380 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211354 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182556 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818769989500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39220500 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357294000 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22445011500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841611515500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818780188000 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39182000 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357649000 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22434661500 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841611680500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815832 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -917,7 +913,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175299 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -926,20 +922,20 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192209 # number of callpals executed +system.cpu0.kern.callpal::total 192210 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1906 -system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29707694000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2577107000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809326710000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29705567000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2577814500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809328294500 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -972,459 +968,479 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 112481926 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 825463 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 825443 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3528 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3528 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 385263 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17281 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 137914 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 137914 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 903973 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1415042 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2319015 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 28925888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 57212080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 86137968 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 204476224 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2671872 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2218881500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 2062606 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2062584 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835833 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17283 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 38 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302707 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302707 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 7 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1928849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657196 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5586045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61721856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142735808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204457664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41925 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3235706 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012896 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112826 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3193978 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 41728 1.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3235706 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2218971499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2036319024 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2034366165 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2306325269 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2306919756 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1470003 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2992 # Transaction distribution -system.iobus.trans_dist::ReadResp 2992 # Transaction distribution -system.iobus.trans_dist::WriteReq 20808 # Transaction distribution -system.iobus.trans_dist::WriteResp 20808 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 7420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2926 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 12900 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47600 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 55 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 3710 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 2083 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 16 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1123168 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2707176 # Total data (bytes) +system.iobus.trans_dist::ReadReq 7317 # Transaction distribution +system.iobus.trans_dist::ReadResp 7317 # Transaction distribution +system.iobus.trans_dist::WriteReq 51362 # Transaction distribution +system.iobus.trans_dist::WriteResp 27090 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 24272 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5525000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5523000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2081000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2079000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer29.occupancy 155677802 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9372000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9370000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17532750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17534501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 964098 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.196429 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 40281211 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 964609 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 41.759108 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10190294250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 265.809335 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 64.640468 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.746626 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.519159 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.126251 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.353021 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 963743 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.196442 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 40274426 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 964254 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 41.767445 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10190503250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.296847 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.404531 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.495065 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.514252 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131649 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.352529 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998431 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42226967 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42226967 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30459275 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7343645 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2478291 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 40281211 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30459275 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7343645 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2478291 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 40281211 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30459275 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7343645 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2478291 # number of overall hits -system.cpu0.icache.overall_hits::total 40281211 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 512792 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 124421 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 343745 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 980958 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 512792 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 124421 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 343745 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 980958 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 512792 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 124421 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 343745 # number of overall misses -system.cpu0.icache.overall_misses::total 980958 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1775017500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4831640896 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6606658396 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1775017500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4831640896 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6606658396 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1775017500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4831640896 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6606658396 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30972067 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7468066 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2822036 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41262169 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30972067 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7468066 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2822036 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41262169 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30972067 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7468066 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2822036 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41262169 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016557 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016660 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121807 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023774 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016557 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016660 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121807 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023774 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016557 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016660 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121807 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023774 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.221136 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14055.887056 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6734.904446 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14266.221136 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14055.887056 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6734.904446 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14266.221136 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14055.887056 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6734.904446 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3704 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42219519 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42219519 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30458523 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7341413 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2474490 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 40274426 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30458523 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7341413 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2474490 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 40274426 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30458523 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7341413 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2474490 # number of overall hits +system.cpu0.icache.overall_hits::total 40274426 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 512857 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 124138 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 343653 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 980648 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 512857 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 124138 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 343653 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 980648 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 512857 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 124138 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 343653 # number of overall misses +system.cpu0.icache.overall_misses::total 980648 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1770888500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4833799298 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6604687798 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1770888500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4833799298 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6604687798 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1770888500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4833799298 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6604687798 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30971380 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7465551 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2818143 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 41255074 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30971380 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7465551 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2818143 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41255074 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30971380 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7465551 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2818143 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41255074 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016559 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016628 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121943 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023770 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016559 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016628 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121943 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023770 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016559 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016628 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121943 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023770 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14265.482769 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14065.930744 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6735.023982 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14265.482769 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14065.930744 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6735.023982 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14265.482769 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14065.930744 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6735.023982 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3646 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.917160 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.645963 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16160 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16160 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16160 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16160 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16160 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16160 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124421 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327585 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 452006 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 124421 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 327585 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 452006 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 124421 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 327585 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 452006 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1525261500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3997287463 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5522548963 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1525261500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3997287463 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5522548963 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1525261500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3997287463 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5522548963 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010954 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010954 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010954 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.866495 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.866495 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.866495 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16203 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16203 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16203 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16203 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16203 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16203 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124138 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327450 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 451588 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 124138 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 327450 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 451588 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 124138 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 327450 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 451588 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1521699500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3997566325 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5519265825 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1521699500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3997566325 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5519265825 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1521699500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3997566325 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5519265825 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010946 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010946 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010946 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.905420 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.905420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.905420 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1393139 # number of replacements +system.cpu0.dcache.tags.replacements 1393134 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13262993 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393651 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13262946 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393646 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 9.516725 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.896843 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.443174 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.657800 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509564 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.145397 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345035 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 261.690760 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.796063 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 175.510993 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.511115 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146086 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.342795 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63351520 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63351520 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 3995753 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1055109 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2515938 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7566800 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3139218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 809021 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1363953 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5312192 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114493 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18830 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51280 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184603 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123317 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20808 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55196 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 63351559 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63351559 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3996259 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1054031 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2516397 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7566687 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3140432 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 808252 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1363715 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5312399 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114574 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18764 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51112 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184450 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123404 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20737 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55180 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199321 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7134971 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1864130 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3879891 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12878992 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7134971 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1864130 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3879891 # number of overall hits -system.cpu0.dcache.overall_hits::total 12878992 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 711080 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 94884 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 563934 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1369898 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 164839 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43578 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 629063 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 837480 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9371 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2106 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7687 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19164 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 9 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 875919 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 138462 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1192997 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2207378 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 875919 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 138462 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1192997 # number of overall misses -system.cpu0.dcache.overall_misses::total 2207378 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2196286000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9809622346 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12005908346 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1651405510 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 20350366997 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 22001772507 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27755500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 126986999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 154742499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 143002 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 143002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3847691510 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 30159989343 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34007680853 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3847691510 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 30159989343 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34007680853 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4706833 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1149993 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3079872 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8936698 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3304057 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 852599 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1993016 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149672 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123864 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20936 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58967 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203767 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123317 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20808 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55205 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199330 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8010890 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2002592 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5072888 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15086370 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8010890 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2002592 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5072888 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15086370 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151074 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082508 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.183103 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.153289 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049890 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051112 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315634 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136183 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075656 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100592 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130361 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094049 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000163 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109341 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069141 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.235171 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146316 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109341 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069141 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.235171 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146316 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23147.063783 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17394.983005 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8764.089258 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37895.394695 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32350.284466 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 26271.400519 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.249763 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16519.708469 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8074.645116 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15889.111111 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15889.111111 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27788.790498 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25280.859334 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15406.369391 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27788.790498 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25280.859334 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15406.369391 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 895030 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1251 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 63218 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.157835 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 113.727273 # average number of cycles each access was blocked +system.cpu0.dcache.demand_hits::cpu0.data 7136691 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1862283 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3880112 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12879086 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7136691 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1862283 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3880112 # number of overall hits +system.cpu0.dcache.overall_hits::total 12879086 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 710837 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 95497 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 564447 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1370781 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 164929 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 43579 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 628162 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 836670 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9380 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2101 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7681 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19162 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 8 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 875766 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 139076 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1192609 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2207451 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 875766 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 139076 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1192609 # number of overall misses +system.cpu0.dcache.overall_misses::total 2207451 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2207514000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9811838599 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 12019352599 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1651311760 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 20363561979 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 22014873739 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27705250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 128352996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 156058246 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 130502 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 130502 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 3858825760 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 30175400578 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34034226338 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3858825760 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 30175400578 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34034226338 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4707096 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1149528 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3080844 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8937468 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3305361 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 851831 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1991877 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6149069 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123954 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20865 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58793 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203612 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123404 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20737 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55188 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199329 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8012457 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2001359 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5072721 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15086537 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8012457 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2001359 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5072721 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15086537 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151014 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083075 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.183212 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.153375 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049897 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051159 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315362 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136065 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075673 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100695 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130645 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094110 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000145 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109301 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069491 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.235102 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146319 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109301 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069491 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.235102 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146319 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23116.056002 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17383.099917 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8768.251529 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37892.373850 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32417.691581 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 26312.493264 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13186.696811 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16710.453847 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8144.152281 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16312.750000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16312.750000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27746.165837 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25302.006423 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15417.885307 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27746.165837 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25302.006423 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15417.885307 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 891586 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 724 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 62691 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.221914 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 80.444444 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835818 # number of writebacks -system.cpu0.dcache.writebacks::total 835818 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 296217 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 296217 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 534994 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 534994 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1640 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1640 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 831211 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 831211 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 831211 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 831211 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 94884 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 267717 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 362601 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43578 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 94069 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 137647 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2106 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6047 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8153 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 138462 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 361786 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 500248 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 138462 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 361786 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 500248 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1998980000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4480743134 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6479723134 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1555929490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2922490326 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4478419816 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23542500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72865001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96407501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 124998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 124998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3554909490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7403233460 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10958142950 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3554909490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7403233460 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10958142950 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249968500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342709000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 592677500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320834500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419662000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740496500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 570803000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762371000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1333174000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082508 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086925 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040574 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051112 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047199 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022383 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100592 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102549 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040011 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000163 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071318 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033159 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071318 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033159 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21067.619409 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.864428 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17870.119316 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35704.472211 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31067.517737 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32535.542482 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.774929 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12049.776914 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11824.788544 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13888.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13888.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835833 # number of writebacks +system.cpu0.dcache.writebacks::total 835833 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 297087 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 297087 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 534212 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 534212 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1624 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1624 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 831299 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 831299 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 831299 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 831299 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 95497 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 267360 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 362857 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43579 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 93950 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137529 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2101 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6057 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8158 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 139076 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 361310 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 500386 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 139076 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 361310 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 500386 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2008989000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4477810640 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6486799640 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1555821240 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2924918842 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4480740082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23501750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 73479753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96981503 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 114498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 114498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3564810240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7402729482 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10967539722 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3564810240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7402729482 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10967539722 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249745500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342957000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 592702500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320247000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 420262500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740509500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569992500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 763219500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1333212000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083075 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086781 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040600 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051159 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047167 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022366 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100695 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103022 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040066 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000145 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033168 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033168 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21037.194886 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16748.244464 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17877.013920 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35701.168912 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31132.717850 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32580.329109 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11185.982865 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12131.377415 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11887.901814 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14312.250000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14312.250000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1439,22 +1455,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1168812 # DTB read hits -system.cpu1.dtb.read_misses 1325 # DTB read misses -system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 141647 # DTB read accesses -system.cpu1.dtb.write_hits 873733 # DTB write hits -system.cpu1.dtb.write_misses 170 # DTB write misses +system.cpu1.dtb.read_hits 1168269 # DTB read hits +system.cpu1.dtb.read_misses 1330 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 141659 # DTB read accesses +system.cpu1.dtb.write_hits 872893 # DTB write hits +system.cpu1.dtb.write_misses 171 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57095 # DTB write accesses -system.cpu1.dtb.data_hits 2042545 # DTB hits -system.cpu1.dtb.data_misses 1495 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 198742 # DTB accesses -system.cpu1.itb.fetch_hits 849434 # ITB hits -system.cpu1.itb.fetch_misses 664 # ITB misses +system.cpu1.dtb.write_accesses 57101 # DTB write accesses +system.cpu1.dtb.data_hits 2041162 # DTB hits +system.cpu1.dtb.data_misses 1501 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 198760 # DTB accesses +system.cpu1.itb.fetch_hits 849127 # ITB hits +system.cpu1.itb.fetch_misses 665 # ITB misses system.cpu1.itb.fetch_acv 34 # ITB acv -system.cpu1.itb.fetch_accesses 850098 # ITB accesses +system.cpu1.itb.fetch_accesses 849792 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1467,64 +1483,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953402608 # number of cpu cycles simulated +system.cpu1.numCycles 953403050 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7466514 # Number of instructions committed -system.cpu1.committedOps 7466514 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6940405 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43972 # Number of float alu accesses -system.cpu1.num_func_calls 203873 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 905018 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6940405 # number of integer instructions -system.cpu1.num_fp_insts 43972 # number of float instructions -system.cpu1.num_int_register_reads 9656232 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5062933 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23750 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written -system.cpu1.num_mem_refs 2049510 # number of memory refs -system.cpu1.num_load_insts 1173515 # Number of load instructions -system.cpu1.num_store_insts 875995 # Number of store instructions -system.cpu1.num_idle_cycles 923975227.132686 # Number of idle cycles -system.cpu1.num_busy_cycles 29427380.867314 # Number of busy cycles +system.cpu1.committedInsts 7463992 # Number of instructions committed +system.cpu1.committedOps 7463992 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6937939 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 43895 # Number of float alu accesses +system.cpu1.num_func_calls 203449 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 905325 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6937939 # number of integer instructions +system.cpu1.num_fp_insts 43895 # number of float instructions +system.cpu1.num_int_register_reads 9652072 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5060714 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 23736 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24066 # number of times the floating registers were written +system.cpu1.num_mem_refs 2048141 # number of memory refs +system.cpu1.num_load_insts 1172984 # Number of load instructions +system.cpu1.num_store_insts 875157 # Number of store instructions +system.cpu1.num_idle_cycles 923975246.943285 # Number of idle cycles +system.cpu1.num_busy_cycles 29427803.056715 # Number of busy cycles system.cpu1.not_idle_fraction 0.030866 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969134 # Percentage of idle cycles -system.cpu1.Branches 1173577 # Number of branches fetched -system.cpu1.op_class::No_OpClass 399506 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 4845173 64.88% 70.23% # Class of executed instruction -system.cpu1.op_class::IntMult 8216 0.11% 70.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5112 0.07% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::MemRead 1201694 16.09% 86.51% # Class of executed instruction -system.cpu1.op_class::MemWrite 877208 11.75% 98.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 130346 1.75% 100.00% # Class of executed instruction +system.cpu1.Branches 1173357 # Number of branches fetched +system.cpu1.op_class::No_OpClass 399705 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 4844088 64.89% 70.24% # Class of executed instruction +system.cpu1.op_class::IntMult 8214 0.11% 70.35% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5110 0.07% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::MemRead 1201071 16.09% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 876369 11.74% 98.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 130183 1.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7468065 # Class of executed instruction +system.cpu1.op_class::total 7465550 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1542,35 +1558,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9007020 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8266685 # Number of conditional branches predicted +system.cpu2.branchPred.lookups 9020137 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8282573 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 125563 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6913379 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 4889018 # Number of BTB hits +system.cpu2.branchPred.BTBLookups 6965204 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 4892106 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 70.718212 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 301119 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7670 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.236364 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 299658 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7807 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3485225 # DTB read hits -system.cpu2.dtb.read_misses 12620 # DTB read misses +system.cpu2.dtb.read_hits 3485260 # DTB read hits +system.cpu2.dtb.read_misses 12402 # DTB read misses system.cpu2.dtb.read_acv 152 # DTB read access violations -system.cpu2.dtb.read_accesses 227645 # DTB read accesses -system.cpu2.dtb.write_hits 2140940 # DTB write hits -system.cpu2.dtb.write_misses 2817 # DTB write misses -system.cpu2.dtb.write_acv 139 # DTB write access violations -system.cpu2.dtb.write_accesses 85106 # DTB write accesses -system.cpu2.dtb.data_hits 5626165 # DTB hits -system.cpu2.dtb.data_misses 15437 # DTB misses -system.cpu2.dtb.data_acv 291 # DTB access violations -system.cpu2.dtb.data_accesses 312751 # DTB accesses -system.cpu2.itb.fetch_hits 539657 # ITB hits -system.cpu2.itb.fetch_misses 5944 # ITB misses -system.cpu2.itb.fetch_acv 165 # ITB acv -system.cpu2.itb.fetch_accesses 545601 # ITB accesses +system.cpu2.dtb.read_accesses 227268 # DTB read accesses +system.cpu2.dtb.write_hits 2138350 # DTB write hits +system.cpu2.dtb.write_misses 2805 # DTB write misses +system.cpu2.dtb.write_acv 140 # DTB write access violations +system.cpu2.dtb.write_accesses 85115 # DTB write accesses +system.cpu2.dtb.data_hits 5623610 # DTB hits +system.cpu2.dtb.data_misses 15207 # DTB misses +system.cpu2.dtb.data_acv 292 # DTB access violations +system.cpu2.dtb.data_accesses 312383 # DTB accesses +system.cpu2.itb.fetch_hits 538601 # ITB hits +system.cpu2.itb.fetch_misses 5813 # ITB misses +system.cpu2.itb.fetch_acv 166 # ITB acv +system.cpu2.itb.fetch_accesses 544414 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1583,259 +1599,259 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 29515720 # number of cpu cycles simulated +system.cpu2.numCycles 29513686 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9404916 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 35474807 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9007020 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5190137 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18003717 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 410566 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 517 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1999 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 235781 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 98995 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 442 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2822037 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 92550 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27961187 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.268716 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.388099 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9389582 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 35469274 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9020137 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5191764 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18021119 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 410530 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 647 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 228650 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 98931 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 387 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2818143 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 92772 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27955647 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.268770 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.388372 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20241670 72.39% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312691 1.12% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 474251 1.70% 75.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3278987 11.73% 86.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 837934 3.00% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194435 0.70% 90.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 239683 0.86% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 437644 1.57% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1943892 6.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20239272 72.40% 72.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 311789 1.12% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 473018 1.69% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3278988 11.73% 86.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 836372 2.99% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194449 0.70% 90.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 239819 0.86% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 437682 1.57% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1944258 6.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27961187 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.305160 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.201895 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7704419 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13193149 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6090024 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 535254 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 192290 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 176132 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13346 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 32094888 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42715 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 192290 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7987526 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4830275 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6354829 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6312082 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2038145 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 31271508 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68877 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 405466 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 55957 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 963204 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 20931686 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 38638449 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 38578281 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56251 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 19026086 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1905600 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 533120 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63723 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3942739 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3510198 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2234995 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 462280 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329256 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 28739879 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 680947 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 28391596 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 17529 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2438506 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1151582 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 487021 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27961187 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.015393 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.594251 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27955647 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.305626 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.201791 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7697914 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13194592 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6089531 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 535341 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 192357 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 175638 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13257 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 32098439 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42458 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 192357 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7981444 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4806689 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6360452 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6310892 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2057913 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 31276153 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 68586 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 406035 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57262 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 980638 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 20937225 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 38641604 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 38581458 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56230 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 19023888 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1913337 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 532654 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63537 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3939185 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3509523 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2229292 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 463055 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 331167 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 28745476 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 680921 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 28394222 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16375 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2445259 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1154216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 487025 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27955647 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.015688 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.594887 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17574861 62.85% 62.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2788082 9.97% 72.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1379347 4.93% 77.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4037262 14.44% 92.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1018579 3.64% 95.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 572705 2.05% 97.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 385941 1.38% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 155733 0.56% 99.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48677 0.17% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17573743 62.86% 62.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2782129 9.95% 72.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1379697 4.94% 77.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4038946 14.45% 92.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1015784 3.63% 95.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 573145 2.05% 97.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 387606 1.39% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 155412 0.56% 99.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 49185 0.18% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27961187 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27955647 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 82533 21.35% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 178965 46.29% 67.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 125088 32.36% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 83781 21.60% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179225 46.21% 67.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 124810 32.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 22261960 78.41% 78.42% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21111 0.07% 78.49% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20516 0.07% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3614417 12.73% 91.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2165470 7.63% 98.93% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 304438 1.07% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 22268545 78.43% 78.43% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21109 0.07% 78.51% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20518 0.07% 78.58% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.58% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.58% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.58% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3613635 12.73% 91.31% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2162330 7.62% 98.93% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 304401 1.07% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 28391596 # Type of FU issued -system.cpu2.iq.rate 0.961914 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 386586 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013616 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 84894790 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 31745632 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27810644 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 253704 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119619 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117118 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 28639647 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136079 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206810 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 28394222 # Type of FU issued +system.cpu2.iq.rate 0.962070 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387816 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013658 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 84894498 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 31757890 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27813110 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253784 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119651 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117192 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 28643478 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136104 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207211 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 438537 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1486 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6057 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 183313 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 438819 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1413 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6020 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178766 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5003 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 177760 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5023 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 176307 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 192290 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4010862 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 349296 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 30806306 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 54542 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3510198 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2234995 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 606167 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15566 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 285460 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6057 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62858 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 135105 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197963 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 28193561 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3506622 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 198035 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 192357 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4003600 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 328635 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 30811270 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51966 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3509523 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2229292 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 606230 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15640 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 265026 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6020 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63511 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134698 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 198209 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 28196871 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3506429 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 197351 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1385480 # number of nop insts executed -system.cpu2.iew.exec_refs 5655108 # number of memory reference insts executed -system.cpu2.iew.exec_branches 5954900 # Number of branches executed -system.cpu2.iew.exec_stores 2148486 # Number of stores executed -system.cpu2.iew.exec_rate 0.955205 # Inst execution rate -system.cpu2.iew.wb_sent 27969918 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27927762 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15888662 # num instructions producing a value -system.cpu2.iew.wb_consumers 19538696 # num instructions consuming a value +system.cpu2.iew.exec_nop 1384873 # number of nop insts executed +system.cpu2.iew.exec_refs 5652310 # number of memory reference insts executed +system.cpu2.iew.exec_branches 5956275 # Number of branches executed +system.cpu2.iew.exec_stores 2145881 # Number of stores executed +system.cpu2.iew.exec_rate 0.955383 # Inst execution rate +system.cpu2.iew.wb_sent 27971955 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27930302 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15891558 # num instructions producing a value +system.cpu2.iew.wb_consumers 19546280 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.946200 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.813189 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.946351 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.813022 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2672008 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 193926 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180997 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27494343 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.021637 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.858517 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2680068 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 193896 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 181086 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27486207 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.021790 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.858200 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18377188 66.84% 66.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2251123 8.19% 75.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1180007 4.29% 79.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 3743706 13.62% 92.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 543464 1.98% 94.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 201872 0.73% 95.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 166281 0.60% 96.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179533 0.65% 96.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 851169 3.10% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18368842 66.83% 66.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2248676 8.18% 75.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1182960 4.30% 79.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 3745017 13.63% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 544035 1.98% 94.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 201250 0.73% 95.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 165260 0.60% 96.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179807 0.65% 96.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 850360 3.09% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27494343 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 28089240 # Number of instructions committed -system.cpu2.commit.committedOps 28089240 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27486207 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 28085126 # Number of instructions committed +system.cpu2.commit.committedOps 28085126 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5123343 # Number of memory references committed -system.cpu2.commit.loads 3071661 # Number of loads committed -system.cpu2.commit.membars 68272 # Number of memory barriers committed -system.cpu2.commit.branches 5784239 # Number of branches committed -system.cpu2.commit.fp_insts 115390 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 26574373 # Number of committed integer instructions. -system.cpu2.commit.function_calls 240380 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1220895 4.35% 4.35% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 21328709 75.93% 80.28% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.35% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.35% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20067 0.07% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.refs 5121230 # Number of memory references committed +system.cpu2.commit.loads 3070704 # Number of loads committed +system.cpu2.commit.membars 68250 # Number of memory barriers committed +system.cpu2.commit.branches 5783973 # Number of branches committed +system.cpu2.commit.fp_insts 115466 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 26570607 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240322 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1220562 4.35% 4.35% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 21327099 75.94% 80.28% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.36% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20069 0.07% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.43% # Class of committed instruction @@ -1858,30 +1874,30 @@ system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.43% system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3139933 11.18% 91.61% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2053319 7.31% 98.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 304438 1.08% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3138954 11.18% 91.61% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2052162 7.31% 98.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 304401 1.08% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 28089240 # Class of committed instruction -system.cpu2.commit.bw_lim_events 851169 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 28085126 # Class of committed instruction +system.cpu2.commit.bw_lim_events 850360 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 57327258 # The number of ROB reads -system.cpu2.rob.rob_writes 61989353 # The number of ROB writes -system.cpu2.timesIdled 175568 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1554533 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746289037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 26870801 # Number of Instructions Simulated -system.cpu2.committedOps 26870801 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.098431 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.098431 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.910389 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.910389 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 36957190 # number of integer regfile reads -system.cpu2.int_regfile_writes 19824047 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70953 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70972 # number of floating regfile writes -system.cpu2.misc_regfile_reads 3637810 # number of misc regfile reads -system.cpu2.misc_regfile_writes 273227 # number of misc regfile writes +system.cpu2.rob.rob_reads 57323983 # The number of ROB reads +system.cpu2.rob.rob_writes 61998256 # The number of ROB writes +system.cpu2.timesIdled 175445 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1558039 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746293269 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 26867020 # Number of Instructions Simulated +system.cpu2.committedOps 26867020 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.098510 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.098510 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.910324 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.910324 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 36957336 # number of integer regfile reads +system.cpu2.int_regfile_writes 19827241 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70923 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71075 # number of floating regfile writes +system.cpu2.misc_regfile_reads 3638892 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273174 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |