diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
3 files changed, 4412 insertions, 4272 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 213dc1867..fc255dc72 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,135 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.902739 # Number of seconds simulated -sim_ticks 1902738973500 # Number of ticks simulated -final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904665 # Number of seconds simulated +sim_ticks 1904665099500 # Number of ticks simulated +final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132013 # Simulator instruction rate (inst/s) -host_op_rate 132013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4427958303 # Simulator tick rate (ticks/s) -host_mem_usage 313120 # Number of bytes of host memory used -host_seconds 429.71 # Real time elapsed on the host -sim_insts 56727331 # Number of instructions simulated -sim_ops 56727331 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24806400 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 74944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 436992 # Number of bytes read from this memory -system.physmem.bytes_read::total 28869696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 900544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 74944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 975488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7821440 # Number of bytes written to this memory -system.physmem.bytes_written::total 7821440 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387600 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122210 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122210 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 473288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13037206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1393158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 39387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 229665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15172704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 473288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 39387 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4110622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4110622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4110622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 473288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13037206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1393158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 39387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 229665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19283326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451089 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 122210 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 451089 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 122210 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28869696 # Total number of bytes read from memory -system.physmem.bytesWritten 7821440 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28869696 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7821440 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4926 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28357 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7885 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7637 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6924 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 6873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7305 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7954 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8091 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7908 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1902738952500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451089 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 122210 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +host_inst_rate 126318 # Simulator instruction rate (inst/s) +host_op_rate 126318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4285588150 # Simulator tick rate (ticks/s) +host_mem_usage 339596 # Number of bytes of host memory used +host_seconds 444.44 # Real time elapsed on the host +sim_insts 56140339 # Number of instructions simulated +sim_ops 56140339 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory +system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory +system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450624 # Number of read requests accepted +system.physmem.writeReqs 122060 # Number of write requests accepted +system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue +system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28171 # Per bank write bursts +system.physmem.perBankRdBursts::1 27944 # Per bank write bursts +system.physmem.perBankRdBursts::2 28133 # Per bank write bursts +system.physmem.perBankRdBursts::3 27978 # Per bank write bursts +system.physmem.perBankRdBursts::4 27881 # Per bank write bursts +system.physmem.perBankRdBursts::5 28082 # Per bank write bursts +system.physmem.perBankRdBursts::6 28123 # Per bank write bursts +system.physmem.perBankRdBursts::7 28118 # Per bank write bursts +system.physmem.perBankRdBursts::8 28377 # Per bank write bursts +system.physmem.perBankRdBursts::9 28284 # Per bank write bursts +system.physmem.perBankRdBursts::10 27947 # Per bank write bursts +system.physmem.perBankRdBursts::11 28190 # Per bank write bursts +system.physmem.perBankRdBursts::12 28259 # Per bank write bursts +system.physmem.perBankRdBursts::13 28280 # Per bank write bursts +system.physmem.perBankRdBursts::14 28300 # Per bank write bursts +system.physmem.perBankRdBursts::15 28502 # Per bank write bursts +system.physmem.perBankWrBursts::0 7913 # Per bank write bursts +system.physmem.perBankWrBursts::1 7477 # Per bank write bursts +system.physmem.perBankWrBursts::2 7607 # Per bank write bursts +system.physmem.perBankWrBursts::3 7420 # Per bank write bursts +system.physmem.perBankWrBursts::4 7384 # Per bank write bursts +system.physmem.perBankWrBursts::5 7571 # Per bank write bursts +system.physmem.perBankWrBursts::6 7682 # Per bank write bursts +system.physmem.perBankWrBursts::7 7471 # Per bank write bursts +system.physmem.perBankWrBursts::8 7660 # Per bank write bursts +system.physmem.perBankWrBursts::9 7641 # Per bank write bursts +system.physmem.perBankWrBursts::10 7379 # Per bank write bursts +system.physmem.perBankWrBursts::11 7517 # Per bank write bursts +system.physmem.perBankWrBursts::12 7673 # Per bank write bursts +system.physmem.perBankWrBursts::13 7762 # Per bank write bursts +system.physmem.perBankWrBursts::14 7923 # Per bank write bursts +system.physmem.perBankWrBursts::15 7975 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1904663535000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 450624 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 122060 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 322714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -139,396 +141,458 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 906.491388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 223.789110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2353.116019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14451 35.71% 35.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6072 15.00% 50.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3826 9.45% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2468 6.10% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1670 4.13% 70.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1520 3.76% 74.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1058 2.61% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 819 2.02% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 687 1.70% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 564 1.39% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 556 1.37% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 509 1.26% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 268 0.66% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 232 0.57% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 203 0.50% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 288 0.71% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 119 0.29% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 109 0.27% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 110 0.27% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 196 0.48% 88.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 119 0.29% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 500 1.24% 90.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 628 1.55% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 91 0.22% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 33 0.08% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 99 0.24% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 30 0.07% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 12 0.03% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 48 0.12% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 23 0.06% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 33 0.08% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 7 0.02% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 3 0.01% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.00% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2429 6.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 243 0.60% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40469 # Bytes accessed per row activation -system.physmem.totQLat 6403559750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13868349750 # Sum of mem lat for all requests -system.physmem.totBusLat 2255080000 # Total cycles spent in databus access -system.physmem.totBankLat 5209710000 # Total cycles spent in bank access -system.physmem.avgQLat 14198.08 # Average queueing delay per request -system.physmem.avgBankLat 11551.05 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30749.13 # Average memory access latency -system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 55 0.12% 94.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 21 0.05% 94.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 49 0.11% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 50 0.11% 94.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 11 0.02% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 26 0.06% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 38 0.08% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 26 0.06% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 54 0.12% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 52 0.11% 95.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 22 0.05% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 49 0.11% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 39 0.08% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 31 0.07% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 44 0.09% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 9 0.02% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 51 0.11% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 50 0.11% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 23 0.05% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 20 0.04% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 23 0.05% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 51 0.11% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 49 0.11% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 7 0.02% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 28 0.06% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 86 0.19% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 45 0.10% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 319 0.69% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 8 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 15 0.03% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 7 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 319 0.69% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation +system.physmem.totQLat 8608105750 # Total ticks spent queuing +system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks +system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.36 # Average write queue length over time -system.physmem.readRowHits 435126 # Number of row buffer hits during reads -system.physmem.writeRowHits 97620 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.88 # Row buffer hit rate for writes -system.physmem.avgGap 3318929.48 # Average gap between requests -system.membus.throughput 19341454 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296468 # Transaction distribution -system.membus.trans_dist::ReadResp 296394 # Transaction distribution -system.membus.trans_dist::WriteReq 13061 # Transaction distribution -system.membus.trans_dist::WriteResp 13061 # Transaction distribution -system.membus.trans_dist::Writeback 122210 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9880 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5735 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4929 # Transaction distribution -system.membus.trans_dist::ReadExReq 162867 # Transaction distribution -system.membus.trans_dist::ReadExResp 162463 # Transaction distribution -system.membus.trans_dist::BadAddressError 74 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921241 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 961899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1086565 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73866 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31383040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31456906 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36765002 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36765002 # Total data (bytes) -system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37911498 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing +system.physmem.readRowHits 429097 # Number of row buffer hits during reads +system.physmem.writeRowHits 97193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes +system.physmem.avgGap 3325854.28 # Average gap between requests +system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19299112 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296504 # Transaction distribution +system.membus.trans_dist::ReadResp 296255 # Transaction distribution +system.membus.trans_dist::WriteReq 12358 # Transaction distribution +system.membus.trans_dist::WriteResp 12358 # Transaction distribution +system.membus.trans_dist::Writeback 122060 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution +system.membus.trans_dist::ReadExReq 162296 # Transaction distribution +system.membus.trans_dist::ReadExResp 162161 # Transaction distribution +system.membus.trans_dist::BadAddressError 249 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36720010 # Total data (bytes) +system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1609327499 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 93500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3831145563 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376230495 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 344151 # number of replacements -system.l2c.tags.tagsinuse 65253.870311 # Cycle average of tags in use -system.l2c.tags.total_refs 2581362 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409161 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.308915 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53541.051154 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5362.839741 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6144.208257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 141.383324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 64.387836 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816972 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081830 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093753 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002157 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000982 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995695 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 862836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 735075 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 214357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 69353 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1881621 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822225 # number of Writeback hits -system.l2c.Writeback_hits::total 822225 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 270 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 439 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24133629433 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 777853501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 21666302610 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 270265519 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1419207803 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24133629433 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929130500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460152500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389283000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1572515500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890654999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2463170499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2501646000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350807499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3852453499 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.323533 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007131 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132537 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.947447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.863208 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.931305 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.611111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.763359 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.701357 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425897 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.233145 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.387874 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164429 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164429 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52570.375166 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79271.304013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53586.446156 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.256098 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10123.943534 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.278227 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10919.127273 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.980000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10349.354839 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69185.666864 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89037.241690 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71539.478604 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -666,39 +730,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.476417 # Cycle average of tags in use +system.iocache.tags.replacements 41697 # number of replacements +system.iocache.tags.tagsinuse 0.224170 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.476417 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029776 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029776 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.warmup_cycle 1712302770000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.224170 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.014011 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.014011 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21570383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21570383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10493964012 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10493964012 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10515534395 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10515534395 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10515534395 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10515534395 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -707,40 +771,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123259.331429 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123259.331429 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252550.154313 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 252550.154313 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 252007.918015 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 252007.918015 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 275771 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27285 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.107055 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12468883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8331886522 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8331886522 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8344355405 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8344355405 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8344355405 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8344355405 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -749,14 +813,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71250.760000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71250.760000 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200517.099586 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 200517.099586 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -770,35 +834,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12458299 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10491650 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 332886 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8054816 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5283733 # Number of BTB hits +system.cpu0.branchPred.lookups 10889682 # Number of BP lookups +system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.597191 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 799392 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28656 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8872852 # DTB read hits -system.cpu0.dtb.read_misses 32010 # DTB read misses -system.cpu0.dtb.read_acv 540 # DTB read access violations -system.cpu0.dtb.read_accesses 628428 # DTB read accesses -system.cpu0.dtb.write_hits 5797852 # DTB write hits -system.cpu0.dtb.write_misses 8130 # DTB write misses -system.cpu0.dtb.write_acv 348 # DTB write access violations -system.cpu0.dtb.write_accesses 210128 # DTB write accesses -system.cpu0.dtb.data_hits 14670704 # DTB hits -system.cpu0.dtb.data_misses 40140 # DTB misses -system.cpu0.dtb.data_acv 888 # DTB access violations -system.cpu0.dtb.data_accesses 838556 # DTB accesses -system.cpu0.itb.fetch_hits 994919 # ITB hits -system.cpu0.itb.fetch_misses 28800 # ITB misses -system.cpu0.itb.fetch_acv 922 # ITB acv -system.cpu0.itb.fetch_accesses 1023719 # ITB accesses +system.cpu0.dtb.read_hits 7794998 # DTB read hits +system.cpu0.dtb.read_misses 29740 # DTB read misses +system.cpu0.dtb.read_acv 552 # DTB read access violations +system.cpu0.dtb.read_accesses 624038 # DTB read accesses +system.cpu0.dtb.write_hits 5176736 # DTB write hits +system.cpu0.dtb.write_misses 7776 # DTB write misses +system.cpu0.dtb.write_acv 327 # DTB write access violations +system.cpu0.dtb.write_accesses 207382 # DTB write accesses +system.cpu0.dtb.data_hits 12971734 # DTB hits +system.cpu0.dtb.data_misses 37516 # DTB misses +system.cpu0.dtb.data_acv 879 # DTB access violations +system.cpu0.dtb.data_accesses 831420 # DTB accesses +system.cpu0.itb.fetch_hits 929400 # ITB hits +system.cpu0.itb.fetch_misses 28175 # ITB misses +system.cpu0.itb.fetch_acv 908 # ITB acv +system.cpu0.itb.fetch_accesses 957575 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -811,269 +875,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 114636003 # number of cpu cycles simulated +system.cpu0.numCycles 103787820 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25048083 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63888139 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12458299 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6083125 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12009946 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1716539 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37364333 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31995 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 196940 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 358937 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 467 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7724257 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 222992 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76114982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177033 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64105036 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 766655 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1565630 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 705022 0.93% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2586372 3.40% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 523946 0.69% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578047 0.76% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 832534 1.09% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4451740 5.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76114982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.108677 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.557313 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26317520 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36878715 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10917325 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 932522 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1068899 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 511897 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35733 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62704701 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 106993 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1068899 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27334042 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15040257 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18326535 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10227103 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4118144 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59323627 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7153 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 638131 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72093935 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 128190 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 211881 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11242711 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9290886 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6078694 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1146384 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 744084 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52609114 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1811011 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51412755 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 100173 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5939256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3114263 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1226583 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76114982 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.675462 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.326460 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53279780 70.00% 70.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10372988 13.63% 83.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4693410 6.17% 89.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3092664 4.06% 93.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2443569 3.21% 97.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1213853 1.59% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 652140 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 314050 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52528 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76114982 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82827 12.15% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 318873 46.78% 58.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 279966 41.07% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35420825 68.90% 68.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56384 0.11% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15702 0.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9231506 17.96% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5866326 11.41% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 816348 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51412755 # Type of FU issued -system.cpu0.iq.rate 0.448487 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 681666 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013259 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 179170597 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60104783 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50356616 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 551733 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267128 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260409 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51801972 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288664 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 541765 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued +system.cpu0.iq.rate 0.434084 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1139912 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4116 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12815 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 456622 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18431 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 154294 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1068899 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10746647 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 795792 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57645786 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 623000 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9290886 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6078694 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1595130 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 581617 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5318 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12815 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164656 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351489 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516145 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51022070 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8928198 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 390684 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3225661 # number of nop insts executed -system.cpu0.iew.exec_refs 14747797 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8123465 # Number of branches executed -system.cpu0.iew.exec_stores 5819599 # Number of stores executed -system.cpu0.iew.exec_rate 0.445079 # Inst execution rate -system.cpu0.iew.wb_sent 50710143 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50617025 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25247170 # num instructions producing a value -system.cpu0.iew.wb_consumers 34011376 # num instructions consuming a value +system.cpu0.iew.exec_nop 2780674 # number of nop insts executed +system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7066025 # Number of branches executed +system.cpu0.iew.exec_stores 5196118 # Number of stores executed +system.cpu0.iew.exec_rate 0.430889 # Inst execution rate +system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22095606 # num instructions producing a value +system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.441546 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742315 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6411331 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 584428 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 481702 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75046083 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.681415 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.595696 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55785925 74.34% 74.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8029512 10.70% 85.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4410175 5.88% 90.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2388789 3.18% 94.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1317256 1.76% 95.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 560978 0.75% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 472301 0.63% 97.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 435634 0.58% 97.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1645513 2.19% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75046083 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51137491 # Number of instructions committed -system.cpu0.commit.committedOps 51137491 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 44873722 # Number of instructions committed +system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13773046 # Number of memory references committed -system.cpu0.commit.loads 8150974 # Number of loads committed -system.cpu0.commit.membars 198820 # Number of memory barriers committed -system.cpu0.commit.branches 7724848 # Number of branches committed -system.cpu0.commit.fp_insts 258424 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47356368 # Number of committed integer instructions. -system.cpu0.commit.function_calls 655486 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1645513 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12194166 # Number of memory references committed +system.cpu0.commit.loads 7163069 # Number of loads committed +system.cpu0.commit.membars 173899 # Number of memory barriers committed +system.cpu0.commit.branches 6736138 # Number of branches committed +system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions. +system.cpu0.commit.function_calls 557213 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 130752703 # The number of ROB reads -system.cpu0.rob.rob_writes 116166541 # The number of ROB writes -system.cpu0.timesIdled 1097555 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38521021 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3690835342 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48197169 # Number of Instructions Simulated -system.cpu0.committedOps 48197169 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 48197169 # Number of Instructions Simulated -system.cpu0.cpi 2.378480 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.378480 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.420437 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.420437 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67125195 # number of integer regfile reads -system.cpu0.int_regfile_writes 36645952 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127833 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129422 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1709874 # number of misc regfile reads -system.cpu0.misc_regfile_writes 817230 # number of misc regfile writes +system.cpu0.rob.rob_reads 113567039 # The number of ROB reads +system.cpu0.rob.rob_writes 101661188 # The number of ROB writes +system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 42330060 # Number of Instructions Simulated +system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated +system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads +system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes +system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads +system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads +system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1105,49 +1169,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111571177 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2198759 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2198668 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13061 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13061 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10020 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5803 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15823 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343740 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302191 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1753935 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3363647 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 431103 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 300395 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5849080 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56122624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 129969996 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13794368 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 11000190 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 210887178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210876874 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1413952 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4971684979 # Layer occupancy (ticks) +system.toL2Bus.throughput 112875870 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 213368266 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3951712593 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5887546567 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 970657716 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 517795038 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1437659 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54613 # Transaction distribution -system.iobus.trans_dist::WriteResp 54613 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1433257 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 53910 # Transaction distribution +system.iobus.trans_dist::WriteResp 53910 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1158,12 +1222,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40510 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123964 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1174,14 +1238,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73866 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735490 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735490 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11269000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68234 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729874 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729874 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9865000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1201,253 +1265,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378285900 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377768695 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26744000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43112505 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42672507 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 876399 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.760309 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6802362 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 876908 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.757213 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.760309 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995626 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995626 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6802362 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6802362 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6802362 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6802362 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6802362 # number of overall hits -system.cpu0.icache.overall_hits::total 6802362 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 921891 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 921891 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 921891 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 921891 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 921891 # number of overall misses -system.cpu0.icache.overall_misses::total 921891 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13290047828 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13290047828 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13290047828 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13290047828 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13290047828 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13290047828 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7724253 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7724253 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7724253 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7724253 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7724253 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7724253 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119350 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119350 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119350 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119350 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119350 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119350 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14416.072863 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14416.072863 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14416.072863 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14416.072863 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1109 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 232 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.685345 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 554.500000 # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 755849 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.693536 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6013634 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 756358 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.950777 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693536 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6013634 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6013634 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6013634 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6013634 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6013634 # number of overall hits +system.cpu0.icache.overall_hits::total 6013634 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 794785 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 794785 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 794785 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 794785 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 794785 # number of overall misses +system.cpu0.icache.overall_misses::total 794785 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11289773018 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11289773018 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11289773018 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11289773018 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11289773018 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11289773018 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6808419 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6808419 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6808419 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6808419 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6808419 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6808419 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116736 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116736 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116736 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116736 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116736 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116736 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14204.813903 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14204.813903 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14204.813903 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14204.813903 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5327 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 41.944882 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 877019 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 877019 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10904529395 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10904529395 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10904529395 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10904529395 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10904529395 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10904529395 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113541 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113541 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113541 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12433.629596 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38259 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 38259 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 38259 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 38259 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 38259 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 38259 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 756526 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 756526 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 756526 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 756526 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 756526 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 756526 # 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mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111116 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12273.727951 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1278910 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.619274 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10469394 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1279422 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.182909 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.619274 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987538 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987538 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6440836 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6440836 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3667453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3667453 # 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miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322981 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014758 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014758 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248105 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248105 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248105 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25257.990277 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25257.990277 # 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average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2886351 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 51822 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 55.697407 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 1092682 # number of replacements +system.cpu0.dcache.tags.tagsinuse 465.850340 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9201265 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1093194 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.416864 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 465.850340 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.909864 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.909864 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5673895 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5673895 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3199282 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3199282 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148885 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 148885 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172652 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 172652 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8873177 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8873177 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8873177 # number of overall hits +system.cpu0.dcache.overall_hits::total 8873177 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1348613 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1348613 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1646140 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1646140 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16729 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16729 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 773 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 773 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2994753 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2994753 # 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number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 109453177208 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 109453177208 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 109453177208 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7022508 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7022508 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4845422 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4845422 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 165614 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 165614 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 173425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 173425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11867930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11867930 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11867930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11867930 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192042 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.192042 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339731 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.339731 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101012 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101012 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004457 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004457 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252340 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.252340 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252340 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.252340 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27106.705184 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27106.705184 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44283.428026 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44283.428026 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15025.569251 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15025.569251 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6041.464424 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6041.464424 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36548.315406 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36548.315406 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2779952 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1302 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 46345 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.983860 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 162.750000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 752999 # number of writebacks -system.cpu0.dcache.writebacks::total 752999 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 583027 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 583027 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1475561 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1475561 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4528 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4528 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2058588 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2058588 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2058588 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2058588 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002818 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1002818 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274050 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 274050 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16035 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16035 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2807 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2807 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1276868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1276868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1276868 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1276868 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26563866972 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26563866972 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11468217837 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11468217837 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177500254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177500254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15271076 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15271076 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38032084809 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38032084809 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38032084809 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38032084809 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459298500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459298500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2147907499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2147907499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607205999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607205999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124936 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124936 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050590 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050590 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087478 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087478 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014752 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014752 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094979 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094979 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26489.220349 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26489.220349 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41847.173279 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41847.173279 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11069.551232 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11069.551232 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5440.354827 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5440.354827 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 588957 # number of writebacks +system.cpu0.dcache.writebacks::total 588957 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 514989 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 514989 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392541 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1392541 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3960 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3960 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1907530 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1907530 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1907530 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1907530 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 833624 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 833624 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253599 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 253599 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12769 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1087223 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1087223 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1087223 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1087223 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24857542918 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24857542918 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10684541815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10684541815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 151212250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 151212250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3123948 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3123948 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35542084733 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35542084733 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35542084733 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35542084733 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 990981000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 990981000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668402499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668402499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2659383499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2659383499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118707 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118707 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052338 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052338 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.077101 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.077101 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004457 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004457 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091610 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091610 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29818.650756 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29818.650756 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42131.640168 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42131.640168 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11842.137207 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11842.137207 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4041.329884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4041.329884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1455,35 +1519,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2517085 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2083961 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 72869 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1481224 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 844711 # Number of BTB hits +system.cpu1.branchPred.lookups 4005476 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.027904 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 172550 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7415 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1869470 # DTB read hits -system.cpu1.dtb.read_misses 10476 # DTB read misses -system.cpu1.dtb.read_acv 22 # DTB read access violations -system.cpu1.dtb.read_accesses 321268 # DTB read accesses -system.cpu1.dtb.write_hits 1203365 # DTB write hits -system.cpu1.dtb.write_misses 2061 # DTB write misses -system.cpu1.dtb.write_acv 64 # DTB write access violations -system.cpu1.dtb.write_accesses 130567 # DTB write accesses -system.cpu1.dtb.data_hits 3072835 # DTB hits -system.cpu1.dtb.data_misses 12537 # DTB misses -system.cpu1.dtb.data_acv 86 # DTB access violations -system.cpu1.dtb.data_accesses 451835 # DTB accesses -system.cpu1.itb.fetch_hits 424254 # ITB hits -system.cpu1.itb.fetch_misses 6539 # ITB misses -system.cpu1.itb.fetch_acv 190 # ITB acv -system.cpu1.itb.fetch_accesses 430793 # ITB accesses +system.cpu1.dtb.read_hits 2861061 # DTB read hits +system.cpu1.dtb.read_misses 13171 # DTB read misses +system.cpu1.dtb.read_acv 26 # DTB read access violations +system.cpu1.dtb.read_accesses 327320 # DTB read accesses +system.cpu1.dtb.write_hits 1771736 # DTB write hits +system.cpu1.dtb.write_misses 2413 # DTB write misses +system.cpu1.dtb.write_acv 61 # DTB write access violations +system.cpu1.dtb.write_accesses 133954 # DTB write accesses +system.cpu1.dtb.data_hits 4632797 # DTB hits +system.cpu1.dtb.data_misses 15584 # DTB misses +system.cpu1.dtb.data_acv 87 # DTB access violations +system.cpu1.dtb.data_accesses 461274 # DTB accesses +system.cpu1.itb.fetch_hits 484886 # ITB hits +system.cpu1.itb.fetch_misses 6783 # ITB misses +system.cpu1.itb.fetch_acv 213 # ITB acv +system.cpu1.itb.fetch_accesses 491669 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1496,508 +1560,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 15249987 # number of cpu cycles simulated +system.cpu1.numCycles 26365345 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5781097 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11894429 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2517085 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1017261 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2131045 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 385761 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6016414 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62392 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 56888 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1433413 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48410 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14320297 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.830599 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.206016 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12189252 85.12% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 136413 0.95% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 229060 1.60% 87.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 170637 1.19% 88.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 294592 2.06% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 114916 0.80% 91.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 126454 0.88% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 195471 1.36% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 863502 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14320297 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.165055 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.779963 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5724387 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6255039 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1992849 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 108261 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 239760 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 108451 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6971 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11669639 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20547 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 239760 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5925475 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 420572 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5212839 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1896462 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 625187 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10812976 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55937 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12872049 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52940 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 40484 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1926881 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1976180 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1276143 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 178422 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 98267 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9491737 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 473513 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9233560 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29148 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1376057 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 698810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 340347 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14320297 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.319506 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10263877 71.67% 71.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1860247 12.99% 84.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 792265 5.53% 90.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 533948 3.73% 93.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 454852 3.18% 97.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 207190 1.45% 98.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 132078 0.92% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 67607 0.47% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8233 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14320297 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3147 1.66% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 101977 53.82% 55.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84363 44.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5756733 62.35% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16005 0.17% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10795 0.12% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1955574 21.18% 83.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1226577 13.28% 97.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 262587 2.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9233560 # Type of FU issued -system.cpu1.iq.rate 0.605480 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 189487 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020522 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32803401 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11243674 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8968182 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 202651 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 99238 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 96146 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9314130 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 105391 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 90243 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued +system.cpu1.iq.rate 0.569740 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 277299 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1341 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1688 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 122180 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 318 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 14956 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 239760 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 255964 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 40163 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10453412 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 142319 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1976180 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1276143 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 429143 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33341 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1750 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1688 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 32963 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 95419 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 128382 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9148055 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1886987 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 85505 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 488162 # number of nop insts executed -system.cpu1.iew.exec_refs 3098273 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1362461 # Number of branches executed -system.cpu1.iew.exec_stores 1211286 # Number of stores executed -system.cpu1.iew.exec_rate 0.599873 # Inst execution rate -system.cpu1.iew.wb_sent 9092483 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9064328 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4254481 # num instructions producing a value -system.cpu1.iew.wb_consumers 5984515 # num instructions consuming a value +system.cpu1.iew.exec_nop 898529 # number of nop insts executed +system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2338044 # Number of branches executed +system.cpu1.iew.exec_stores 1780212 # Number of stores executed +system.cpu1.iew.exec_rate 0.564317 # Inst execution rate +system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7139948 # num instructions producing a value +system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.594383 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710915 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1421128 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 133166 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 121427 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14080537 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.636506 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577564 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10719102 76.13% 76.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1572221 11.17% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 583613 4.14% 91.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 356342 2.53% 93.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 255998 1.82% 95.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 100117 0.71% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 105425 0.75% 97.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 105001 0.75% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 282718 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14080537 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8962351 # Number of instructions committed -system.cpu1.commit.committedOps 8962351 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 23251022 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 14604164 # Number of instructions committed +system.cpu1.commit.committedOps 14604164 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2852844 # Number of memory references committed -system.cpu1.commit.loads 1698881 # Number of loads committed -system.cpu1.commit.membars 42409 # Number of memory barriers committed -system.cpu1.commit.branches 1280511 # Number of branches committed -system.cpu1.commit.fp_insts 94891 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8306060 # Number of committed integer instructions. -system.cpu1.commit.function_calls 141484 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 282718 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4287363 # Number of memory references committed +system.cpu1.commit.loads 2592870 # Number of loads committed +system.cpu1.commit.membars 62980 # Number of memory barriers committed +system.cpu1.commit.branches 2183593 # Number of branches committed +system.cpu1.commit.fp_insts 107360 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions. +system.cpu1.commit.function_calls 233831 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 466797 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 24092433 # The number of ROB reads -system.cpu1.rob.rob_writes 21005155 # The number of ROB writes -system.cpu1.timesIdled 128904 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 929690 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3789568266 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8530162 # Number of Instructions Simulated -system.cpu1.committedOps 8530162 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8530162 # Number of Instructions Simulated -system.cpu1.cpi 1.787772 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.787772 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.559355 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.559355 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11798212 # number of integer regfile reads -system.cpu1.int_regfile_writes 6449971 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52607 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52314 # number of floating regfile writes -system.cpu1.misc_regfile_reads 504098 # number of misc regfile reads -system.cpu1.misc_regfile_writes 209723 # number of misc regfile writes -system.cpu1.icache.tags.replacements 214995 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.564735 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1210101 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 215507 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.615135 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878702632250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.564735 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919072 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919072 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1210101 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1210101 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1210101 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1210101 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1210101 # number of overall hits -system.cpu1.icache.overall_hits::total 1210101 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 223312 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 223312 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 223312 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 223312 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 223312 # number of overall misses -system.cpu1.icache.overall_misses::total 223312 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3028009139 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3028009139 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3028009139 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3028009139 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3028009139 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3028009139 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1433413 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1433413 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1433413 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1433413 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1433413 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1433413 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155790 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.155790 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155790 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.155790 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155790 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.155790 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13559.545116 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13559.545116 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13559.545116 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13559.545116 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked +system.cpu1.rob.rob_reads 39695803 # The number of ROB reads +system.cpu1.rob.rob_writes 34392702 # The number of ROB writes +system.cpu1.timesIdled 272923 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2721078 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13810279 # Number of Instructions Simulated +system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated +system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 19249115 # number of integer regfile reads +system.cpu1.int_regfile_writes 10558811 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58616 # number of floating regfile reads +system.cpu1.fp_regfile_writes 58623 # number of floating regfile writes +system.cpu1.misc_regfile_reads 636847 # number of misc regfile reads +system.cpu1.misc_regfile_writes 274262 # number of misc regfile writes +system.cpu1.icache.tags.replacements 328629 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.249918 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1927863 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 329141 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.857256 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 49124844500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.249918 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984863 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1927863 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1927863 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1927863 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1927863 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1927863 # number of overall hits +system.cpu1.icache.overall_hits::total 1927863 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses +system.cpu1.icache.overall_misses::total 344335 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4815194513 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4815194513 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4815194513 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4815194513 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4815194513 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4815194513 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2272198 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2272198 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2272198 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2272198 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2272198 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2272198 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.151543 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.151543 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13984.040289 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13984.040289 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1435 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 51 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.531250 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 28.137255 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7746 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7746 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7746 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 215566 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 215566 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 215566 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 215566 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 215566 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 215566 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2508977533 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2508977533 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2508977533 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2508977533 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2508977533 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2508977533 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150387 # 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average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15125 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 15125 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 15125 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 15125 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 15125 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 15125 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329210 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3979739752 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3979739752 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.144886 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.144886 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.144886 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12088.757182 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # 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average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25015.574205 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25015.574205 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 432228 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3904 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7570 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.647541 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57.097490 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 69226 # number of writebacks -system.cpu1.dcache.writebacks::total 69226 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 124077 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 124077 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 172447 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 172447 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 558 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 558 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296524 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296524 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296524 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296524 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 76109 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 76109 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37399 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 37399 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4591 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4591 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2996 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2996 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 113508 # 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number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16100047 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1944598149 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1944598149 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1944598149 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1944598149 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23613000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23613000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 620064002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 620064002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643677002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643677002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043808 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043808 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033534 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033534 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.127224 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.127224 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091261 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091261 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039792 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039792 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11250.643380 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11250.643380 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29100.321720 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29100.321720 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7545.361141 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7545.361141 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5373.847463 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5373.847463 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 251201 # number of writebacks +system.cpu1.dcache.writebacks::total 251201 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211025 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 211025 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306586 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306586 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1580 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1580 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 517611 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 517611 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 517611 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 517611 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267912 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 267912 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 63373 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 63373 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6415 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6415 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 815 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 815 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 331285 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 331285 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 331285 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 331285 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3418270202 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3418270202 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2068179649 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2068179649 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71253503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71253503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4081902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4081902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5486449851 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5486449851 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5486449851 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5486449851 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491833500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491833500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943255503 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 943255503 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1435089003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1435089003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100953 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.100953 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.125222 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.125222 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017315 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017315 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.077152 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.077152 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12758.929059 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12758.929059 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32635.028309 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32635.028309 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11107.327046 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11107.327046 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5008.468712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5008.468712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2006,170 +2070,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6603 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184198 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65080 40.52% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.20% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 193 0.12% 41.92% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93271 58.08% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 160599 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64086 49.21% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.48% 50.79% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 193 0.15% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63894 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130228 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1861779564000 97.85% 97.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63861000 0.00% 97.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 571607000 0.03% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 92660000 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40230450500 2.11% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1902738142500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984726 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 39.83% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866804619500 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904664253500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983248 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685036 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810889 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.664268 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed +system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed +system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed +system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed +system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3514 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 153834 90.90% 93.18% # number of callpals executed -system.cpu0.kern.callpal::rdps 6534 3.86% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rti 4517 2.67% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169239 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7061 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches +system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed +system.cpu0.kern.callpal::rdps 6127 4.09% 96.83% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.83% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.83% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.83% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.84% # number of callpals executed +system.cpu0.kern.callpal::rti 4274 2.85% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149930 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1285 -system.cpu0.kern.mode_good::user 1286 +system.cpu0.kern.mode_good::kernel 1257 +system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181986 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.308015 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1900726417500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2011717000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3515 # number of times the context was actually changed +system.cpu0.kern.swap_context 2970 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2440 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 55424 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17233 36.50% 36.50% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 4.07% 40.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 284 0.60% 41.17% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27775 58.83% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 47214 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16850 47.30% 47.30% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 5.40% 52.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.80% 53.50% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16566 46.50% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35622 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871948155000 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531300500 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 128640500 0.01% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29802235500 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1902410331500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.977775 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.596436 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.754480 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed +system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed +system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed +system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed +system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed +system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed +system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 193 0.40% 0.40% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.40% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1095 2.25% 2.65% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.66% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41959 86.06% 88.73% # number of callpals executed -system.cpu1.kern.callpal::rdps 2221 4.56% 93.29% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.29% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.30% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.30% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.31% # number of callpals executed -system.cpu1.kern.callpal::rti 3048 6.25% 99.56% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.35% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed +system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed +system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed +system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48756 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1363 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2408 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 668 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 209 -system.cpu1.kern.mode_switch_good::kernel 0.490095 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 66403 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 557 +system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_good::idle 69 +system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086794 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.315839 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4405402000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 814709500 0.04% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1897179577000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1096 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1278 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 56fb70faf..cb131fc03 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,125 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860201 # Number of seconds simulated -sim_ticks 1860200687500 # Number of ticks simulated -final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860198 # Number of seconds simulated +sim_ticks 1860197608000 # Number of ticks simulated +final_tick 1860197608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133673 # Simulator instruction rate (inst/s) -host_op_rate 133673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4693486883 # Simulator tick rate (ticks/s) -host_mem_usage 310052 # Number of bytes of host memory used -host_seconds 396.34 # Real time elapsed on the host -sim_insts 52979577 # Number of instructions simulated -sim_ops 52979577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879296 # Number of bytes read from this memory +host_inst_rate 128608 # Simulator instruction rate (inst/s) +host_op_rate 128608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4515644283 # Simulator tick rate (ticks/s) +host_mem_usage 336512 # Number of bytes of host memory used +host_seconds 411.95 # Real time elapsed on the host +sim_insts 52979573 # Number of instructions simulated +sim_ops 52979573 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879808 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28495552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515968 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388739 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15071 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388747 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445243 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117437 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117437 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15318536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040407 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040407 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28495552 # Total number of bytes read from memory -system.physmem.bytesWritten 7515968 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27330 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28321 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7923 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7495 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7495 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6715 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6683 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7403 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7888 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7823 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1860195209000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445243 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117437 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 330882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.num_reads::total 445260 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117448 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117448 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15319147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445260 # Number of read requests accepted +system.physmem.writeReqs 117448 # Number of write requests accepted +system.physmem.readBursts 445260 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117448 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28493888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue +system.physmem.bytesWritten 7515904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28496640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7516672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 177 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28229 # Per bank write bursts +system.physmem.perBankRdBursts::1 27970 # Per bank write bursts +system.physmem.perBankRdBursts::2 28438 # Per bank write bursts +system.physmem.perBankRdBursts::3 28034 # Per bank write bursts +system.physmem.perBankRdBursts::4 27800 # Per bank write bursts +system.physmem.perBankRdBursts::5 27233 # Per bank write bursts +system.physmem.perBankRdBursts::6 27248 # Per bank write bursts +system.physmem.perBankRdBursts::7 27300 # Per bank write bursts +system.physmem.perBankRdBursts::8 27656 # Per bank write bursts +system.physmem.perBankRdBursts::9 27404 # Per bank write bursts +system.physmem.perBankRdBursts::10 27929 # Per bank write bursts +system.physmem.perBankRdBursts::11 27540 # Per bank write bursts +system.physmem.perBankRdBursts::12 27555 # Per bank write bursts +system.physmem.perBankRdBursts::13 28228 # Per bank write bursts +system.physmem.perBankRdBursts::14 28334 # Per bank write bursts +system.physmem.perBankRdBursts::15 28319 # Per bank write bursts +system.physmem.perBankWrBursts::0 7929 # Per bank write bursts +system.physmem.perBankWrBursts::1 7498 # Per bank write bursts +system.physmem.perBankWrBursts::2 7947 # Per bank write bursts +system.physmem.perBankWrBursts::3 7517 # Per bank write bursts +system.physmem.perBankWrBursts::4 7338 # Per bank write bursts +system.physmem.perBankWrBursts::5 6689 # Per bank write bursts +system.physmem.perBankWrBursts::6 6763 # Per bank write bursts +system.physmem.perBankWrBursts::7 6689 # Per bank write bursts +system.physmem.perBankWrBursts::8 7098 # Per bank write bursts +system.physmem.perBankWrBursts::9 6803 # Per bank write bursts +system.physmem.perBankWrBursts::10 7320 # Per bank write bursts +system.physmem.perBankWrBursts::11 6984 # Per bank write bursts +system.physmem.perBankWrBursts::12 7119 # Per bank write bursts +system.physmem.perBankWrBursts::13 7873 # Per bank write bursts +system.physmem.perBankWrBursts::14 8054 # Per bank write bursts +system.physmem.perBankWrBursts::15 7815 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1860192151000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 445260 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 117448 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 332300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -129,242 +131,288 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 955.810131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 232.523406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2430.690638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13031 34.59% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5648 14.99% 49.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3558 9.45% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2240 5.95% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1644 4.36% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1436 3.81% 73.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 989 2.63% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 804 2.13% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 676 1.79% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 516 1.37% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 573 1.52% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 541 1.44% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 276 0.73% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 231 0.61% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 160 0.42% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 263 0.70% 86.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 87 0.23% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 129 0.34% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 153 0.41% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 242 0.64% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 113 0.30% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 462 1.23% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 590 1.57% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 81 0.22% 91.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 28 0.07% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 16 0.04% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 89 0.24% 91.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 26 0.07% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 8 0.02% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 14 0.04% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 43 0.11% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 28 0.07% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 18 0.05% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 7 0.02% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 5 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 6 0.02% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.01% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 3 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.01% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.01% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 5 0.01% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2432 6.46% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 13 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 5 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37668 # Bytes accessed per row activation -system.physmem.totQLat 6113897250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13475242250 # Sum of mem lat for all requests -system.physmem.totBusLat 2225940000 # Total cycles spent in databus access -system.physmem.totBankLat 5135405000 # Total cycles spent in bank access -system.physmem.avgQLat 13733.29 # Average queueing delay per request -system.physmem.avgBankLat 11535.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30268.66 # Average memory access latency -system.physmem.avgRdBW 15.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.32 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 43193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 833.653601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 238.014185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1939.409877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14703 34.04% 34.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6277 14.53% 48.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4438 10.27% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2692 6.23% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1642 3.80% 68.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1371 3.17% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 939 2.17% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 792 1.83% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 658 1.52% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 515 1.19% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 623 1.44% 80.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 600 1.39% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 275 0.64% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 275 0.64% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 263 0.61% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 360 0.83% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 192 0.44% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 168 0.39% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 100 0.23% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 208 0.48% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 111 0.26% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 353 0.82% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 185 0.43% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 668 1.55% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 85 0.20% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 47 0.11% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 186 0.43% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 74 0.17% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 80 0.19% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 97 0.22% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 19 0.04% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 108 0.25% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 28 0.06% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 15 0.03% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.00% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 16 0.04% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 24 0.06% 91.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 101 0.23% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 13 0.03% 91.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 66 0.15% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 39 0.09% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 82 0.19% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 66 0.15% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 13 0.03% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 95 0.22% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 10 0.02% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 3 0.01% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 24 0.06% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 91 0.21% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 11 0.03% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 39 0.09% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 79 0.18% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 94 0.22% 94.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 22 0.05% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 12 0.03% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 4 0.01% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 12 0.03% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 13 0.03% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 67 0.16% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 68 0.16% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 99 0.23% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 11 0.03% 95.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 14 0.03% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 83 0.19% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 39 0.09% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 81 0.19% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 67 0.16% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 13 0.03% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 21 0.05% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 3 0.01% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 24 0.06% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 13 0.03% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 81 0.19% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 309 0.72% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 16 0.04% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.01% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.01% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 18 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 331 0.77% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 5 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 3 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 37 0.09% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 176 0.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43193 # Bytes accessed per row activation +system.physmem.totQLat 8380902250 # Total ticks spent queuing +system.physmem.totMemAccLat 15783312250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2226085000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5176325000 # Total ticks spent accessing banks +system.physmem.avgQLat 18824.31 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11626.52 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 35450.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.67 # Average write queue length over time -system.physmem.readRowHits 430049 # Number of row buffer hits during reads -system.physmem.writeRowHits 94886 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3305955.80 # Average gap between requests -system.membus.throughput 19401806 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295958 # Transaction distribution -system.membus.trans_dist::ReadResp 295878 # Transaction distribution +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.37 # Average write queue length when enqueuing +system.physmem.readRowHits 424661 # Number of row buffer hits during reads +system.physmem.writeRowHits 94799 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.avgGap 3305785.86 # Average gap between requests +system.physmem.pageHitRate 92.32 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19402801 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295960 # Transaction distribution +system.membus.trans_dist::ReadResp 295877 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117437 # Transaction distribution -system.membus.trans_dist::UpgradeReq 178 # Transaction distribution -system.membus.trans_dist::UpgradeResp 178 # Transaction distribution -system.membus.trans_dist::ReadExReq 156851 # Transaction distribution -system.membus.trans_dist::ReadExResp 156851 # Transaction distribution -system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.trans_dist::Writeback 117448 # Transaction distribution +system.membus.trans_dist::UpgradeReq 180 # Transaction distribution +system.membus.trans_dist::UpgradeResp 180 # Transaction distribution +system.membus.trans_dist::ReadExReq 156869 # Transaction distribution +system.membus.trans_dist::ReadExResp 156869 # Transaction distribution +system.membus.trans_dist::BadAddressError 83 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884153 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917424 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042103 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748404 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36055668 # Total data (bytes) +system.membus.tot_pkt_size::total 36057460 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36057460 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29849000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1552225748 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1551414500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3765192546 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3763341794 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376305243 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261102 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710341438000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261102 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078819 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078819 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -373,14 +421,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21345883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21345883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10482445518 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10482445518 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10503791401 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10503791401 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10503791401 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10503791401 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12983817806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12983817806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13004951689 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13004951689 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13004951689 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13004951689 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -397,19 +445,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123386.606936 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123386.606936 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252272.947584 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 252272.947584 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 251738.559641 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 251738.559641 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 274094 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312471.549047 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312471.549047 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311682.485057 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311682.485057 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 402476 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27191 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29170 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.080321 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.797600 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -423,14 +471,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12348383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12348383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8320362536 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8320362536 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8332710919 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8332710919 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8332710919 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8332710919 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10821554320 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10821554320 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10833691203 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10833691203 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10833691203 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10833691203 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -439,14 +487,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71377.936416 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71377.936416 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200239.760685 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 200239.760685 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260434.018098 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260434.018098 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -460,35 +508,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13856452 # Number of BP lookups -system.cpu.branchPred.condPredicted 11625252 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 398822 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9666189 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5826807 # Number of BTB hits +system.cpu.branchPred.lookups 13864479 # Number of BP lookups +system.cpu.branchPred.condPredicted 11634507 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 398117 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9551974 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5822395 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.280292 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 904750 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39047 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 60.954887 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906213 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38605 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9922890 # DTB read hits -system.cpu.dtb.read_misses 41426 # DTB read misses -system.cpu.dtb.read_acv 537 # DTB read access violations -system.cpu.dtb.read_accesses 941977 # DTB read accesses -system.cpu.dtb.write_hits 6601888 # DTB write hits -system.cpu.dtb.write_misses 10414 # DTB write misses -system.cpu.dtb.write_acv 409 # DTB write access violations -system.cpu.dtb.write_accesses 338180 # DTB write accesses -system.cpu.dtb.data_hits 16524778 # DTB hits -system.cpu.dtb.data_misses 51840 # DTB misses -system.cpu.dtb.data_acv 946 # DTB access violations -system.cpu.dtb.data_accesses 1280157 # DTB accesses -system.cpu.itb.fetch_hits 1306702 # ITB hits -system.cpu.itb.fetch_misses 37996 # ITB misses -system.cpu.itb.fetch_acv 1078 # ITB acv -system.cpu.itb.fetch_accesses 1344698 # ITB accesses +system.cpu.dtb.read_hits 9930859 # DTB read hits +system.cpu.dtb.read_misses 42001 # DTB read misses +system.cpu.dtb.read_acv 541 # DTB read access violations +system.cpu.dtb.read_accesses 942214 # DTB read accesses +system.cpu.dtb.write_hits 6592411 # DTB write hits +system.cpu.dtb.write_misses 10345 # DTB write misses +system.cpu.dtb.write_acv 410 # DTB write access violations +system.cpu.dtb.write_accesses 337923 # DTB write accesses +system.cpu.dtb.data_hits 16523270 # DTB hits +system.cpu.dtb.data_misses 52346 # DTB misses +system.cpu.dtb.data_acv 951 # DTB access violations +system.cpu.dtb.data_accesses 1280137 # DTB accesses +system.cpu.itb.fetch_hits 1308071 # ITB hits +system.cpu.itb.fetch_misses 36703 # ITB misses +system.cpu.itb.fetch_acv 1058 # ITB acv +system.cpu.itb.fetch_accesses 1344774 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -501,134 +549,134 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 120724090 # number of cpu cycles simulated +system.cpu.numCycles 121927488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28054756 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70765698 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13856452 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6731557 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13261846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1996538 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38180961 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33921 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253688 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 362223 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8553305 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264520 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81438491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.868947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28039089 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70847333 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13864479 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6728608 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13268188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1998523 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38187764 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33374 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253703 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 358378 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 313 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8556240 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264321 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81433386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.870004 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.213508 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68176645 83.72% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854498 1.05% 84.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1700203 2.09% 86.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 823613 1.01% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2757448 3.39% 91.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 566024 0.70% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 644448 0.79% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011541 1.24% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4904071 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68165198 83.71% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 850053 1.04% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1699284 2.09% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 821371 1.01% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2763942 3.39% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 562061 0.69% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645266 0.79% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1012758 1.24% 93.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4913453 6.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81438491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.114778 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.586177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29237679 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37865551 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12126902 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 959687 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1248671 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585551 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42601 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69445978 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129475 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1248671 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30384491 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14146796 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20012830 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11334710 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4310991 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65667162 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7173 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505660 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79531258 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240064 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12233478 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10440283 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6900737 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318689 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 855517 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58206235 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050936 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56823082 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 100209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6920159 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3549975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389936 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81438491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697742 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359996 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81433386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113711 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.581061 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29221081 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37872240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12130703 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 959021 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1250340 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 583021 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69509272 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129850 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1250340 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30372674 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14147971 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20014852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11335195 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4312352 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65701425 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7084 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 503729 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1544223 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43873094 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79768312 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79589398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166462 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180112 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5692974 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682864 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240315 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12255388 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10448429 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6906827 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1318660 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 851527 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58223534 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050984 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56812947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113805 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6931173 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3605221 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390018 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81433386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56732960 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10881055 13.36% 83.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5157432 6.33% 89.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3394617 4.17% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2629816 3.23% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1458992 1.79% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753848 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332168 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 97603 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56726750 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10882649 13.36% 83.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5163201 6.34% 89.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3388782 4.16% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2628492 3.23% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1462722 1.80% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 751690 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332968 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96132 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81438491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81433386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91824 11.60% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372747 47.08% 58.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 327090 41.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91250 11.56% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372174 47.14% 58.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326051 41.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38740473 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61726 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38733166 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61715 0.11% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued @@ -656,114 +704,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10354642 18.22% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6680643 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949069 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10362094 18.24% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6670366 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56823082 # Type of FU issued -system.cpu.iq.rate 0.470686 # Inst issue rate -system.cpu.iq.fu_busy_cnt 791661 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013932 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195283781 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66854445 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55585028 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692743 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327940 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57245966 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361491 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598566 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56812947 # Type of FU issued +system.cpu.iq.rate 0.465957 # Inst issue rate +system.cpu.iq.fu_busy_cnt 789475 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013896 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195270080 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66882864 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55570085 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692479 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327821 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57233809 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 596971 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1347977 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 522824 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1356016 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3236 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 528856 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17906 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 181081 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17919 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 183461 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1248671 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10233873 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 701956 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63782733 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684936 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10440283 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6900737 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1806230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512408 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17686 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202063 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410564 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612627 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56356224 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9992501 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466857 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1250340 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10233655 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 702274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63801966 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 688802 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10448429 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6906827 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805093 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17454 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 201109 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411560 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 612669 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56346471 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10001011 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466475 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3525562 # number of nop insts executed -system.cpu.iew.exec_refs 16620030 # number of memory reference insts executed -system.cpu.iew.exec_branches 8925380 # Number of branches executed -system.cpu.iew.exec_stores 6627529 # Number of stores executed -system.cpu.iew.exec_rate 0.466818 # Inst execution rate -system.cpu.iew.wb_sent 56027730 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55912968 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27713014 # num instructions producing a value -system.cpu.iew.wb_consumers 37524402 # num instructions consuming a value +system.cpu.iew.exec_nop 3527448 # number of nop insts executed +system.cpu.iew.exec_refs 16619020 # number of memory reference insts executed +system.cpu.iew.exec_branches 8923746 # Number of branches executed +system.cpu.iew.exec_stores 6618009 # Number of stores executed +system.cpu.iew.exec_rate 0.462131 # Inst execution rate +system.cpu.iew.wb_sent 56013491 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55897906 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27708487 # num instructions producing a value +system.cpu.iew.wb_consumers 37528450 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.463147 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738533 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458452 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738333 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7495675 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661000 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 567647 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80189820 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700468 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629642 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7515002 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660966 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566897 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80183046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700527 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629598 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59377156 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8657171 10.80% 84.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4615541 5.76% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2519398 3.14% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1507686 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611065 0.76% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 523948 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 528681 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1849174 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59370328 74.04% 74.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8654728 10.79% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4617014 5.76% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2519187 3.14% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1509953 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 613300 0.76% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 523538 0.65% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 523484 0.65% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1851514 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80189820 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170363 # Number of instructions committed -system.cpu.commit.committedOps 56170363 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80183046 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170357 # Number of instructions committed +system.cpu.commit.committedOps 56170357 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470219 # Number of memory references committed -system.cpu.commit.loads 9092306 # Number of loads committed -system.cpu.commit.membars 226376 # Number of memory barriers committed -system.cpu.commit.branches 8439998 # Number of branches committed +system.cpu.commit.refs 15470384 # Number of memory references committed +system.cpu.commit.loads 9092413 # Number of loads committed +system.cpu.commit.membars 226354 # Number of memory barriers committed +system.cpu.commit.branches 8439829 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019946 # Number of committed integer instructions. -system.cpu.commit.function_calls 740578 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1849174 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52019973 # Number of committed integer instructions. +system.cpu.commit.function_calls 740579 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1851514 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141757103 # The number of ROB reads -system.cpu.rob.rob_writes 128582546 # The number of ROB writes -system.cpu.timesIdled 1193264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 39285599 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599670846 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979577 # Number of Instructions Simulated -system.cpu.committedOps 52979577 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52979577 # Number of Instructions Simulated -system.cpu.cpi 2.278691 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.278691 # CPI: Total CPI of All Threads -system.cpu.ipc 0.438848 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.438848 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73899188 # number of integer regfile reads -system.cpu.int_regfile_writes 40322867 # number of integer regfile writes -system.cpu.fp_regfile_reads 166085 # number of floating regfile reads +system.cpu.rob.rob_reads 141767299 # The number of ROB reads +system.cpu.rob.rob_writes 128622610 # The number of ROB writes +system.cpu.timesIdled 1192878 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40494102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598461292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979573 # Number of Instructions Simulated +system.cpu.committedOps 52979573 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979573 # Number of Instructions Simulated +system.cpu.cpi 2.301406 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301406 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434517 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434517 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73879526 # number of integer regfile reads +system.cpu.int_regfile_writes 40317649 # number of integer regfile writes +system.cpu.fp_regfile_reads 165968 # number of floating regfile reads system.cpu.fp_regfile_writes 167427 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985758 # number of misc regfile reads -system.cpu.misc_regfile_writes 938984 # number of misc regfile writes +system.cpu.misc_regfile_reads 1984782 # number of misc regfile reads +system.cpu.misc_regfile_writes 938976 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -795,7 +843,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454551 # Throughput (bytes/s) +system.iobus.throughput 1454553 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51150 # Transaction distribution @@ -855,225 +903,225 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378268160 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377740446 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43098759 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42670757 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111927083 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2117675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2117578 # Transaction distribution +system.cpu.toL2Bus.throughput 111891693 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2116597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2116497 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301054 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2016984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678218 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5695202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64539584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143593268 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208132852 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208122804 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17856 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2479701498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1516139861 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2192873665 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009263 # number of replacements -system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7487431 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7487431 # number of overall hits -system.cpu.icache.overall_hits::total 7487431 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065872 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065872 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065872 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065872 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065872 # number of overall misses -system.cpu.icache.overall_misses::total 1065872 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14976021459 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14976021459 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14976021459 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14976021459 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14976021459 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14976021459 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8553303 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8553303 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8553303 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8553303 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8553303 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8553303 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124615 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124615 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124615 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124615 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124615 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124615 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14050.487731 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14050.487731 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14050.487731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14050.487731 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8372 # number of cycles access was blocked +system.cpu.icache.tags.replacements 1007825 # number of replacements +system.cpu.icache.tags.tagsinuse 509.660233 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7491263 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1008333 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.429354 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.660233 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7491264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7491264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7491264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7491264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7491264 # number of overall hits +system.cpu.icache.overall_hits::total 7491264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064974 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064974 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064974 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064974 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064974 # number of overall misses +system.cpu.icache.overall_misses::total 1064974 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14872208186 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14872208186 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14872208186 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14872208186 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14872208186 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14872208186 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8556238 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8556238 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8556238 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8556238 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8556238 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8556238 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124468 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124468 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124468 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124468 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124468 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124468 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13964.855655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13964.855655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13964.855655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13964.855655 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5226 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 214 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 45.010753 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.420561 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009992 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009992 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12273344851 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12273344851 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12273344851 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12273344851 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12273344851 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12273344851 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118082 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69058.140169 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15072 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273785 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288857 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14410483773 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15437345031 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 542534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 542534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8118910641 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8118910641 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1026861258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22529394414 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23556255672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1026861258 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1155,161 +1203,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401910 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.428162 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994568 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203713 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186169 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186169 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200552 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316212 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108710 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108710 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 117511571842 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117511571842 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117511571842 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117511571842 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208971 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208971 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215517 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215517 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15164547 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15164547 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15164547 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15164547 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200357 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200357 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316284 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316284 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108776 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247464 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247464 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247464 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247464 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22029.515913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22029.515913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39262.583024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39262.583024 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14178.689347 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14178.689347 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.247354 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247354 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247354 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247354 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22323.812086 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22323.812086 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39693.638678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39693.638678 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14153.204830 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14153.204830 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30961.110464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30961.110464 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2958985 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31327.914673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31327.914673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3032993 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 97398 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98350 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.380347 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.838770 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840831 # number of writebacks -system.cpu.dcache.writebacks::total 840831 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 723109 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 723109 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5191 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5191 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2366614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2366614 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2366614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2366614 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083719 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083719 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300470 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300470 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17516 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17516 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840887 # number of writebacks +system.cpu.dcache.writebacks::total 840887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722519 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722519 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643978 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643978 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5197 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5197 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366497 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366497 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366497 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366497 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084061 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084061 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300460 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300460 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17534 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17534 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384189 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384189 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384189 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384189 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26582228002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26582228002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11613303338 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11613303338 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201814751 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201814751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1384521 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384521 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384521 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384521 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27189046254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27189046254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11757002855 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11757002855 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761751 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38195531340 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38195531340 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38195531340 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38195531340 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424015000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424015000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997805998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997805998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421820998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421820998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083858 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083858 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38946049109 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38946049109 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38946049109 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38946049109 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424137500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424137500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997802998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997802998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421940498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421940498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048873 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048873 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24528.709012 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24528.709012 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38650.458741 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38650.458741 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11521.737326 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11521.737326 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091300 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091300 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25080.734621 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25080.734621 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39130.010168 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39130.010168 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11449.854625 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11449.854625 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1318,28 +1366,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 6437 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182247 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818706968000 97.77% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64176500 0.00% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554827000 0.03% 97.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40873882000 2.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860199853500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818037303500 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64303500 0.00% 97.74% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561270000 0.03% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41533903500 2.23% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860196780500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694268 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815393 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1378,8 +1426,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175130 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed @@ -1388,19 +1436,19 @@ system.cpu.kern.callpal::rti 5105 2.66% 99.64% # nu system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191976 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326158 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29671097000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2774842500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827753906000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29638597000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2732860000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827825315500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index f5971916a..739cb26e4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,143 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842705 # Number of seconds simulated -sim_ticks 1842705252000 # Number of ticks simulated -final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842698 # Number of seconds simulated +sim_ticks 1842698476000 # Number of ticks simulated +final_tick 1842698476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260475 # Simulator instruction rate (inst/s) -host_op_rate 260475 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6607474809 # Simulator tick rate (ticks/s) -host_mem_usage 309028 # Number of bytes of host memory used -host_seconds 278.88 # Real time elapsed on the host -sim_insts 72641883 # Number of instructions simulated -sim_ops 72641883 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20049216 # Number of bytes read from this memory +host_inst_rate 222585 # Simulator instruction rate (inst/s) +host_op_rate 222585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5605413242 # Simulator tick rate (ticks/s) +host_mem_usage 334468 # Number of bytes of host memory used +host_seconds 328.74 # Real time elapsed on the host +sim_insts 73171582 # Number of instructions simulated +sim_ops 73171582 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 489344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20103680 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2290432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 282112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2525760 # Number of bytes read from this memory -system.physmem.bytes_read::total 28435648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 282112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 917888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory -system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313269 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 144384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2235712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 284736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2526400 # Number of bytes read from this memory +system.physmem.bytes_read::total 28436608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 144384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 284736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7460736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7460736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314120 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2302 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35788 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39465 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444307 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10880316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1242973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 153097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1370680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15431468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79952 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 153097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498120 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10880316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1242973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 99238 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 44800 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 99238 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 44800 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 6351232 # Total number of bytes read from memory -system.physmem.bytesWritten 2867200 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6348 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6059 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6008 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5967 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6045 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2861 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2670 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2847 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3000 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2703 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2468 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2705 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2852 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2761 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1841692926500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 99238 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 44800 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 67489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.num_reads::cpu1.inst 2256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34933 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39475 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444322 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116574 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116574 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 265558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 78355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1213282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 154521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1371033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15432046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 78355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 154521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 78355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1213282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 154521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1371033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19480856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98004 # Number of read requests accepted +system.physmem.writeReqs 44399 # Number of write requests accepted +system.physmem.readBursts 98004 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44399 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6271808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 2840768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6272256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2841536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6232 # Per bank write bursts +system.physmem.perBankRdBursts::1 6028 # Per bank write bursts +system.physmem.perBankRdBursts::2 6221 # Per bank write bursts +system.physmem.perBankRdBursts::3 6513 # Per bank write bursts +system.physmem.perBankRdBursts::4 5794 # Per bank write bursts +system.physmem.perBankRdBursts::5 6242 # Per bank write bursts +system.physmem.perBankRdBursts::6 5925 # Per bank write bursts +system.physmem.perBankRdBursts::7 6039 # Per bank write bursts +system.physmem.perBankRdBursts::8 6348 # Per bank write bursts +system.physmem.perBankRdBursts::9 6026 # Per bank write bursts +system.physmem.perBankRdBursts::10 6373 # Per bank write bursts +system.physmem.perBankRdBursts::11 5867 # Per bank write bursts +system.physmem.perBankRdBursts::12 5876 # Per bank write bursts +system.physmem.perBankRdBursts::13 6234 # Per bank write bursts +system.physmem.perBankRdBursts::14 6235 # Per bank write bursts +system.physmem.perBankRdBursts::15 6044 # Per bank write bursts +system.physmem.perBankWrBursts::0 2859 # Per bank write bursts +system.physmem.perBankWrBursts::1 2656 # Per bank write bursts +system.physmem.perBankWrBursts::2 2839 # Per bank write bursts +system.physmem.perBankWrBursts::3 3122 # Per bank write bursts +system.physmem.perBankWrBursts::4 2688 # Per bank write bursts +system.physmem.perBankWrBursts::5 2969 # Per bank write bursts +system.physmem.perBankWrBursts::6 2850 # Per bank write bursts +system.physmem.perBankWrBursts::7 2699 # Per bank write bursts +system.physmem.perBankWrBursts::8 3075 # Per bank write bursts +system.physmem.perBankWrBursts::9 2558 # Per bank write bursts +system.physmem.perBankWrBursts::10 2888 # Per bank write bursts +system.physmem.perBankWrBursts::11 2432 # Per bank write bursts +system.physmem.perBankWrBursts::12 2458 # Per bank write bursts +system.physmem.perBankWrBursts::13 2707 # Per bank write bursts +system.physmem.perBankWrBursts::14 2844 # Per bank write bursts +system.physmem.perBankWrBursts::15 2743 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 1841686150500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 98004 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 44399 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -149,362 +151,413 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 15760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 584.832487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.909397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1926.760563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 6603 41.90% 41.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2572 16.32% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1454 9.23% 67.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 899 5.70% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 642 4.07% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 535 3.39% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 370 2.35% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 312 1.98% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 250 1.59% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 195 1.24% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 235 1.49% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 190 1.21% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 101 0.64% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 71 0.45% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 63 0.40% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 80 0.51% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 51 0.32% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 28 0.18% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 74 0.47% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 51 0.32% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 34 0.22% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 173 1.10% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 86 0.55% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 27 0.17% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 12 0.08% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 22 0.14% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 10 0.06% 96.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 4 0.03% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 7 0.04% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 1 0.01% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 3 0.02% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 2 0.01% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 1 0.01% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 2 0.01% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.01% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.01% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.01% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.01% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 383 2.43% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 6 0.04% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 2 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 15760 # Bytes accessed per row activation -system.physmem.totQLat 1910826000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3572864750 # Sum of mem lat for all requests -system.physmem.totBusLat 496135000 # Total cycles spent in databus access -system.physmem.totBankLat 1165903750 # Total cycles spent in bank access -system.physmem.avgQLat 19257.12 # Average queueing delay per request -system.physmem.avgBankLat 11749.86 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 36006.98 # Average memory access latency -system.physmem.avgRdBW 3.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 17930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 508.141439 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.008973 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1572.275953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 7528 41.99% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2973 16.58% 58.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1838 10.25% 68.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 1006 5.61% 74.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 670 3.74% 78.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 572 3.19% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 359 2.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 327 1.82% 85.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 240 1.34% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 222 1.24% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 225 1.25% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 213 1.19% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 93 0.52% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 79 0.44% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 78 0.44% 91.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 102 0.57% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 45 0.25% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 56 0.31% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 39 0.22% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 53 0.30% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 119 0.66% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 70 0.39% 94.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 89 0.50% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 16 0.09% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 5 0.03% 95.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 36 0.20% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 6 0.03% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 15 0.08% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 5 0.03% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 11 0.06% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 11 0.06% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 2 0.01% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 1 0.01% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 2 0.01% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.01% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 4 0.02% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 10 0.06% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 3 0.02% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 13 0.07% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 7 0.04% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 13 0.07% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 2 0.01% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 23 0.13% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.01% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 14 0.08% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.01% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 76 0.42% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.01% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 4 0.02% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.01% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 9 0.05% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 5 0.03% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.01% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 8 0.04% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 8 0.04% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 3 0.02% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 4 0.02% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 5 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 20 0.11% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 2 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 4 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.08% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 76 0.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 17930 # Bytes accessed per row activation +system.physmem.totQLat 2684942500 # Total ticks spent queuing +system.physmem.totMemAccLat 4336678750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 489985000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1161751250 # Total ticks spent accessing banks +system.physmem.avgQLat 27398.21 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11854.97 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 44253.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.17 # Average write queue length over time -system.physmem.readRowHits 92920 # Number of row buffer hits during reads -system.physmem.writeRowHits 35346 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.90 # Row buffer hit rate for writes -system.physmem.avgGap 12786160.09 # Average gap between requests -system.membus.throughput 19523578 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 45592 # Transaction distribution -system.membus.trans_dist::ReadResp 45560 # Transaction distribution -system.membus.trans_dist::WriteReq 3756 # Transaction distribution -system.membus.trans_dist::WriteResp 3756 # Transaction distribution -system.membus.trans_dist::Writeback 44800 # Transaction distribution -system.membus.trans_dist::UpgradeReq 46 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47 # Transaction distribution -system.membus.trans_dist::ReadExReq 56741 # Transaction distribution -system.membus.trans_dist::ReadExResp 56741 # Transaction distribution -system.membus.trans_dist::BadAddressError 32 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 191660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35966088 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12465000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.18 # Average write queue length when enqueuing +system.physmem.readRowHits 89612 # Number of row buffer hits during reads +system.physmem.writeRowHits 34842 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.47 # Row buffer hit rate for writes +system.physmem.avgGap 12932916.80 # Average gap between requests +system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19524796 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44746 # Transaction distribution +system.membus.trans_dist::ReadResp 44539 # Transaction distribution +system.membus.trans_dist::WriteReq 3750 # Transaction distribution +system.membus.trans_dist::WriteResp 3750 # Transaction distribution +system.membus.trans_dist::Writeback 44399 # Transaction distribution +system.membus.trans_dist::UpgradeReq 43 # Transaction distribution +system.membus.trans_dist::UpgradeResp 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 56527 # Transaction distribution +system.membus.trans_dist::ReadExResp 56527 # Transaction distribution +system.membus.trans_dist::BadAddressError 207 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 203660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 254372 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15690 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6953984 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6969674 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9129482 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35968328 # Total data (bytes) +system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12460500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 516080000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 511769750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 39000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 256500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 771793954 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 762797456 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 156435750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 153003500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 337384 # number of replacements -system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use -system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks. +system.l2c.tags.replacements 337399 # number of replacements +system.l2c.tags.tagsinuse 65421.710089 # Cycle average of tags in use +system.l2c.tags.total_refs 2471820 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402562 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.140222 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009052 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032116 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.032390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998282 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 518817 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124693 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 293247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239325 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1753041 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits -system.l2c.Writeback_hits::total 835257 # number of Writeback hits +system.l2c.tags.occ_blocks::writebacks 54901.425298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2456.924718 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2698.289857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 528.309889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 619.621947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2142.597203 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2074.541175 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837729 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041173 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032693 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.031655 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998256 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 520374 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 492975 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124091 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 84248 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 292559 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239147 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1753394 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835552 # number of Writeback hits +system.l2c.Writeback_hits::total 835552 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 1 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -623,14 +668,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254914 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694870261000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254914 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078432 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078432 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -639,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9629212 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9629212 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4353407559 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4353407559 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4363036771 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4363036771 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4363036771 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4363036771 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9304463 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9304463 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5314395237 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5314395237 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5323699700 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5323699700 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5323699700 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5323699700 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -663,56 +708,56 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55660.184971 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 55660.184971 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104770.108755 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104770.108755 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104566.489419 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104566.489419 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 114649 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53783.023121 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53783.023121 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127897.459497 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127897.459497 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127590.166567 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127590.166567 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 168405 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11461 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12345 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.003403 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.641555 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17350 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 17350 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5987712 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5987712 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3454277559 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3454277559 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3460265271 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3460265271 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3460265271 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3460265271 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.415818 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.415818 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85538.742857 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 85538.742857 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199900.321701 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199900.321701 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5715463 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5715463 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435167237 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4435167237 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4440882700 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4440882700 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4440882700 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4440882700 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82832.797101 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82832.797101 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262498.060902 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 262498.060902 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -730,22 +775,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4909978 # DTB read hits -system.cpu0.dtb.read_misses 6100 # DTB read misses +system.cpu0.dtb.read_hits 4920992 # DTB read hits +system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428319 # DTB read accesses -system.cpu0.dtb.write_hits 3504299 # DTB write hits -system.cpu0.dtb.write_misses 671 # DTB write misses +system.cpu0.dtb.read_accesses 428234 # DTB read accesses +system.cpu0.dtb.write_hits 3511178 # DTB write hits +system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 163761 # DTB write accesses -system.cpu0.dtb.data_hits 8414277 # DTB hits -system.cpu0.dtb.data_misses 6771 # DTB misses +system.cpu0.dtb.write_accesses 163777 # DTB write accesses +system.cpu0.dtb.data_hits 8432170 # DTB hits +system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592080 # DTB accesses -system.cpu0.itb.fetch_hits 2758234 # ITB hits +system.cpu0.dtb.data_accesses 592011 # DTB accesses +system.cpu0.itb.fetch_hits 2763046 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2761268 # ITB accesses +system.cpu0.itb.fetch_accesses 2766080 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -758,51 +803,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928316891 # number of cpu cycles simulated +system.cpu0.numCycles 928344318 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33736461 # Number of instructions committed -system.cpu0.committedOps 33736461 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31599588 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169686 # Number of float alu accesses -system.cpu0.num_func_calls 810809 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4665593 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31599588 # number of integer instructions -system.cpu0.num_fp_insts 169686 # number of float instructions -system.cpu0.num_int_register_reads 44374544 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23060255 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87629 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89168 # number of times the floating registers were written -system.cpu0.num_mem_refs 8444409 # number of memory refs -system.cpu0.num_load_insts 4931349 # Number of load instructions -system.cpu0.num_store_insts 3513060 # Number of store instructions -system.cpu0.num_idle_cycles 903633014.989213 # Number of idle cycles -system.cpu0.num_busy_cycles 24683876.010787 # Number of busy cycles -system.cpu0.not_idle_fraction 0.026590 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.973410 # Percentage of idle cycles +system.cpu0.committedInsts 33880492 # Number of instructions committed +system.cpu0.committedOps 33880492 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31739536 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169894 # Number of float alu accesses +system.cpu0.num_func_calls 813170 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4699422 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31739536 # number of integer instructions +system.cpu0.num_fp_insts 169894 # number of float instructions +system.cpu0.num_int_register_reads 44596322 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23159667 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87728 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89270 # number of times the floating registers were written +system.cpu0.num_mem_refs 8462332 # number of memory refs +system.cpu0.num_load_insts 4942381 # Number of load instructions +system.cpu0.num_store_insts 3519951 # Number of store instructions +system.cpu0.num_idle_cycles 904625586.132235 # Number of idle cycles +system.cpu0.num_busy_cycles 23718731.867765 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6416 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211386 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182586 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819515680500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39349500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365678500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22783774000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842704482500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819501633500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38918500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365019000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22792135500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842697706500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694800 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815835 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694791 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815828 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -841,7 +886,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175327 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -850,20 +895,20 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192242 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29786026000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2614250500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810304201500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391309 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29773270000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2593332500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810331099500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -896,444 +941,427 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110422039 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 786602 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 786555 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3756 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3756 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371447 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 15 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 849315 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370344 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2219659 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27177600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55325386 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82502986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203464200 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks) +system.toL2Bus.throughput 110448008 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 784800 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 784578 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3750 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3750 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371852 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150627 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133731 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 207 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846719 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1369630 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2216349 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27094720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55304714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82399434 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203511688 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10688 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2136322000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1913139810 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1907046997 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2237602233 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2233138904 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469136 # Throughput (bytes/s) +system.iobus.throughput 1469141 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 2975 # Transaction distribution system.iobus.trans_dist::ReadResp 2975 # Transaction distribution -system.iobus.trans_dist::WriteReq 21036 # Transaction distribution -system.iobus.trans_dist::WriteResp 21036 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 20646 # Transaction distribution +system.iobus.trans_dist::WriteResp 20646 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47242 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4186 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15690 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098482 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6200000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6239000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1827000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 157303021 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 153606200 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9566000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9562000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17990250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17411500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 950451 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43221003 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 246.999230 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.674980 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.517805 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482420 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194678 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321324 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998422 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 33216972 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7763860 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2240171 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43221003 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33216972 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7763860 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2240171 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43221003 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33216972 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7763860 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2240171 # number of overall hits -system.cpu0.icache.overall_hits::total 43221003 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 526470 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 126995 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 313704 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 967169 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 526470 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 126995 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 313704 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 967169 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 526470 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 126995 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 313704 # number of overall misses -system.cpu0.icache.overall_misses::total 967169 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1823123501 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4463889198 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6287012699 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1823123501 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4463889198 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6287012699 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1823123501 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4463889198 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6287012699 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33743442 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7890855 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2553875 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44188172 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33743442 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7890855 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2553875 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44188172 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33743442 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7890855 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2553875 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44188172 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015602 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016094 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122835 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021888 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015602 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016094 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122835 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021888 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015602 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016094 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122835 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021888 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14355.868349 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14229.621548 # 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number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1394 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1394 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 784711 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 784711 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 784711 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 784711 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98930 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252708 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 351638 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 45023 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88528 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133551 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4084281738 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24249500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66698251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90947751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3576805741 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6804065155 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10380870896 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3576805741 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6804065155 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10380870896 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 294283500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312003000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 606286500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 361937500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429433000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791370500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 656221000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 741436000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397657000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083444 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086144 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051014 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046894 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098681 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037292 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032215 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032215 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20778.830992 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16781.975276 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17906.452539 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33786.197965 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28952.712667 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30582.187614 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11200.692841 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12344.669813 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12017.408959 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16999.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5430 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7595 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 143357 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 341252 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484609 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 143357 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341252 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484609 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2056105000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4263367239 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6319472239 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1563762241 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2632845749 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4196607990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24206750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90370250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3619867241 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6896212988 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10516080229 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3619867241 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6896212988 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10516080229 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296519000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310561500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607080500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364164500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426924000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791088500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660683500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737485500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1398169000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083613 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086086 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039373 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047212 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021711 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100862 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099697 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037414 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032165 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032165 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20769.786353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16910.272766 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.451318 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35250.039245 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29537.732081 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31435.972269 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11180.946882 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12184.806630 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.650428 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1348,22 +1376,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1205047 # DTB read hits -system.cpu1.dtb.read_misses 1367 # DTB read misses +system.cpu1.dtb.read_hits 1203387 # DTB read hits +system.cpu1.dtb.read_misses 1366 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142944 # DTB read accesses -system.cpu1.dtb.write_hits 904403 # DTB write hits -system.cpu1.dtb.write_misses 185 # DTB write misses -system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58533 # DTB write accesses -system.cpu1.dtb.data_hits 2109450 # DTB hits -system.cpu1.dtb.data_misses 1552 # DTB misses -system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 201477 # DTB accesses -system.cpu1.itb.fetch_hits 861634 # ITB hits -system.cpu1.itb.fetch_misses 693 # ITB misses +system.cpu1.dtb.read_accesses 142939 # DTB read accesses +system.cpu1.dtb.write_hits 898859 # DTB write hits +system.cpu1.dtb.write_misses 183 # DTB write misses +system.cpu1.dtb.write_acv 22 # DTB write access violations +system.cpu1.dtb.write_accesses 58529 # DTB write accesses +system.cpu1.dtb.data_hits 2102246 # DTB hits +system.cpu1.dtb.data_misses 1549 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 201468 # DTB accesses +system.cpu1.itb.fetch_hits 859133 # ITB hits +system.cpu1.itb.fetch_misses 692 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 862327 # ITB accesses +system.cpu1.itb.fetch_accesses 859825 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1376,28 +1404,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953630418 # number of cpu cycles simulated +system.cpu1.numCycles 953620014 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7889245 # Number of instructions committed -system.cpu1.committedOps 7889245 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7344952 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44937 # Number of float alu accesses -system.cpu1.num_func_calls 213049 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 993802 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7344952 # number of integer instructions -system.cpu1.num_fp_insts 44937 # number of float instructions -system.cpu1.num_int_register_reads 10269748 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5343251 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24271 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24577 # number of times the floating registers were written -system.cpu1.num_mem_refs 2116682 # number of memory refs -system.cpu1.num_load_insts 1209934 # Number of load instructions -system.cpu1.num_store_insts 906748 # Number of store instructions -system.cpu1.num_idle_cycles 923700977.463911 # Number of idle cycles -system.cpu1.num_busy_cycles 29929440.536089 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031385 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968615 # Percentage of idle cycles +system.cpu1.committedInsts 7953643 # Number of instructions committed +system.cpu1.committedOps 7953643 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7410219 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45003 # Number of float alu accesses +system.cpu1.num_func_calls 212713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1020267 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7410219 # number of integer instructions +system.cpu1.num_fp_insts 45003 # number of float instructions +system.cpu1.num_int_register_reads 10384111 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5386902 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24304 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24611 # number of times the floating registers were written +system.cpu1.num_mem_refs 2109479 # number of memory refs +system.cpu1.num_load_insts 1208276 # Number of load instructions +system.cpu1.num_store_insts 901203 # Number of store instructions +system.cpu1.num_idle_cycles 922135498.680812 # Number of idle cycles +system.cpu1.num_busy_cycles 31484515.319188 # Number of busy cycles +system.cpu1.not_idle_fraction 0.033016 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.966984 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1415,35 +1443,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9022316 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8342315 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 122648 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7529449 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6410701 # Number of BTB hits +system.cpu2.branchPred.lookups 9128355 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8449925 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 124319 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7461780 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6520544 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.141702 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 283187 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 12478 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 87.385905 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 281902 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13317 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3192037 # DTB read hits -system.cpu2.dtb.read_misses 11608 # DTB read misses +system.cpu2.dtb.read_hits 3185589 # DTB read hits +system.cpu2.dtb.read_misses 11798 # DTB read misses system.cpu2.dtb.read_acv 121 # DTB read access violations -system.cpu2.dtb.read_accesses 216573 # DTB read accesses -system.cpu2.dtb.write_hits 2009173 # DTB write hits -system.cpu2.dtb.write_misses 2522 # DTB write misses +system.cpu2.dtb.read_accesses 217406 # DTB read accesses +system.cpu2.dtb.write_hits 2009886 # DTB write hits +system.cpu2.dtb.write_misses 2608 # DTB write misses system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 81978 # DTB write accesses -system.cpu2.dtb.data_hits 5201210 # DTB hits -system.cpu2.dtb.data_misses 14130 # DTB misses +system.cpu2.dtb.write_accesses 82301 # DTB write accesses +system.cpu2.dtb.data_hits 5195475 # DTB hits +system.cpu2.dtb.data_misses 14406 # DTB misses system.cpu2.dtb.data_acv 227 # DTB access violations -system.cpu2.dtb.data_accesses 298551 # DTB accesses -system.cpu2.itb.fetch_hits 369667 # ITB hits -system.cpu2.itb.fetch_misses 5681 # ITB misses -system.cpu2.itb.fetch_acv 262 # ITB acv -system.cpu2.itb.fetch_accesses 375348 # ITB accesses +system.cpu2.dtb.data_accesses 299707 # DTB accesses +system.cpu2.itb.fetch_hits 369992 # ITB hits +system.cpu2.itb.fetch_misses 5727 # ITB misses +system.cpu2.itb.fetch_acv 273 # ITB acv +system.cpu2.itb.fetch_accesses 375719 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1456,270 +1484,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31245078 # number of cpu cycles simulated +system.cpu2.numCycles 31308710 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8348883 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36663716 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9022316 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6693888 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8736568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 602984 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9694630 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 11222 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1957 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63711 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 86195 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2553880 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 85053 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27335965 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.341226 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.294449 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8320877 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36988805 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9128355 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6802446 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8846835 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 603748 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9639992 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63718 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87241 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2552980 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 86276 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27364450 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.351710 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.294118 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18599397 68.04% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269863 0.99% 69.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 429102 1.57% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4885317 17.87% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 756803 2.77% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 166340 0.61% 91.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 191609 0.70% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 429140 1.57% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1608394 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18517615 67.67% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 268760 0.98% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 429758 1.57% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4997201 18.26% 88.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 759565 2.78% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 164512 0.60% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 190396 0.70% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 427414 1.56% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1609229 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27335965 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288760 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.173424 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8495766 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9778515 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8128034 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 307242 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 380496 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165135 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12538 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36269918 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39153 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 380496 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8853799 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2797423 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5789351 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7998658 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1270334 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35131949 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2438 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 231189 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 444117 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23541427 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 43931372 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43874902 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52705 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21760313 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1781114 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 501831 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59191 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3719256 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3350609 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2097879 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 369762 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 260934 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32641753 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 622044 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32196803 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34835 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2138258 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1073109 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 438824 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27335965 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.177818 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.573987 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27364450 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.291560 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.181422 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8471005 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9721532 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8236973 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308822 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 380199 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165870 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12770 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36596033 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40157 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 380199 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8829996 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2781091 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5750095 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8109315 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1267845 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35455371 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2432 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 230458 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 443882 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23756988 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44373855 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44317462 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52634 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21971271 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1785717 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 500561 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59005 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3706520 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3341982 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2099682 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 368903 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 258103 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32963824 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 619272 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32519364 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 32677 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2138512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1074729 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 437003 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27364450 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.188380 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.575952 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15167963 55.49% 55.49% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3067850 11.22% 66.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1557003 5.70% 72.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5712284 20.90% 93.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 903378 3.30% 96.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480833 1.76% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 285081 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142652 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18921 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15094542 55.16% 55.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3058510 11.18% 66.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1555503 5.68% 72.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5825063 21.29% 93.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 904805 3.31% 96.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480018 1.75% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 285628 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141467 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18914 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27335965 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27364450 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33684 13.60% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113022 45.64% 59.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100957 40.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33388 13.55% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112327 45.58% 59.13% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100703 40.87% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26526068 82.39% 82.39% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20082 0.06% 82.46% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8432 0.03% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3318552 10.31% 92.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2030927 6.31% 99.10% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289082 0.90% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26855600 82.58% 82.59% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20032 0.06% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8424 0.03% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3311528 10.18% 92.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2031960 6.25% 99.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288160 0.89% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32196803 # Type of FU issued -system.cpu2.iq.rate 1.030460 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 247663 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007692 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 91777621 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35291242 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 31803164 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234448 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114643 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110912 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32319915 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122111 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186470 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32519364 # Type of FU issued +system.cpu2.iq.rate 1.038668 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 246418 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007578 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92448223 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35610975 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32122316 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234050 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114559 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110669 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32641435 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121907 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186593 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 409308 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1087 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 154806 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 407978 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1104 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4025 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 156833 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4179 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 28515 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4157 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 26970 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 380496 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2018433 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 205280 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34533473 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 223572 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3350609 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2097879 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 552418 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 143005 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2030 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3940 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62474 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127218 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 189692 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32041792 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3211958 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 155011 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 380199 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2010765 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204147 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34852291 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 222063 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3341982 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2099682 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 549953 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 141753 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1988 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4025 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63582 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127875 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 191457 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32361861 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3205658 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 157503 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1269676 # number of nop insts executed -system.cpu2.iew.exec_refs 5228104 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7451179 # Number of branches executed -system.cpu2.iew.exec_stores 2016146 # Number of stores executed -system.cpu2.iew.exec_rate 1.025499 # Inst execution rate -system.cpu2.iew.wb_sent 31946323 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31914076 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18560539 # num instructions producing a value -system.cpu2.iew.wb_consumers 21756623 # num instructions consuming a value +system.cpu2.iew.exec_nop 1269195 # number of nop insts executed +system.cpu2.iew.exec_refs 5222587 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7560841 # Number of branches executed +system.cpu2.iew.exec_stores 2016929 # Number of stores executed +system.cpu2.iew.exec_rate 1.033638 # Inst execution rate +system.cpu2.iew.wb_sent 32266608 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32232985 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18776213 # num instructions producing a value +system.cpu2.iew.wb_consumers 21965918 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.021411 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.853098 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.029521 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.854788 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2307107 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 183220 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 175579 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26955469 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.193861 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846623 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2305690 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182269 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 176747 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26984251 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.204438 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.848007 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16175286 60.01% 60.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2330504 8.65% 68.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1226068 4.55% 73.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5456953 20.24% 93.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503178 1.87% 95.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186113 0.69% 96.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 177622 0.66% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179384 0.67% 97.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 720361 2.67% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16102351 59.67% 59.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2321930 8.60% 68.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1225737 4.54% 72.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5569081 20.64% 93.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 502606 1.86% 95.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185666 0.69% 96.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 176683 0.65% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180209 0.67% 97.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 719988 2.67% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26955469 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32181084 # Number of instructions committed -system.cpu2.commit.committedOps 32181084 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26984251 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32500866 # Number of instructions committed +system.cpu2.commit.committedOps 32500866 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4884374 # Number of memory references committed -system.cpu2.commit.loads 2941301 # Number of loads committed -system.cpu2.commit.membars 64148 # Number of memory barriers committed -system.cpu2.commit.branches 7305681 # Number of branches committed -system.cpu2.commit.fp_insts 109768 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30735120 # Number of committed integer instructions. -system.cpu2.commit.function_calls 229363 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 720361 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4876853 # Number of memory references committed +system.cpu2.commit.loads 2934004 # Number of loads committed +system.cpu2.commit.membars 63840 # Number of memory barriers committed +system.cpu2.commit.branches 7415854 # Number of branches committed +system.cpu2.commit.fp_insts 109494 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31057555 # Number of committed integer instructions. +system.cpu2.commit.function_calls 228510 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 719988 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60649307 # The number of ROB reads -system.cpu2.rob.rob_writes 69356385 # The number of ROB writes -system.cpu2.timesIdled 245741 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3909113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746532644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31016177 # Number of Instructions Simulated -system.cpu2.committedOps 31016177 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31016177 # Number of Instructions Simulated -system.cpu2.cpi 1.007380 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.007380 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.992674 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.992674 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42141472 # number of integer regfile reads -system.cpu2.int_regfile_writes 22438304 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67749 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68082 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5235386 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258296 # number of misc regfile writes +system.cpu2.rob.rob_reads 60996891 # The number of ROB reads +system.cpu2.rob.rob_writes 69992925 # The number of ROB writes +system.cpu2.timesIdled 244953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3944260 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746464525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31337447 # Number of Instructions Simulated +system.cpu2.committedOps 31337447 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31337447 # Number of Instructions Simulated +system.cpu2.cpi 0.999083 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.999083 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.000918 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.000918 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42570866 # number of integer regfile reads +system.cpu2.int_regfile_writes 22648106 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67644 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67951 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5345306 # number of misc regfile reads +system.cpu2.misc_regfile_writes 257045 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |