diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
4 files changed, 5428 insertions, 5392 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 96524a9ce..3b6b51422 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.887168 # Number of seconds simulated -sim_ticks 1887168480000 # Number of ticks simulated -final_tick 1887168480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906037 # Number of seconds simulated +sim_ticks 1906037467000 # Number of ticks simulated +final_tick 1906037467000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181674 # Simulator instruction rate (inst/s) -host_op_rate 181674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6108559174 # Simulator tick rate (ticks/s) -host_mem_usage 367844 # Number of bytes of host memory used -host_seconds 308.94 # Real time elapsed on the host -sim_insts 56125948 # Number of instructions simulated -sim_ops 56125948 # Number of ops (including micro ops) simulated +host_inst_rate 252781 # Simulator instruction rate (inst/s) +host_op_rate 252781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8583432112 # Simulator tick rate (ticks/s) +host_mem_usage 376892 # Number of bytes of host memory used +host_seconds 222.06 # Real time elapsed on the host +sim_insts 56132533 # Number of instructions simulated +sim_ops 56132533 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1049920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24850048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1050496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1049920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1049920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7553472 # Number of bytes written to this memory -system.physmem.bytes_written::total 7553472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16405 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388282 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25909440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1050496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1050496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7561088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7561088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118023 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118023 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 556347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13167901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13724757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 556347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 556347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4002542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4002542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4002542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 556347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13167901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17727299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404702 # Number of read requests accepted -system.physmem.writeReqs 118023 # Number of write requests accepted -system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118023 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25893824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7551936 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7553472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 404835 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118142 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118142 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 551141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13041708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13593353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 551141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 551141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3966915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3966915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3966915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 551141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13041708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17560268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404835 # Number of read requests accepted +system.physmem.writeReqs 118142 # Number of write requests accepted +system.physmem.readBursts 404835 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118142 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25902720 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 7559680 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25909440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7561088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41707 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25482 # Per bank write bursts -system.physmem.perBankRdBursts::1 25721 # Per bank write bursts -system.physmem.perBankRdBursts::2 25818 # Per bank write bursts -system.physmem.perBankRdBursts::3 25768 # Per bank write bursts -system.physmem.perBankRdBursts::4 25084 # Per bank write bursts -system.physmem.perBankRdBursts::5 25019 # Per bank write bursts -system.physmem.perBankRdBursts::6 24651 # Per bank write bursts -system.physmem.perBankRdBursts::7 24525 # Per bank write bursts -system.physmem.perBankRdBursts::8 25293 # Per bank write bursts -system.physmem.perBankRdBursts::9 25189 # Per bank write bursts -system.physmem.perBankRdBursts::10 25397 # Per bank write bursts -system.physmem.perBankRdBursts::11 24988 # Per bank write bursts -system.physmem.perBankRdBursts::12 24521 # Per bank write bursts -system.physmem.perBankRdBursts::13 25565 # Per bank write bursts -system.physmem.perBankRdBursts::14 25830 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 41709 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25494 # Per bank write bursts +system.physmem.perBankRdBursts::1 25705 # Per bank write bursts +system.physmem.perBankRdBursts::2 25829 # Per bank write bursts +system.physmem.perBankRdBursts::3 25773 # Per bank write bursts +system.physmem.perBankRdBursts::4 25090 # Per bank write bursts +system.physmem.perBankRdBursts::5 25012 # Per bank write bursts +system.physmem.perBankRdBursts::6 24715 # Per bank write bursts +system.physmem.perBankRdBursts::7 24579 # Per bank write bursts +system.physmem.perBankRdBursts::8 25194 # Per bank write bursts +system.physmem.perBankRdBursts::9 25292 # Per bank write bursts +system.physmem.perBankRdBursts::10 25390 # Per bank write bursts +system.physmem.perBankRdBursts::11 24989 # Per bank write bursts +system.physmem.perBankRdBursts::12 24533 # Per bank write bursts +system.physmem.perBankRdBursts::13 25560 # Per bank write bursts +system.physmem.perBankRdBursts::14 25835 # Per bank write bursts system.physmem.perBankRdBursts::15 25740 # Per bank write bursts -system.physmem.perBankWrBursts::0 7815 # Per bank write bursts -system.physmem.perBankWrBursts::1 7682 # Per bank write bursts -system.physmem.perBankWrBursts::2 8062 # Per bank write bursts -system.physmem.perBankWrBursts::3 7737 # Per bank write bursts -system.physmem.perBankWrBursts::4 7196 # Per bank write bursts -system.physmem.perBankWrBursts::5 7012 # Per bank write bursts -system.physmem.perBankWrBursts::6 6647 # Per bank write bursts -system.physmem.perBankWrBursts::7 6398 # Per bank write bursts -system.physmem.perBankWrBursts::8 7404 # Per bank write bursts -system.physmem.perBankWrBursts::9 6806 # Per bank write bursts -system.physmem.perBankWrBursts::10 7277 # Per bank write bursts -system.physmem.perBankWrBursts::11 6969 # Per bank write bursts -system.physmem.perBankWrBursts::12 7052 # Per bank write bursts -system.physmem.perBankWrBursts::13 8011 # Per bank write bursts -system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::0 7824 # Per bank write bursts +system.physmem.perBankWrBursts::1 7665 # Per bank write bursts +system.physmem.perBankWrBursts::2 8071 # Per bank write bursts +system.physmem.perBankWrBursts::3 7733 # Per bank write bursts +system.physmem.perBankWrBursts::4 7203 # Per bank write bursts +system.physmem.perBankWrBursts::5 7017 # Per bank write bursts +system.physmem.perBankWrBursts::6 6707 # Per bank write bursts +system.physmem.perBankWrBursts::7 6431 # Per bank write bursts +system.physmem.perBankWrBursts::8 7312 # Per bank write bursts +system.physmem.perBankWrBursts::9 6902 # Per bank write bursts +system.physmem.perBankWrBursts::10 7273 # Per bank write bursts +system.physmem.perBankWrBursts::11 6973 # Per bank write bursts +system.physmem.perBankWrBursts::12 7066 # Per bank write bursts +system.physmem.perBankWrBursts::13 8009 # Per bank write bursts +system.physmem.perBankWrBursts::14 7985 # Per bank write bursts system.physmem.perBankWrBursts::15 7949 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 29 # Number of times write queue was full causing retry -system.physmem.totGap 1887159671500 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times write queue was full causing retry +system.physmem.totGap 1906028705500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404702 # Read request sizes (log2) +system.physmem.readPktSize::6 404835 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118023 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118142 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 64 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,187 +148,196 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.182842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.768050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 414.563237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14483 22.79% 22.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10991 17.29% 40.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4893 7.70% 47.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3583 5.64% 53.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2419 3.81% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1815 2.86% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1455 2.29% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1407 2.21% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22517 35.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63563 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.639515 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2907.321691 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5276 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 519.304127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.318074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.802576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14872 23.08% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11053 17.15% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5024 7.80% 48.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3269 5.07% 53.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2580 4.00% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1937 3.01% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4194 6.51% 66.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1317 2.04% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20191 31.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64437 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5312 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.190700 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2898.366893 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5309 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5279 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5279 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.352529 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.833418 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.552708 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4665 88.37% 88.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 223 4.22% 92.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 69 1.31% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 13 0.25% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 7 0.13% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 8 0.15% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.21% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 9 0.17% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 33 0.63% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 187 3.54% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 5 0.09% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 7 0.13% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.06% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 9 0.17% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5279 # Writes before turning the bus around for reads -system.physmem.totQLat 2194493000 # Total ticks spent queuing -system.physmem.totMemAccLat 9780574250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2022955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5423.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5312 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5312 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.236446 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.912972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.909399 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4665 87.82% 87.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 19 0.36% 88.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 18 0.34% 88.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 199 3.75% 92.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 5 0.09% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.47% 92.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 40 0.75% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.11% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 23 0.43% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.11% 94.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.08% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.17% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.38% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.45% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 32 0.60% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.06% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 171 3.22% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.08% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.06% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.08% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 8 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5312 # Writes before turning the bus around for reads +system.physmem.totQLat 2653633250 # Total ticks spent queuing +system.physmem.totMemAccLat 10242320750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6556.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24173.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25306.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing -system.physmem.readRowHits 363582 # Number of row buffer hits during reads -system.physmem.writeRowHits 95445 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes -system.physmem.avgGap 3610234.20 # Average gap between requests -system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233596440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127458375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1576130400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 379397520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60352481790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1079356093500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1265285353785 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.470116 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1795392967750 # Time in different power states -system.physmem_0.memoryStateTime::REF 63016460000 # Time in different power states +system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing +system.physmem.readRowHits 362859 # Number of row buffer hits during reads +system.physmem.writeRowHits 95554 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes +system.physmem.avgGap 3644574.63 # Average gap between requests +system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238049280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 129888000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577136600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 380058480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67941192465 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084023651750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278782921775 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.912502 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1803110214250 # Time in different power states +system.physmem_0.memoryStateTime::REF 63646700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28752031000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39278414500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246939840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134739000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579679400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385236000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61300664820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1078524362250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1265431817070 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.547722 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1794008459000 # Time in different power states -system.physmem_1.memoryStateTime::REF 63016460000 # Time in different power states +system.physmem_1.actEnergy 249094440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135914625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579757400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385359120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68603580630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1083442617750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278889269165 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.968292 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1802146960250 # Time in different power states +system.physmem_1.memoryStateTime::REF 63646700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30136553500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 40241682250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14997890 # Number of BP lookups -system.cpu.branchPred.condPredicted 13009268 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370594 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9393435 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5198350 # Number of BTB hits +system.cpu.branchPred.lookups 15005157 # Number of BP lookups +system.cpu.branchPred.condPredicted 13016352 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 370563 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9544476 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5200630 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.340246 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807960 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32049 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 54.488376 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807259 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30802 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9241004 # DTB read hits -system.cpu.dtb.read_misses 17472 # DTB read misses +system.cpu.dtb.read_hits 9242284 # DTB read hits +system.cpu.dtb.read_misses 17197 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766036 # DTB read accesses -system.cpu.dtb.write_hits 6386411 # DTB write hits -system.cpu.dtb.write_misses 2301 # DTB write misses +system.cpu.dtb.read_accesses 765766 # DTB read accesses +system.cpu.dtb.write_hits 6387071 # DTB write hits +system.cpu.dtb.write_misses 2294 # DTB write misses system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298419 # DTB write accesses -system.cpu.dtb.data_hits 15627415 # DTB hits -system.cpu.dtb.data_misses 19773 # DTB misses +system.cpu.dtb.write_accesses 298411 # DTB write accesses +system.cpu.dtb.data_hits 15629355 # DTB hits +system.cpu.dtb.data_misses 19491 # DTB misses system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1064455 # DTB accesses -system.cpu.itb.fetch_hits 4013195 # ITB hits -system.cpu.itb.fetch_misses 6857 # ITB misses -system.cpu.itb.fetch_acv 677 # ITB acv -system.cpu.itb.fetch_accesses 4020052 # ITB accesses +system.cpu.dtb.data_accesses 1064177 # DTB accesses +system.cpu.itb.fetch_hits 4015320 # ITB hits +system.cpu.itb.fetch_misses 6841 # ITB misses +system.cpu.itb.fetch_acv 659 # ITB acv +system.cpu.itb.fetch_accesses 4022161 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -341,39 +350,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 182043546 # number of cpu cycles simulated +system.cpu.numCycles 223168437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56125948 # Number of instructions committed -system.cpu.committedOps 56125948 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2502558 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5565 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3594204473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.243483 # CPI: cycles per instruction -system.cpu.ipc 0.308311 # IPC: instructions per cycle +system.cpu.committedInsts 56132533 # Number of instructions committed +system.cpu.committedOps 56132533 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2504504 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5489 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3590815720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.975741 # CPI: cycles per instruction +system.cpu.ipc 0.251525 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211461 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74782 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211546 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74811 40.93% 40.93% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1902 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105860 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73415 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1902 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73415 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1834747397000 97.22% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80828500 0.00% 97.23% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 680298500 0.04% 97.26% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51658959000 2.74% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1887167483000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105910 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182756 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73444 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73444 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148923 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837436986000 96.40% 96.40% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 81017000 0.00% 96.41% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 682412000 0.04% 96.44% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 67836062500 3.56% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1906036477500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981727 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693510 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814906 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693457 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814873 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -409,115 +418,115 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175514 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175591 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5129 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192398 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1739 -system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324983 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192481 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.325047 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36501486500 1.93% 1.93% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4115911000 0.22% 2.15% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1846550075500 97.85% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4173 # number of times the context was actually changed -system.cpu.tickCycles 86269078 # Number of cycles that the object actually ticked -system.cpu.idleCycles 95774468 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395484 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.981722 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13771544 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395996 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.865031 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.981722 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393243 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 38636753000 2.03% 2.03% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4528404000 0.24% 2.26% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862871310500 97.74% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.tickCycles 86394668 # Number of cycles that the object actually ticked +system.cpu.idleCycles 136773769 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395457 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.977331 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13772866 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395969 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.866169 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 121717500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.977331 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63656757 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63656757 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7813939 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7813939 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5575873 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5575873 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182717 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182717 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198981 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198981 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13389812 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13389812 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13389812 # number of overall hits -system.cpu.dcache.overall_hits::total 13389812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 574561 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 574561 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17285 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17285 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1776395 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1776395 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1776395 # number of overall misses -system.cpu.dcache.overall_misses::total 1776395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32870602000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32870602000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22298477500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22298477500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232185000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232185000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55169079500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55169079500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55169079500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55169079500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9015773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9015773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150434 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150434 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198981 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198981 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15166207 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15166207 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15166207 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15166207 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133303 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133303 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093418 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093418 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086424 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086424 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31056.763558 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31056.763558 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63663599 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63663599 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5575814 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5575814 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182834 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182834 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199026 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199026 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13390973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13390973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13390973 # number of overall hits +system.cpu.dcache.overall_hits::total 13390973 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201770 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201770 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 575091 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 575091 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17213 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17213 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776861 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776861 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776861 # number of overall misses +system.cpu.dcache.overall_misses::total 1776861 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46961675000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46961675000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33993891500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33993891500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 235176000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 235176000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80955566500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80955566500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80955566500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80955566500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6150905 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150905 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200047 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200047 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199026 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199026 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15167834 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15167834 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15167834 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15167834 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133279 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093497 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093497 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117147 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117147 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39077.090458 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39077.090458 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59110.456432 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59110.456432 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13662.696799 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13662.696799 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45561.001395 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45561.001395 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,129 +535,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838310 # number of writebacks -system.cpu.dcache.writebacks::total 838310 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127379 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127379 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270264 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270264 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838295 # number of writebacks +system.cpu.dcache.writebacks::total 838295 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127341 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127341 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270722 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 270722 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 397643 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 397643 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 397643 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124816.826374 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125070.657444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131083.368870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124816.826374 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125070.657444 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -800,126 +809,132 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76511 # number of writebacks -system.cpu.l2cache.writebacks::total 76511 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 76630 # number of writebacks +system.cpu.l2cache.writebacks::total 76630 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 317 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 317 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116544 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116544 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16406 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16406 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272166 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272166 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16406 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388710 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16406 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388710 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405116 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16415 # 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number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 453499 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 453499 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7758089500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7758089500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1150653000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1150653000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17010167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17010167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1150653000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24768256500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25918909500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1150653000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24768256500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25918909500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363977000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363977000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1930958000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1930958000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3294935000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3294935000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9622 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9622 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16552 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16552 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1214500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1214500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13695042500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13695042500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1987583500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1987583500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30951837500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30951837500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1987583500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44646880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46634463500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1987583500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44646880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46634463500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364010000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364010000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931836500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931836500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3295846500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3295846500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011239 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249303 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249303 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141862 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141862 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383239 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383239 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011240 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249344 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249344 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141874 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141874 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71441.176471 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71441.176471 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117402.850407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117402.850407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121083.368870 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121083.368870 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113715.758709 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113715.758709 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196826.839827 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196826.839827 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200772.864269 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200772.864269 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199120.740696 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199120.740696 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5711775 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2855459 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 956362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2277135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 956450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2277896 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304307 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304307 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459755 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304379 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304379 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1460498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091781 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8597358 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93420352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143049956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236470308 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422854 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6149527 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.252989 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4380147 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219373 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8599520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93467712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143047028 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236514740 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422969 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6151080 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000871 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029504 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5726891 93.13% 93.13% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 422636 6.87% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6145721 99.91% 99.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5359 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6149527 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3706565999 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6151080 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3707269500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 284383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2189850563 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2190955582 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105755497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105716998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -935,9 +950,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51172 # Transaction distribution -system.iobus.trans_dist::WriteResp 51172 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5096 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51174 # Transaction distribution +system.iobus.trans_dist::WriteResp 51174 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5100 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -949,11 +964,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33100 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33104 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20384 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116554 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20400 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -965,11 +980,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44324 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44340 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705932 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4707000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705948 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4711000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -991,23 +1006,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216043265 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215087245 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23480000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23482000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.302220 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.290787 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1729987199000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.302220 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081389 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081389 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1748608829000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.290787 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080674 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080674 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1021,14 +1036,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908791382 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4908791382 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21943883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21943883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427163362 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427163362 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21943883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21943883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21943883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21943883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1045,19 +1060,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126843.254335 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126843.254335 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130611.363159 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130611.363159 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126843.254335 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126843.254335 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1071,14 +1086,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831191382 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2831191382 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13293883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13293883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3349563362 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3349563362 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13293883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13293883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13293883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13293883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1087,63 +1102,63 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76843.254335 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80611.363159 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80611.363159 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295659 # Transaction distribution -system.membus.trans_dist::WriteReq 9620 # Transaction distribution -system.membus.trans_dist::WriteResp 9620 # Transaction distribution -system.membus.trans_dist::Writeback 118023 # Transaction distribution -system.membus.trans_dist::CleanEvict 262178 # Transaction distribution -system.membus.trans_dist::UpgradeReq 157 # Transaction distribution -system.membus.trans_dist::UpgradeResp 157 # Transaction distribution -system.membus.trans_dist::ReadExReq 116404 # Transaction distribution -system.membus.trans_dist::ReadExResp 116404 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution +system.membus.trans_dist::ReadResp 295688 # Transaction distribution +system.membus.trans_dist::WriteReq 9622 # Transaction distribution +system.membus.trans_dist::WriteResp 9622 # Transaction distribution +system.membus.trans_dist::Writeback 118142 # Transaction distribution +system.membus.trans_dist::CleanEvict 262192 # Transaction distribution +system.membus.trans_dist::UpgradeReq 159 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159 # Transaction distribution +system.membus.trans_dist::ReadExReq 116508 # Transaction distribution +system.membus.trans_dist::ReadExResp 116508 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288774 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148635 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1149038 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1182174 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306584 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30840996 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1306991 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44340 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30812800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30857140 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33498724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33514868 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 843798 # Request fanout histogram +system.membus.snoop_fanout::samples 844052 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843798 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 844052 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843798 # Request fanout histogram -system.membus.reqLayer0.occupancy 29290000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 844052 # Request fanout histogram +system.membus.reqLayer0.occupancy 29776500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1318757186 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319401645 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160035845 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160603841 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72019946 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69882415 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 7571a76a8..c3ff68c1f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906957 # Number of seconds simulated -sim_ticks 1906956794000 # Number of ticks simulated -final_tick 1906956794000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.921764 # Number of seconds simulated +sim_ticks 1921763645000 # Number of ticks simulated +final_tick 1921763645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101212 # Simulator instruction rate (inst/s) -host_op_rate 101212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3411514986 # Simulator tick rate (ticks/s) -host_mem_usage 375140 # Number of bytes of host memory used -host_seconds 558.98 # Real time elapsed on the host -sim_insts 56575230 # Number of instructions simulated -sim_ops 56575230 # Number of ops (including micro ops) simulated +host_inst_rate 133766 # Simulator instruction rate (inst/s) +host_op_rate 133766 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4532754153 # Simulator tick rate (ticks/s) +host_mem_usage 384052 # Number of bytes of host memory used +host_seconds 423.97 # Real time elapsed on the host +sim_insts 56713315 # Number of instructions simulated +sim_ops 56713315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 862400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24773696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 117248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 514752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 874240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24774144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 514944 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26269056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 862400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 117248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 979648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861568 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861568 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13475 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1832 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8043 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26267328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 874240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7875136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7875136 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13660 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387096 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8046 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410454 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122837 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122837 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 452239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12991220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 61484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 269934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13775381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 452239 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 61484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4122573 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4122573 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4122573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 452239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12991220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 61484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 269934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17897953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410454 # Number of read requests accepted -system.physmem.writeReqs 122837 # Number of write requests accepted -system.physmem.readBursts 410454 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122837 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 7860160 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26269056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7861568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410427 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123049 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123049 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 454915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12891358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 267954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13668345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 454915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53617 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 508533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4097869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4097869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4097869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 454915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12891358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 267954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17766214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410427 # Number of read requests accepted +system.physmem.writeReqs 123049 # Number of write requests accepted +system.physmem.readBursts 410427 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123049 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26259904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 7874176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26267328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7875136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 46373 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26161 # Per bank write bursts -system.physmem.perBankRdBursts::1 25973 # Per bank write bursts -system.physmem.perBankRdBursts::2 26108 # Per bank write bursts -system.physmem.perBankRdBursts::3 25765 # Per bank write bursts -system.physmem.perBankRdBursts::4 25066 # Per bank write bursts -system.physmem.perBankRdBursts::5 25574 # Per bank write bursts -system.physmem.perBankRdBursts::6 25905 # Per bank write bursts -system.physmem.perBankRdBursts::7 25241 # Per bank write bursts -system.physmem.perBankRdBursts::8 25825 # Per bank write bursts -system.physmem.perBankRdBursts::9 26325 # Per bank write bursts -system.physmem.perBankRdBursts::10 25290 # Per bank write bursts -system.physmem.perBankRdBursts::11 25205 # Per bank write bursts -system.physmem.perBankRdBursts::12 25472 # Per bank write bursts -system.physmem.perBankRdBursts::13 25390 # Per bank write bursts -system.physmem.perBankRdBursts::14 25632 # Per bank write bursts -system.physmem.perBankRdBursts::15 25396 # Per bank write bursts -system.physmem.perBankWrBursts::0 8442 # Per bank write bursts -system.physmem.perBankWrBursts::1 7958 # Per bank write bursts -system.physmem.perBankWrBursts::2 8052 # Per bank write bursts -system.physmem.perBankWrBursts::3 7723 # Per bank write bursts -system.physmem.perBankWrBursts::4 7027 # Per bank write bursts -system.physmem.perBankWrBursts::5 7199 # Per bank write bursts -system.physmem.perBankWrBursts::6 7428 # Per bank write bursts -system.physmem.perBankWrBursts::7 6815 # Per bank write bursts -system.physmem.perBankWrBursts::8 7536 # Per bank write bursts -system.physmem.perBankWrBursts::9 7897 # Per bank write bursts -system.physmem.perBankWrBursts::10 7294 # Per bank write bursts -system.physmem.perBankWrBursts::11 7366 # Per bank write bursts -system.physmem.perBankWrBursts::12 7733 # Per bank write bursts -system.physmem.perBankWrBursts::13 8096 # Per bank write bursts -system.physmem.perBankWrBursts::14 8387 # Per bank write bursts -system.physmem.perBankWrBursts::15 7862 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 46661 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25500 # Per bank write bursts +system.physmem.perBankRdBursts::1 25969 # Per bank write bursts +system.physmem.perBankRdBursts::2 26011 # Per bank write bursts +system.physmem.perBankRdBursts::3 25727 # Per bank write bursts +system.physmem.perBankRdBursts::4 25508 # Per bank write bursts +system.physmem.perBankRdBursts::5 25811 # Per bank write bursts +system.physmem.perBankRdBursts::6 25519 # Per bank write bursts +system.physmem.perBankRdBursts::7 25160 # Per bank write bursts +system.physmem.perBankRdBursts::8 25451 # Per bank write bursts +system.physmem.perBankRdBursts::9 25839 # Per bank write bursts +system.physmem.perBankRdBursts::10 25659 # Per bank write bursts +system.physmem.perBankRdBursts::11 25030 # Per bank write bursts +system.physmem.perBankRdBursts::12 26076 # Per bank write bursts +system.physmem.perBankRdBursts::13 25978 # Per bank write bursts +system.physmem.perBankRdBursts::14 25473 # Per bank write bursts +system.physmem.perBankRdBursts::15 25600 # Per bank write bursts +system.physmem.perBankWrBursts::0 8066 # Per bank write bursts +system.physmem.perBankWrBursts::1 8046 # Per bank write bursts +system.physmem.perBankWrBursts::2 8027 # Per bank write bursts +system.physmem.perBankWrBursts::3 7668 # Per bank write bursts +system.physmem.perBankWrBursts::4 7376 # Per bank write bursts +system.physmem.perBankWrBursts::5 7761 # Per bank write bursts +system.physmem.perBankWrBursts::6 7583 # Per bank write bursts +system.physmem.perBankWrBursts::7 6991 # Per bank write bursts +system.physmem.perBankWrBursts::8 7326 # Per bank write bursts +system.physmem.perBankWrBursts::9 7600 # Per bank write bursts +system.physmem.perBankWrBursts::10 7532 # Per bank write bursts +system.physmem.perBankWrBursts::11 7413 # Per bank write bursts +system.physmem.perBankWrBursts::12 7962 # Per bank write bursts +system.physmem.perBankWrBursts::13 8267 # Per bank write bursts +system.physmem.perBankWrBursts::14 7722 # Per bank write bursts +system.physmem.perBankWrBursts::15 7694 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 1906952476500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1921759329500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410454 # Read request sizes (log2) +system.physmem.readPktSize::6 410427 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122837 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123049 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,187 +158,199 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.098216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.146393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.677441 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14983 23.10% 23.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11330 17.47% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5177 7.98% 48.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3304 5.09% 53.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2428 3.74% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1616 2.49% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1474 2.27% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1311 2.02% 64.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23234 35.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64857 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5518 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.361182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2842.300525 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5515 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 72 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 522.687084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.252168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.914363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14928 22.86% 22.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11344 17.37% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5465 8.37% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2873 4.40% 53.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2572 3.94% 56.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1636 2.51% 59.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3782 5.79% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1204 1.84% 67.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21501 32.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65305 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5548 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.956561 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2834.723442 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5545 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5518 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.257158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.834122 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.444866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4906 88.91% 88.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 212 3.84% 92.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 76 1.38% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 18 0.33% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 9 0.16% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 6 0.11% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 17 0.31% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 11 0.20% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 35 0.63% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 173 3.14% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.14% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.09% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 6 0.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 4 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5518 # Writes before turning the bus around for reads -system.physmem.totQLat 4043689250 # Total ticks spent queuing -system.physmem.totMemAccLat 11737339250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9854.77 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5548 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.176280 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.947134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.868875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4772 86.01% 86.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 155 2.79% 88.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 19 0.34% 89.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 186 3.35% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 8 0.14% 92.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.38% 93.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.74% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 18 0.32% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 27 0.49% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.16% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.36% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.43% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 29 0.52% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 158 2.85% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.04% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.07% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 14 0.25% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5548 # Writes before turning the bus around for reads +system.physmem.totQLat 4465229000 # Total ticks spent queuing +system.physmem.totMemAccLat 12158560250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10882.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28604.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29632.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing -system.physmem.readRowHits 369741 # Number of row buffer hits during reads -system.physmem.writeRowHits 98545 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.22 # Row buffer hit rate for writes -system.physmem.avgGap 3575819.72 # Average gap between requests -system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242910360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132540375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1605185400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392973120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57318973425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1093892654250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278138192210 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.251160 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1819616623000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63677380000 # Time in different power states +system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing +system.physmem.readRowHits 369445 # Number of row buffer hits during reads +system.physmem.writeRowHits 98595 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes +system.physmem.avgGap 3602335.12 # Average gap between requests +system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245919240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134182125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1600599000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 398636640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63180018945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1097637063000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1288716655350 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.590642 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1825809460500 # Time in different power states +system.physmem_0.memoryStateTime::REF 64171900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23660103250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31782207000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247408560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134994750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1595373000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402868080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57679570530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1093576349250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278189519450 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.278071 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1819088073250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63677380000 # Time in different power states +system.physmem_1.actEnergy 247786560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135201000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1599826800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 398623680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62993858085 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1097800353750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1288695886275 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.579840 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1826084104500 # Time in different power states +system.physmem_1.memoryStateTime::REF 64171900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24188666750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31507549250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16421216 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14369135 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 322041 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10416019 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5388507 # Number of BTB hits +system.cpu0.branchPred.lookups 16172722 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14147320 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 315974 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10263532 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5327857 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.732884 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 814349 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 18392 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 51.910561 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 805529 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17788 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9282981 # DTB read hits -system.cpu0.dtb.read_misses 32197 # DTB read misses -system.cpu0.dtb.read_acv 549 # DTB read access violations -system.cpu0.dtb.read_accesses 681404 # DTB read accesses -system.cpu0.dtb.write_hits 5956980 # DTB write hits -system.cpu0.dtb.write_misses 7300 # DTB write misses -system.cpu0.dtb.write_acv 382 # DTB write access violations -system.cpu0.dtb.write_accesses 235779 # DTB write accesses -system.cpu0.dtb.data_hits 15239961 # DTB hits -system.cpu0.dtb.data_misses 39497 # DTB misses -system.cpu0.dtb.data_acv 931 # DTB access violations -system.cpu0.dtb.data_accesses 917183 # DTB accesses -system.cpu0.itb.fetch_hits 1451467 # ITB hits -system.cpu0.itb.fetch_misses 20802 # ITB misses -system.cpu0.itb.fetch_acv 603 # ITB acv -system.cpu0.itb.fetch_accesses 1472269 # ITB accesses +system.cpu0.dtb.read_hits 9178933 # DTB read hits +system.cpu0.dtb.read_misses 32423 # DTB read misses +system.cpu0.dtb.read_acv 530 # DTB read access violations +system.cpu0.dtb.read_accesses 683199 # DTB read accesses +system.cpu0.dtb.write_hits 5878949 # DTB write hits +system.cpu0.dtb.write_misses 7260 # DTB write misses +system.cpu0.dtb.write_acv 384 # DTB write access violations +system.cpu0.dtb.write_accesses 235377 # DTB write accesses +system.cpu0.dtb.data_hits 15057882 # DTB hits +system.cpu0.dtb.data_misses 39683 # DTB misses +system.cpu0.dtb.data_acv 914 # DTB access violations +system.cpu0.dtb.data_accesses 918576 # DTB accesses +system.cpu0.itb.fetch_hits 1433805 # ITB hits +system.cpu0.itb.fetch_misses 20098 # ITB misses +system.cpu0.itb.fetch_acv 602 # ITB acv +system.cpu0.itb.fetch_accesses 1453903 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,598 +363,599 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 115722397 # number of cpu cycles simulated +system.cpu0.numCycles 146988157 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26666578 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 71121267 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16421216 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6202856 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 81967119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1079386 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 563 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29093 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 971886 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 464461 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8198819 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 234916 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 110639677 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.642819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.946891 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26434329 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70323281 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16172722 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6133386 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 112438747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1062414 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 847 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 925731 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 462393 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 403 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8125656 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 231201 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 140823886 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.499370 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.736005 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 97354556 87.99% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 847860 0.77% 88.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1824694 1.65% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 789927 0.71% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2609447 2.36% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576925 0.52% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 654110 0.59% 94.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 850099 0.77% 95.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5132059 4.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 127673480 90.66% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 835079 0.59% 91.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1817427 1.29% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 778983 0.55% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2600412 1.85% 94.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 568090 0.40% 95.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 652333 0.46% 95.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 824353 0.59% 96.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5073729 3.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 110639677 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.141902 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614585 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21680681 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78105435 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8575313 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1774700 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 503547 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 522363 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36577 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62219552 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 111460 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 503547 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22526069 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 50558199 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19082823 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9419071 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8549966 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 60053732 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 197896 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2013708 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 145060 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4631346 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 40115150 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72965738 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72822559 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 133404 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35357429 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4757713 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1490349 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 215164 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12632454 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9363221 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6214194 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1348186 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 960020 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53527289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1914294 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52757497 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 50335 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6507909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2851663 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1318911 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 110639677 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.476841 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.213091 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 140823886 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.110027 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.478428 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21407057 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108692435 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8462793 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1765937 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 495663 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 515138 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35957 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61540375 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 109013 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 495663 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22243524 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 77757616 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19856258 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9307175 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11163648 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59419645 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 199110 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2023904 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 235068 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7176378 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39704161 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72277966 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72138515 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 129817 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34987460 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4716693 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1464722 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 211632 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12540163 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9262921 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6150917 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1355884 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 997025 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52994830 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1876718 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52216371 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52644 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6477091 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2861227 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1292062 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 140823886 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.370792 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088351 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 88942477 80.39% 80.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9398072 8.49% 88.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3917958 3.54% 92.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2747278 2.48% 94.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2855598 2.58% 97.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1392573 1.26% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 913992 0.83% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 361366 0.33% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 110363 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 119350315 84.75% 84.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9307127 6.61% 91.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3871720 2.75% 94.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2724493 1.93% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2821208 2.00% 98.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1374944 0.98% 99.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 898986 0.64% 99.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 361887 0.26% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 113206 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 110639677 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 140823886 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 181613 18.32% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 474655 47.88% 66.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 334992 33.79% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 180499 18.19% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 473486 47.73% 65.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 338115 34.08% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36170574 68.56% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57549 0.11% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28793 0.05% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9634233 18.26% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6027526 11.42% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 833151 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35829212 68.62% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56563 0.11% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28580 0.05% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9526937 18.25% 87.04% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5949680 11.39% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 819736 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52757497 # Type of FU issued -system.cpu0.iq.rate 0.455897 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 991260 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018789 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 216609620 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61691492 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51347656 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 586645 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 275208 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 269627 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53428897 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 316072 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 584424 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52216371 # Type of FU issued +system.cpu0.iq.rate 0.355242 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 992101 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019000 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 245730281 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61098362 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50826597 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 571091 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 267903 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 262355 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52896880 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307812 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 579556 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1070558 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2876 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17548 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 473318 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1070231 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2809 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17956 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496898 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 412098 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18718 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 406168 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 503547 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 47448039 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 802619 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58859222 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 120684 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9363221 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6214194 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1691778 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39350 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 562336 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17548 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 158131 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 358107 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516238 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52248436 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9338690 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 509060 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 495663 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 74229287 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1063310 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58247929 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 119878 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9262921 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6150917 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1658630 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39535 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 822687 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17956 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 156887 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 351474 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 508361 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51713827 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9234499 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 502543 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3417639 # number of nop insts executed -system.cpu0.iew.exec_refs 15316719 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8298030 # Number of branches executed -system.cpu0.iew.exec_stores 5978029 # Number of stores executed -system.cpu0.iew.exec_rate 0.451498 # Inst execution rate -system.cpu0.iew.wb_sent 51729756 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51617283 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26562977 # num instructions producing a value -system.cpu0.iew.wb_consumers 36791821 # num instructions consuming a value +system.cpu0.iew.exec_nop 3376381 # number of nop insts executed +system.cpu0.iew.exec_refs 15134335 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8213447 # Number of branches executed +system.cpu0.iew.exec_stores 5899836 # Number of stores executed +system.cpu0.iew.exec_rate 0.351823 # Inst execution rate +system.cpu0.iew.wb_sent 51204042 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51088952 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26321891 # num instructions producing a value +system.cpu0.iew.wb_consumers 36458900 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.446044 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.721980 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.347572 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.721961 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6839384 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 595383 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 473671 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 109429659 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.474443 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.410223 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6803374 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 584656 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 464905 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 139620670 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.367725 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.257359 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 91094862 83.25% 83.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7261881 6.64% 89.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3995871 3.65% 93.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2069124 1.89% 95.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1633444 1.49% 96.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 582030 0.53% 97.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 441609 0.40% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 443115 0.40% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1907723 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 121488072 87.01% 87.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7189020 5.15% 92.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3942453 2.82% 94.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2051651 1.47% 96.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1610967 1.15% 97.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 576073 0.41% 98.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 437348 0.31% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 435843 0.31% 98.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1889243 1.35% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 109429659 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51918164 # Number of instructions committed -system.cpu0.commit.committedOps 51918164 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 139620670 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51342045 # Number of instructions committed +system.cpu0.commit.committedOps 51342045 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14033539 # Number of memory references committed -system.cpu0.commit.loads 8292663 # Number of loads committed -system.cpu0.commit.membars 202804 # Number of memory barriers committed -system.cpu0.commit.branches 7846921 # Number of branches committed -system.cpu0.commit.fp_insts 266538 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 48077974 # Number of committed integer instructions. -system.cpu0.commit.function_calls 666824 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2988262 5.76% 5.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33767854 65.04% 70.80% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 56339 0.11% 70.90% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.90% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28331 0.05% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.96% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8495467 16.36% 87.33% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5746879 11.07% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 833149 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13846709 # Number of memory references committed +system.cpu0.commit.loads 8192690 # Number of loads committed +system.cpu0.commit.membars 198882 # Number of memory barriers committed +system.cpu0.commit.branches 7762297 # Number of branches committed +system.cpu0.commit.fp_insts 259271 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47551840 # Number of committed integer instructions. +system.cpu0.commit.function_calls 657143 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2951360 5.75% 5.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33433980 65.12% 70.87% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55376 0.11% 70.98% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28117 0.05% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8391572 16.34% 87.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5660021 11.02% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 819736 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51918164 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1907723 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166079481 # The number of ROB reads -system.cpu0.rob.rob_writes 118719518 # The number of ROB writes -system.cpu0.timesIdled 511712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5082720 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698191192 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48933669 # Number of Instructions Simulated -system.cpu0.committedOps 48933669 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.364883 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.364883 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.422854 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.422854 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68649325 # number of integer regfile reads -system.cpu0.int_regfile_writes 37335516 # number of integer regfile writes -system.cpu0.fp_regfile_reads 132501 # number of floating regfile reads -system.cpu0.fp_regfile_writes 134063 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1824055 # number of misc regfile reads -system.cpu0.misc_regfile_writes 833586 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1296864 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.135915 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10665502 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1297376 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.220826 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26097500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.135915 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988547 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988547 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 51342045 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1889243 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 195675599 # The number of ROB reads +system.cpu0.rob.rob_writes 117488366 # The number of ROB writes +system.cpu0.timesIdled 519286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6164271 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3696539134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48394452 # Number of Instructions Simulated +system.cpu0.committedOps 48394452 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.037294 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.037294 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.329240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.329240 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67992315 # number of integer regfile reads +system.cpu0.int_regfile_writes 36972661 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128885 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130381 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1712039 # number of misc regfile reads +system.cpu0.misc_regfile_writes 819549 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1282830 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.258957 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10531989 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1283342 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.206689 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.258957 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988787 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988787 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 57664711 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 57664711 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6558537 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6558537 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3738792 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3738792 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165967 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 165967 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191452 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191452 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10297329 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10297329 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10297329 # number of overall hits -system.cpu0.dcache.overall_hits::total 10297329 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1618045 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1618045 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1793563 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1793563 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21339 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21339 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2425 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2425 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3411608 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3411608 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3411608 # number of overall misses -system.cpu0.dcache.overall_misses::total 3411608 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39371994500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39371994500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77781772548 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77781772548 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331348500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 331348500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20480000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20480000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117153767048 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117153767048 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117153767048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117153767048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8176582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8176582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5532355 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5532355 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 187306 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 187306 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193877 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 193877 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13708937 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13708937 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13708937 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13708937 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197888 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197888 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324195 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324195 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113926 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113926 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012508 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012508 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248860 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248860 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248860 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248860 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24333.065211 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24333.065211 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43367.181720 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43367.181720 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15527.836356 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15527.836356 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8445.360825 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8445.360825 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34339.750361 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34339.750361 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4364063 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4809 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 121083 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 97 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.041913 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 49.577320 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 56925383 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56925383 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6490454 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6490454 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3680062 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3680062 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162917 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 162917 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187619 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 187619 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10170516 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10170516 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10170516 # number of overall hits +system.cpu0.dcache.overall_hits::total 10170516 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1594902 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1594902 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1768783 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1768783 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20957 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20957 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2842 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2842 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3363685 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3363685 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3363685 # number of overall misses +system.cpu0.dcache.overall_misses::total 3363685 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54779472000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54779472000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114120076576 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114120076576 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 388638000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 388638000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44723000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44723000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 168899548576 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 168899548576 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 168899548576 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 168899548576 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8085356 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8085356 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5448845 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5448845 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183874 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183874 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190461 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 190461 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13534201 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13534201 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13534201 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13534201 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197258 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197258 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324616 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324616 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113975 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113975 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014922 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014922 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248532 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248532 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248532 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248532 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34346.606876 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34346.606876 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64518.980890 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64518.980890 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18544.543589 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18544.543589 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15736.453202 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15736.453202 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50212.653259 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50212.653259 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6977235 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 18493 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 125 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.354674 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 147.944000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 766891 # number of writebacks -system.cpu0.dcache.writebacks::total 766891 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 594303 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 594303 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523628 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1523628 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5200 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5200 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2117931 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2117931 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2117931 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2117931 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1023742 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1023742 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 269935 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 269935 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16139 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16139 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2425 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2425 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1293677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1293677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1293677 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1293677 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7035 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7035 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10024 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10024 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17059 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17059 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29563027500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29563027500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12280270109 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12280270109 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188351000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188351000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18055000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18055000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41843297609 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 41843297609 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41843297609 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 41843297609 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1480741500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1480741500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2153066498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153066498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3633807998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3633807998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012508 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012508 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094367 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094367 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28877.419799 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28877.419799 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45493.434008 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45493.434008 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11670.549600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11670.549600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7445.360825 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7445.360825 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210482.089552 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210482.089552 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214791.151038 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214791.151038 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 213014.127323 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 213014.127323 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 756224 # number of writebacks +system.cpu0.dcache.writebacks::total 756224 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579464 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 579464 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502811 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1502811 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5193 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5193 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082275 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2082275 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082275 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2082275 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015438 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1015438 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265972 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 265972 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15764 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15764 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2841 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2841 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1281410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281410 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1281410 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10125 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17170 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43462270000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43462270000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18192812239 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18192812239 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186019000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186019000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41882000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41882000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61655082239 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61655082239 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61655082239 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61655082239 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1482526500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1482526500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2174117500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2174117500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3656644000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3656644000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048813 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048813 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014916 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014916 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094679 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094679 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42801.500436 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42801.500436 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68401.231103 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68401.231103 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11800.241056 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11800.241056 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14741.992256 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14741.992256 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210436.692690 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210436.692690 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214727.654321 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214727.654321 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212967.035527 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212967.035527 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 927295 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.382377 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7224199 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 927807 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.786317 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28149280500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.382377 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994887 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994887 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9126911 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9126911 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7224199 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7224199 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7224199 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7224199 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7224199 # number of overall hits -system.cpu0.icache.overall_hits::total 7224199 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 974618 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 974618 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 974618 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 974618 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 974618 # number of overall misses -system.cpu0.icache.overall_misses::total 974618 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13621983991 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13621983991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13621983991 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13621983991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13621983991 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13621983991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8198817 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8198817 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8198817 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8198817 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8198817 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8198817 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118873 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118873 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118873 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118873 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118873 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118873 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13976.741647 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13976.741647 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13976.741647 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13976.741647 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5225 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 909478 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.072720 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7170024 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 909987 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.879260 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42291813500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.072720 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992330 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992330 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9035950 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9035950 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7170024 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7170024 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7170024 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7170024 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7170024 # number of overall hits +system.cpu0.icache.overall_hits::total 7170024 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 955631 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 955631 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 955631 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 955631 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 955631 # number of overall misses +system.cpu0.icache.overall_misses::total 955631 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14538250986 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14538250986 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14538250986 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14538250986 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14538250986 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14538250986 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8125655 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8125655 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8125655 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8125655 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8125655 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8125655 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117607 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117607 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117607 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117607 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117607 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117607 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15213.247567 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15213.247567 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15213.247567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15213.247567 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8860 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 285 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.738916 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 31.087719 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 46524 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 46524 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 46524 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 46524 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 46524 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 46524 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 928094 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 928094 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 928094 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 928094 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 928094 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 928094 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12135046494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12135046494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12135046494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12135046494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12135046494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12135046494 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113199 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113199 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13075.234291 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45336 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45336 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45336 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45336 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45336 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45336 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 910295 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 910295 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 910295 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 910295 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 910295 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 910295 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12844771491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12844771491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12844771491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12844771491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12844771491 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12844771491 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112027 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.112027 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.112027 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14110.559204 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3314305 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2896651 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 61906 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1740825 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 779195 # Number of BTB hits +system.cpu1.branchPred.lookups 3566695 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3123821 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 62988 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1777720 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 839763 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 44.760099 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 157645 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4636 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 47.238204 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 169438 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 5003 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1755656 # DTB read hits -system.cpu1.dtb.read_misses 9508 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 286377 # DTB read accesses -system.cpu1.dtb.write_hits 1073642 # DTB write hits -system.cpu1.dtb.write_misses 1995 # DTB write misses -system.cpu1.dtb.write_acv 40 # DTB write access violations -system.cpu1.dtb.write_accesses 108795 # DTB write accesses -system.cpu1.dtb.data_hits 2829298 # DTB hits -system.cpu1.dtb.data_misses 11503 # DTB misses -system.cpu1.dtb.data_acv 45 # DTB access violations -system.cpu1.dtb.data_accesses 395172 # DTB accesses -system.cpu1.itb.fetch_hits 497795 # ITB hits -system.cpu1.itb.fetch_misses 4809 # ITB misses -system.cpu1.itb.fetch_acv 84 # ITB acv -system.cpu1.itb.fetch_accesses 502604 # ITB accesses +system.cpu1.dtb.read_hits 1880373 # DTB read hits +system.cpu1.dtb.read_misses 9576 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 286028 # DTB read accesses +system.cpu1.dtb.write_hits 1172828 # DTB write hits +system.cpu1.dtb.write_misses 2034 # DTB write misses +system.cpu1.dtb.write_acv 35 # DTB write access violations +system.cpu1.dtb.write_accesses 108538 # DTB write accesses +system.cpu1.dtb.data_hits 3053201 # DTB hits +system.cpu1.dtb.data_misses 11610 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 394566 # DTB accesses +system.cpu1.itb.fetch_hits 516269 # ITB hits +system.cpu1.itb.fetch_misses 4737 # ITB misses +system.cpu1.itb.fetch_acv 64 # ITB acv +system.cpu1.itb.fetch_accesses 521006 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -955,563 +968,564 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 13378620 # number of cpu cycles simulated +system.cpu1.numCycles 14959639 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5528968 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12732566 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3314305 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 936840 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 6841586 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 246622 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 24765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 177717 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 60433 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1438917 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48462 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 12756788 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.998101 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.406721 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6140426 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13703075 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3566695 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1009201 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7602996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 256204 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 312 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 176452 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 62292 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1530550 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50498 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14135722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.969393 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.379564 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 10526481 82.52% 82.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 138708 1.09% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 230541 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 169879 1.33% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 284565 2.23% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 115144 0.90% 89.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 131557 1.03% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 159487 1.25% 92.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1000426 7.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11742806 83.07% 83.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 150793 1.07% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 240174 1.70% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 177797 1.26% 87.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 306821 2.17% 89.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 121463 0.86% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 138409 0.98% 91.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 186182 1.32% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1071277 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 12756788 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.247731 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.951710 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4581654 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6264793 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1608431 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 184437 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 117472 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 99495 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5921 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10317942 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 18589 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 117472 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4714026 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 446929 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4987547 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1661018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 829794 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 9788331 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3632 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 64825 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 14992 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 371131 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6443318 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 11674537 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 11622438 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 46696 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5463726 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 979592 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 407944 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 36440 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1686696 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1800249 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1144526 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 213224 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 121752 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8623787 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 466284 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8415044 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20175 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1448509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 669329 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 345933 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 12756788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.659652 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.379213 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14135722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.238421 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.916003 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5035823 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7049483 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1732735 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 195750 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 121930 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 104865 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6244 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11127162 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 19879 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 121930 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5174702 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 499846 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5538858 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1790125 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1010259 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10570144 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4276 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 68050 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 20115 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 516529 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6943229 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12595828 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12537363 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52773 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5938747 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1004482 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 436817 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 40607 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1800852 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1926573 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1243636 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 225182 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 130261 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9311043 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 502453 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9112092 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20417 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1494632 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 673391 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 369352 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14135722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644615 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.367603 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9236176 72.40% 72.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1557417 12.21% 84.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 656816 5.15% 89.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 459502 3.60% 93.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 405096 3.18% 96.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 217416 1.70% 98.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 137120 1.07% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 62655 0.49% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 24590 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10331729 73.09% 73.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1677616 11.87% 84.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 710014 5.02% 89.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 492260 3.48% 93.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 443396 3.14% 96.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 237464 1.68% 98.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 151784 1.07% 99.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 65612 0.46% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 25847 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 12756788 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14135722 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22931 9.91% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 125391 54.21% 64.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 82988 35.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 23101 9.34% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 135152 54.66% 64.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 89008 36.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5217804 62.01% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14291 0.17% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10471 0.12% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1829208 21.74% 84.10% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1094853 13.01% 97.11% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 243140 2.89% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5665609 62.18% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16110 0.18% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10836 0.12% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1960524 21.52% 84.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1194738 13.11% 97.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 258998 2.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8415044 # Type of FU issued -system.cpu1.iq.rate 0.628992 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 231310 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027488 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 29661025 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10457474 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8106737 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 177336 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 85037 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 82464 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8548271 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 94565 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87834 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9112092 # Type of FU issued +system.cpu1.iq.rate 0.609112 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247261 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027135 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 32423377 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11214835 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8782259 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 204207 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 97217 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 94699 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9246642 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 109193 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94025 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 257024 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 716 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4046 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 124034 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 261324 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4031 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 123982 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 425 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 63290 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 65647 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 117472 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 288545 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 130999 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9554579 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 24166 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1800249 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1144526 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 424658 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4139 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 125975 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4046 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28597 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 88577 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117174 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8309020 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1771054 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 106024 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 121930 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 296920 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 166801 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10329862 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 27466 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1926573 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1243636 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 455903 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4091 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 161850 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4031 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28253 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 94223 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 122476 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8997942 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1896570 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 114150 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 464508 # number of nop insts executed -system.cpu1.iew.exec_refs 2851870 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1230259 # Number of branches executed -system.cpu1.iew.exec_stores 1080816 # Number of stores executed -system.cpu1.iew.exec_rate 0.621067 # Inst execution rate -system.cpu1.iew.wb_sent 8217653 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8189201 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3916216 # num instructions producing a value -system.cpu1.iew.wb_consumers 5553340 # num instructions consuming a value +system.cpu1.iew.exec_nop 516366 # number of nop insts executed +system.cpu1.iew.exec_refs 3077114 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1335580 # Number of branches executed +system.cpu1.iew.exec_stores 1180544 # Number of stores executed +system.cpu1.iew.exec_rate 0.601481 # Inst execution rate +system.cpu1.iew.wb_sent 8905860 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8876958 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4235192 # num instructions producing a value +system.cpu1.iew.wb_consumers 6022422 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.612111 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.705200 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.593394 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.703237 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1470840 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 120351 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 107539 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 12487025 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642311 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620138 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1521482 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 133101 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 111980 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13855601 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.631015 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.609308 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 9576588 76.69% 76.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1351659 10.82% 87.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 487280 3.90% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 294734 2.36% 93.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 217151 1.74% 95.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 92181 0.74% 96.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 81385 0.65% 96.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 96065 0.77% 97.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 289982 2.32% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10693520 77.18% 77.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1462734 10.56% 87.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 528018 3.81% 91.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 318233 2.30% 93.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 242012 1.75% 95.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 100894 0.73% 96.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 90931 0.66% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 102553 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 316706 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 12487025 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8020551 # Number of instructions committed -system.cpu1.commit.committedOps 8020551 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13855601 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8743092 # Number of instructions committed +system.cpu1.commit.committedOps 8743092 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2563717 # Number of memory references committed -system.cpu1.commit.loads 1543225 # Number of loads committed -system.cpu1.commit.membars 37500 # Number of memory barriers committed -system.cpu1.commit.branches 1142801 # Number of branches committed -system.cpu1.commit.fp_insts 80747 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7435629 # Number of committed integer instructions. -system.cpu1.commit.function_calls 128494 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 382508 4.77% 4.77% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 4766897 59.43% 64.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14118 0.18% 64.38% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10465 0.13% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1580725 19.71% 84.24% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1020940 12.73% 96.97% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 243139 3.03% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2784903 # Number of memory references committed +system.cpu1.commit.loads 1665249 # Number of loads committed +system.cpu1.commit.membars 42287 # Number of memory barriers committed +system.cpu1.commit.branches 1247450 # Number of branches committed +system.cpu1.commit.fp_insts 93039 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8096711 # Number of committed integer instructions. +system.cpu1.commit.function_calls 139604 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 427747 4.89% 4.89% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5200103 59.48% 64.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 15945 0.18% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10829 0.12% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1707536 19.53% 84.23% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1120175 12.81% 97.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 258998 2.96% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8020551 # Class of committed instruction -system.cpu1.commit.bw_lim_events 289982 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 21604416 # The number of ROB reads -system.cpu1.rob.rob_writes 19248787 # The number of ROB writes -system.cpu1.timesIdled 107122 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 621832 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3799884834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 7641561 # Number of Instructions Simulated -system.cpu1.committedOps 7641561 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.750771 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.750771 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.571177 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.571177 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 10694286 # number of integer regfile reads -system.cpu1.int_regfile_writes 5846668 # number of integer regfile writes -system.cpu1.fp_regfile_reads 46070 # number of floating regfile reads -system.cpu1.fp_regfile_writes 45105 # number of floating regfile writes -system.cpu1.misc_regfile_reads 889333 # number of misc regfile reads -system.cpu1.misc_regfile_writes 191018 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 88757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.801602 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2280391 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 89062 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 25.604534 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1034185237500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.801602 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960550 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.960550 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 10633162 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 10633162 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1420631 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1420631 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 810208 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 810208 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 27933 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 27933 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 26395 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 26395 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2230839 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2230839 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2230839 # number of overall hits -system.cpu1.dcache.overall_hits::total 2230839 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 166361 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 166361 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 175617 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 175617 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4254 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4254 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2523 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2523 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 341978 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 341978 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 341978 # number of overall misses -system.cpu1.dcache.overall_misses::total 341978 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2085855500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2085855500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6615792667 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6615792667 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 40341500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 40341500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21053500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 21053500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8701648167 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8701648167 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8701648167 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8701648167 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1586992 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1586992 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 985825 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 985825 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 32187 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 32187 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 28918 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 28918 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2572817 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2572817 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2572817 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2572817 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.104828 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.104828 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178142 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.178142 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.132165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.132165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087247 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087247 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132920 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.132920 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132920 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.132920 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12538.127927 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12538.127927 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37671.709840 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37671.709840 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9483.192290 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9483.192290 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8344.629409 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8344.629409 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 25445.052509 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 25445.052509 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 379425 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 575 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15060 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.194223 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 47.916667 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 8743092 # Class of committed instruction +system.cpu1.commit.bw_lim_events 316706 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 23719092 # The number of ROB reads +system.cpu1.rob.rob_writes 20805392 # The number of ROB writes +system.cpu1.timesIdled 122607 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 823917 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3827854089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8318863 # Number of Instructions Simulated +system.cpu1.committedOps 8318863 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.798279 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.798279 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556087 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556087 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11586341 # number of integer regfile reads +system.cpu1.int_regfile_writes 6325577 # number of integer regfile writes +system.cpu1.fp_regfile_reads 52057 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51356 # number of floating regfile writes +system.cpu1.misc_regfile_reads 501983 # number of misc regfile reads +system.cpu1.misc_regfile_writes 207801 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 98586 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.617617 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2459541 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 98896 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.869975 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 61777830500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.617617 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950425 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.950425 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11508888 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11508888 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1514240 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1514240 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 887339 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 887339 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 31145 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 31145 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29838 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 29838 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2401579 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2401579 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2401579 # number of overall hits +system.cpu1.dcache.overall_hits::total 2401579 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 186104 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 186104 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 193582 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 193582 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4934 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4934 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2994 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2994 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 379686 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 379686 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 379686 # number of overall misses +system.cpu1.dcache.overall_misses::total 379686 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2502679500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2502679500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9084892318 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9084892318 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46731500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46731500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48320000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 48320000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11587571818 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11587571818 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11587571818 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11587571818 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1700344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1700344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1080921 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1080921 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36079 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 36079 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32832 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 32832 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2781265 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2781265 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2781265 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2781265 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109451 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.109451 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179090 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.179090 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136755 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136755 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136516 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.136516 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136516 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.136516 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13447.746959 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13447.746959 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46930.460053 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46930.460053 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9471.321443 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9471.321443 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16138.944556 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16138.944556 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30518.828237 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 30518.828237 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 537858 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1114 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 16003 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.609823 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 123.777778 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 56462 # number of writebacks -system.cpu1.dcache.writebacks::total 56462 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 100117 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 100117 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 144305 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 144305 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 244422 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 244422 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 244422 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 244422 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 66244 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 66244 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 31312 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 31312 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3781 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3781 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2522 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2522 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 97556 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 97556 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 97556 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 97556 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2884 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2884 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3042 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3042 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 801271000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 801271000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1099670460 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1099670460 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31948000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31948000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18531500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18531500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1900941460 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1900941460 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1900941460 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1900941460 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29727000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29727000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 636171000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 636171000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 665898000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 665898000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.041742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031762 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117470 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117470 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.037918 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.037918 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12095.752068 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12095.752068 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35119.777082 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35119.777082 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8449.616504 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8449.616504 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7347.938144 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7347.938144 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188145.569620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188145.569620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220586.338419 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220586.338419 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 218901.380671 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 218901.380671 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 63787 # number of writebacks +system.cpu1.dcache.writebacks::total 63787 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 112960 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 112960 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 158580 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 158580 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 271540 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 271540 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 271540 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 271540 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73144 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 73144 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35002 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 35002 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4480 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4480 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2993 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2993 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 108146 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 108146 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 108146 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 108146 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2930 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3080 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 925590000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 925590000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553309551 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1553309551 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37834000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37834000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45327000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45327000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2478899551 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2478899551 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2478899551 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2478899551 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 28469500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 28469500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 648479500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 648479500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676949000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676949000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043017 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043017 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032382 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032382 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124172 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124172 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091161 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091161 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038884 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038884 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12654.353057 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12654.353057 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44377.737015 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44377.737015 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8445.089286 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8445.089286 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15144.336786 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15144.336786 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189796.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189796.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221324.061433 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 221324.061433 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 219788.636364 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 219788.636364 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 200477 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.242239 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1230816 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 200989 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.123798 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882066156500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.242239 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918442 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.918442 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1639971 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1639971 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1230816 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1230816 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1230816 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1230816 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1230816 # number of overall hits -system.cpu1.icache.overall_hits::total 1230816 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 208101 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 208101 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 208101 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 208101 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 208101 # number of overall misses -system.cpu1.icache.overall_misses::total 208101 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2838828500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2838828500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2838828500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2838828500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2838828500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2838828500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1438917 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1438917 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1438917 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1438917 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1438917 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1438917 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.144623 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.144623 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.144623 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.144623 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.144623 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.144623 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.589901 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13641.589901 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13641.589901 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13641.589901 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 462 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 222828 # number of replacements +system.cpu1.icache.tags.tagsinuse 467.348174 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1300089 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 223338 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.821172 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1895764140500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.348174 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912789 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.912789 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1753949 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1753949 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1300089 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1300089 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1300089 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1300089 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1300089 # number of overall hits +system.cpu1.icache.overall_hits::total 1300089 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 230461 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 230461 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 230461 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 230461 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 230461 # number of overall misses +system.cpu1.icache.overall_misses::total 230461 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3280299500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3280299500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3280299500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3280299500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3280299500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3280299500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1530550 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1530550 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1530550 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1530550 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1530550 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1530550 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150574 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.150574 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150574 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.150574 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150574 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.150574 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.642569 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14233.642569 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14233.642569 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14233.642569 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 780 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.400000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.571429 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7047 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7047 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7047 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7047 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7047 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7047 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 201054 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 201054 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 201054 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 201054 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 201054 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 201054 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2552554500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2552554500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2552554500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2552554500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2552554500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2552554500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.139726 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.139726 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.139726 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12695.865290 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7062 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7062 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7062 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7062 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7062 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7062 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223399 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 223399 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 223399 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 223399 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 223399 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 223399 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2948315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2948315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2948315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2948315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2948315500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2948315500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.145960 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.145960 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13197.532218 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1527,10 +1541,10 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7371 # Transaction distribution system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 54460 # Transaction distribution -system.iobus.trans_dist::WriteResp 54460 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54607 # Transaction distribution +system.iobus.trans_dist::WriteResp 54607 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1541,12 +1555,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40202 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123662 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1557,13 +1571,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 72634 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734282 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 10965000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73826 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2735458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11255000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1583,52 +1597,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216128229 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215099741 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27294000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27445000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.504095 # Cycle average of tags in use +system.iocache.tags.replacements 41696 # number of replacements +system.iocache.tags.tagsinuse 0.507802 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711315950000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.504095 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031506 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031506 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1725999022000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.507802 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031738 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031738 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.tags.tag_accesses 375552 # Number of tag accesses +system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses +system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses -system.iocache.demand_misses::total 178 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 178 # number of overall misses -system.iocache.overall_misses::total 178 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22218883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22218883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907321346 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907321346 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22218883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22218883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22218883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22218883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses +system.iocache.demand_misses::total 176 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 176 # number of overall misses +system.iocache.overall_misses::total 176 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22249883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22249883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427997858 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427997858 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22249883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22249883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22249883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22249883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1637,40 +1651,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124825.185393 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124825.185393 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.725501 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118100.725501 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124825.185393 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124825.185393 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126419.789773 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126419.789773 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.446332 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130631.446332 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126419.789773 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126419.789773 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # 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mshr miss rate for WriteLineReq accesses @@ -1679,195 +1693,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74825.185393 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.725501 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.725501 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74825.185393 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74825.185393 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76419.789773 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.446332 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.446332 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # 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Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081880 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.094421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003178 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000967 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995480 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2299 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6267 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5773 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50615 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38456225 # Number of tag accesses -system.l2c.tags.data_accesses 38456225 # Number of data accesses -system.l2c.Writeback_hits::writebacks 823353 # number of Writeback hits -system.l2c.Writeback_hits::total 823353 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 230 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 400 # number of UpgradeReq hits +system.l2c.tags.replacements 344948 # number of replacements +system.l2c.tags.tagsinuse 65190.787367 # Cycle average of tags in use +system.l2c.tags.total_refs 3990905 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410112 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.731256 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11174884000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53006.163408 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5332.464187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6575.010887 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 209.732945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 67.415939 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.808810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081367 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.100327 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1750 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5661 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51290 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 38374495 # Number of tag accesses +system.l2c.tags.data_accesses 38374495 # Number of data accesses +system.l2c.Writeback_hits::writebacks 820011 # number of Writeback hits +system.l2c.Writeback_hits::total 820011 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 181 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 256 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 437 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 26 # 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number of demand (read+write) hits -system.l2c.demand_hits::total 2099193 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 914307 # number of overall hits -system.l2c.overall_hits::cpu0.data 906371 # number of overall hits -system.l2c.overall_hits::cpu1.inst 199175 # number of overall hits -system.l2c.overall_hits::cpu1.data 79340 # number of overall hits -system.l2c.overall_hits::total 2099193 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2738 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1002 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3740 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 352 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 366 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 718 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114723 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7302 # 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number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1122774000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 30101005000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 155099500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 879940500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 32258819000 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 823353 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 823353 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2908 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1232 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4140 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 401 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 392 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012303 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254274 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71779.934688 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71691.391941 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71754.807692 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71285.194175 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71790.645880 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71548.780488 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129416.394357 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 148234.089047 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130545.015195 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124263.473250 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114195.362953 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130834.344660 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114245.434061 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197936.692690 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177296.666667 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197506.393329 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203210.666667 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209194.197952 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204553.581003 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201046.709377 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 207640.746753 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202049.654321 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7193 # Transaction distribution -system.membus.trans_dist::ReadResp 296434 # Transaction distribution -system.membus.trans_dist::WriteReq 12908 # Transaction distribution -system.membus.trans_dist::WriteResp 12908 # Transaction distribution -system.membus.trans_dist::Writeback 122837 # Transaction distribution -system.membus.trans_dist::CleanEvict 263082 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9353 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4872 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4824 # Transaction distribution -system.membus.trans_dist::ReadExReq 122000 # Transaction distribution -system.membus.trans_dist::ReadExResp 121659 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289315 # Transaction distribution -system.membus.trans_dist::BadAddressError 74 # Transaction distribution +system.membus.trans_dist::ReadReq 7195 # Transaction distribution +system.membus.trans_dist::ReadResp 296388 # Transaction distribution +system.membus.trans_dist::WriteReq 13055 # Transaction distribution +system.membus.trans_dist::WriteResp 13055 # Transaction distribution +system.membus.trans_dist::Writeback 123049 # Transaction distribution +system.membus.trans_dist::CleanEvict 262884 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10279 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5759 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5112 # Transaction distribution +system.membus.trans_dist::ReadExReq 122086 # Transaction distribution +system.membus.trans_dist::ReadExResp 121678 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289268 # Transaction distribution +system.membus.trans_dist::BadAddressError 75 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1184934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1225284 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1350114 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72634 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31472384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31545018 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1227712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1352540 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73826 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31484224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31558050 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34203258 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10191 # Total snoops (count) -system.membus.snoop_fanout::samples 873294 # Request fanout histogram +system.membus.pkt_size::total 34216290 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11781 # Total snoops (count) +system.membus.snoop_fanout::samples 875308 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 873294 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875308 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 873294 # Request fanout histogram -system.membus.reqLayer0.occupancy 36159500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875308 # Request fanout histogram +system.membus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1354680439 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1356119148 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 95500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 92500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2187139696 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2187698407 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72110882 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69909650 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2235424 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12908 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12908 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 946207 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1643079 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9387 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4947 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14334 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302784 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302784 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1129148 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1099173 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 5063061 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2531463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 338644 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1334 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1266 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2238892 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13055 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13055 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 943078 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1635745 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10313 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5834 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16147 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301580 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301580 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1133694 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1098094 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2591178 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3901537 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 531442 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 279415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7303572 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59378176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131958120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 12865536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9234898 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213436730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 458492 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5507130 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.077786 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.267834 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2554026 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3861302 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 573119 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 309440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7297887 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58240320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130381048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 14295680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10315306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213232354 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462162 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5511701 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.123436 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.329209 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 5078755 92.22% 92.22% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 428375 7.78% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4831850 87.67% 87.67% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 679365 12.33% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 482 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5507130 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3369225418 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5511701 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3368234918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1393343588 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1366825726 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1972546779 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1954242307 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 301679801 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 335428339 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 151036436 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 167784154 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2152,161 +2172,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6502 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 187776 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 66469 40.53% 40.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.17% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 149 0.09% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 95308 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 163983 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 65388 49.23% 49.23% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.45% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 149 0.11% 50.89% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 65239 49.11% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 132833 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864137851500 97.75% 97.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61127000 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 545976000 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 68164000 0.00% 97.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42142829000 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906955947500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983737 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6535 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 184475 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65083 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.20% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 93355 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 160682 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64077 49.21% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.48% 50.79% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63891 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130212 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864797723000 97.04% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61900500 0.00% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 553477500 0.03% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 85562000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56264153500 2.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1921762816500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984543 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684507 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810041 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed -system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 225 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684388 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810371 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed +system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 228 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 249 0.14% 0.14% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3603 2.09% 2.23% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 157157 91.07% 93.34% # number of callpals executed -system.cpu0.kern.callpal::rdps 6335 3.67% 97.01% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.01% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 97.02% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rti 4619 2.68% 99.70% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.22% 99.92% # number of callpals executed +system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3533 2.09% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::swpipl 153850 90.93% 93.22% # number of callpals executed +system.cpu0.kern.callpal::rdps 6345 3.75% 96.97% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::rti 4587 2.71% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 172559 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7164 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches +system.cpu0.kern.callpal::total 169199 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7137 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1347 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1342 -system.cpu0.kern.mode_good::user 1343 +system.cpu0.kern.mode_good::kernel 1346 +system.cpu0.kern.mode_good::user 1347 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.187326 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188595 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.315622 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904989354500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1966585000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.317421 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1919561135500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2201673000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3604 # number of times the context was actually changed +system.cpu0.kern.swap_context 3534 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2444 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 51472 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 15731 36.02% 36.02% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 4.41% 40.43% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 249 0.57% 41.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 25763 59.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 43668 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 15435 47.07% 47.07% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.87% 52.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 249 0.76% 53.69% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15186 46.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 32795 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874760769500 98.33% 98.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 538410500 0.03% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 114320500 0.01% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31218212000 1.64% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1906631712500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981184 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 55164 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 17245 36.53% 36.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 4.08% 40.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 27750 58.79% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 47204 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16874 47.30% 47.30% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.40% 52.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 284 0.80% 53.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16590 46.51% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 35673 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874997277000 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 538569500 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 135298500 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45735704500 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1921406849500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978487 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.589450 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.751008 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed -system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed -system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 101 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.597838 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.755720 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed +system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed +system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 98 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 149 0.33% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 911 2.02% 2.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.36% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 2.38% # number of callpals executed -system.cpu1.kern.callpal::swpipl 38628 85.51% 87.88% # number of callpals executed -system.cpu1.kern.callpal::rdps 2426 5.37% 93.25% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2865 6.34% 99.61% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.29% 99.90% # number of callpals executed +system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1056 2.16% 2.55% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed +system.cpu1.kern.callpal::swpipl 42024 86.04% 88.61% # number of callpals executed +system.cpu1.kern.callpal::rdps 2414 4.94% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.56% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::rti 2970 6.08% 99.65% # number of callpals executed +system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 45176 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1151 # number of protection mode switches -system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2341 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 568 -system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 173 -system.cpu1.kern.mode_switch_good::kernel 0.493484 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 48843 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1253 # number of protection mode switches +system.cpu1.kern.mode_switch::user 392 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2414 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 600 +system.cpu1.kern.mode_good::user 392 +system.cpu1.kern.mode_good::idle 208 +system.cpu1.kern.mode_switch_good::kernel 0.478851 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.073900 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.292256 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3648998000 0.19% 0.19% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 689386500 0.04% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1901995153000 99.77% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 912 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.086164 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.295639 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4354098000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 702561000 0.04% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1916032066000 99.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1057 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 275b5ad07..3a598fe00 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860990 # Number of seconds simulated -sim_ticks 1860990273000 # Number of ticks simulated -final_tick 1860990273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.875745 # Number of seconds simulated +sim_ticks 1875745192000 # Number of ticks simulated +final_tick 1875745192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102674 # Simulator instruction rate (inst/s) -host_op_rate 102674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3606509618 # Simulator tick rate (ticks/s) -host_mem_usage 370916 # Number of bytes of host memory used -host_seconds 516.01 # Real time elapsed on the host -sim_insts 52980740 # Number of instructions simulated -sim_ops 52980740 # Number of ops (including micro ops) simulated +host_inst_rate 131976 # Simulator instruction rate (inst/s) +host_op_rate 131976 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4672432142 # Simulator tick rate (ticks/s) +host_mem_usage 378172 # Number of bytes of host memory used +host_seconds 401.45 # Real time elapsed on the host +sim_insts 52981683 # Number of instructions simulated +sim_ops 52981683 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 964096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 962112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881536 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25845056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7523456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7523456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25844608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 962112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 962112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7523648 # Number of bytes written to this memory +system.physmem.bytes_written::total 7523648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388774 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403829 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117554 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13369226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13887797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4042716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4042716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4042716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13369226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17930514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403829 # Number of read requests accepted -system.physmem.writeReqs 117554 # Number of write requests accepted -system.physmem.readBursts 403829 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117554 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25837696 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7522048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25845056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7523456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 403822 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 512923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13264881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13778315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512923 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512923 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4011018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4011018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4011018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13264881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17789333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403822 # Number of read requests accepted +system.physmem.writeReqs 117557 # Number of write requests accepted +system.physmem.readBursts 403822 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117557 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25836864 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue +system.physmem.bytesWritten 7522176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25844608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7523648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25640 # Per bank write bursts -system.physmem.perBankRdBursts::1 25420 # Per bank write bursts -system.physmem.perBankRdBursts::2 25567 # Per bank write bursts -system.physmem.perBankRdBursts::3 25490 # Per bank write bursts -system.physmem.perBankRdBursts::4 25392 # Per bank write bursts -system.physmem.perBankRdBursts::5 24736 # Per bank write bursts -system.physmem.perBankRdBursts::6 24946 # Per bank write bursts -system.physmem.perBankRdBursts::7 25069 # Per bank write bursts -system.physmem.perBankRdBursts::8 24934 # Per bank write bursts -system.physmem.perBankRdBursts::9 25024 # Per bank write bursts -system.physmem.perBankRdBursts::10 25571 # Per bank write bursts -system.physmem.perBankRdBursts::11 24874 # Per bank write bursts -system.physmem.perBankRdBursts::12 24488 # Per bank write bursts -system.physmem.perBankRdBursts::13 25240 # Per bank write bursts -system.physmem.perBankRdBursts::14 25741 # Per bank write bursts -system.physmem.perBankRdBursts::15 25582 # Per bank write bursts -system.physmem.perBankWrBursts::0 7942 # Per bank write bursts +system.physmem.perBankRdBursts::0 25633 # Per bank write bursts +system.physmem.perBankRdBursts::1 25421 # Per bank write bursts +system.physmem.perBankRdBursts::2 25565 # Per bank write bursts +system.physmem.perBankRdBursts::3 25492 # Per bank write bursts +system.physmem.perBankRdBursts::4 25387 # Per bank write bursts +system.physmem.perBankRdBursts::5 24737 # Per bank write bursts +system.physmem.perBankRdBursts::6 24937 # Per bank write bursts +system.physmem.perBankRdBursts::7 25080 # Per bank write bursts +system.physmem.perBankRdBursts::8 24933 # Per bank write bursts +system.physmem.perBankRdBursts::9 25019 # Per bank write bursts +system.physmem.perBankRdBursts::10 25561 # Per bank write bursts +system.physmem.perBankRdBursts::11 24878 # Per bank write bursts +system.physmem.perBankRdBursts::12 24487 # Per bank write bursts +system.physmem.perBankRdBursts::13 25242 # Per bank write bursts +system.physmem.perBankRdBursts::14 25745 # Per bank write bursts +system.physmem.perBankRdBursts::15 25584 # Per bank write bursts +system.physmem.perBankWrBursts::0 7946 # Per bank write bursts system.physmem.perBankWrBursts::1 7515 # Per bank write bursts -system.physmem.perBankWrBursts::2 7958 # Per bank write bursts -system.physmem.perBankWrBursts::3 7515 # Per bank write bursts -system.physmem.perBankWrBursts::4 7335 # Per bank write bursts -system.physmem.perBankWrBursts::5 6671 # Per bank write bursts -system.physmem.perBankWrBursts::6 6772 # Per bank write bursts -system.physmem.perBankWrBursts::7 6705 # Per bank write bursts -system.physmem.perBankWrBursts::8 7147 # Per bank write bursts -system.physmem.perBankWrBursts::9 6708 # Per bank write bursts -system.physmem.perBankWrBursts::10 7414 # Per bank write bursts -system.physmem.perBankWrBursts::11 6974 # Per bank write bursts +system.physmem.perBankWrBursts::2 7960 # Per bank write bursts +system.physmem.perBankWrBursts::3 7517 # Per bank write bursts +system.physmem.perBankWrBursts::4 7330 # Per bank write bursts +system.physmem.perBankWrBursts::5 6676 # Per bank write bursts +system.physmem.perBankWrBursts::6 6762 # Per bank write bursts +system.physmem.perBankWrBursts::7 6719 # Per bank write bursts +system.physmem.perBankWrBursts::8 7146 # Per bank write bursts +system.physmem.perBankWrBursts::9 6702 # Per bank write bursts +system.physmem.perBankWrBursts::10 7407 # Per bank write bursts +system.physmem.perBankWrBursts::11 6970 # Per bank write bursts system.physmem.perBankWrBursts::12 7148 # Per bank write bursts -system.physmem.perBankWrBursts::13 7857 # Per bank write bursts -system.physmem.perBankWrBursts::14 8057 # Per bank write bursts +system.physmem.perBankWrBursts::13 7861 # Per bank write bursts +system.physmem.perBankWrBursts::14 8061 # Per bank write bursts system.physmem.perBankWrBursts::15 7814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 22 # Number of times write queue was full causing retry -system.physmem.totGap 1860985018500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 1875739913500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403829 # Read request sizes (log2) +system.physmem.readPktSize::6 403822 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117554 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117557 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -148,202 +148,197 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61694 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 540.722923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.893410 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.338201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13637 22.10% 22.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10472 16.97% 39.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4852 7.86% 46.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3164 5.13% 52.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2278 3.69% 55.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1550 2.51% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1469 2.38% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1300 2.11% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22972 37.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61694 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5210 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.486564 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2926.418549 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5207 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.822002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.292900 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 411.615573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13686 22.02% 22.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10474 16.86% 38.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4974 8.00% 46.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2759 4.44% 51.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2428 3.91% 55.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1656 2.66% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3743 6.02% 63.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1149 1.85% 65.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21272 34.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62141 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.350259 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2906.647984 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5216 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5210 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5210 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.558925 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.942347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.343325 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4470 85.80% 85.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 144 2.76% 88.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 197 3.78% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 15 0.29% 92.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 22 0.42% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 47 0.90% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 16 0.31% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.02% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 3 0.06% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.12% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.10% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 4 0.08% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.06% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.19% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 6 0.12% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 10 0.19% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 18 0.35% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 17 0.33% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 156 2.99% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 8 0.15% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.13% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.06% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.06% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.04% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 4 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 11 0.21% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5210 # Writes before turning the bus around for reads -system.physmem.totQLat 3803541750 # Total ticks spent queuing -system.physmem.totMemAccLat 11373179250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9421.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5219 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5219 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.520406 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.103659 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.296995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4441 85.09% 85.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 172 3.30% 88.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 18 0.34% 88.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 180 3.45% 92.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.08% 92.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.40% 92.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 36 0.69% 93.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.04% 93.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.23% 93.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 25 0.48% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.08% 94.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 11 0.21% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.08% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.38% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.56% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 29 0.56% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 164 3.14% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.06% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.11% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.08% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.08% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 11 0.21% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5219 # Writes before turning the bus around for reads +system.physmem.totQLat 4201414500 # Total ticks spent queuing +system.physmem.totMemAccLat 11770808250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018505000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10407.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28171.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29157.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing -system.physmem.readRowHits 364213 # Number of row buffer hits during reads -system.physmem.writeRowHits 95338 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes -system.physmem.avgGap 3569324.31 # Average gap between requests -system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 231343560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126229125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577628000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378516240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56189479095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1067301426750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1247355039810 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.266370 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1775383293000 # Time in different power states -system.physmem_0.memoryStateTime::REF 62142340000 # Time in different power states +system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing +system.physmem.readRowHits 363834 # Number of row buffer hits during reads +system.physmem.writeRowHits 95259 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.03 # Row buffer hit rate for writes +system.physmem.avgGap 3597651.45 # Average gap between requests +system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 233286480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127289250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577565600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378594000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61659983700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1071355704750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1257846562020 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.587193 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1782093997750 # Time in different power states +system.physmem_0.memoryStateTime::REF 62635040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23458453250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31009992250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 235063080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128258625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571294400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383091120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 55921872645 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1067536177500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1247326174410 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.250855 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1775778508500 # Time in different power states -system.physmem_1.memoryStateTime::REF 62142340000 # Time in different power states +system.physmem_1.actEnergy 236499480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129042375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571255400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383026320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61488464715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1071506168250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1257828594780 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.577609 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1782344410500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62635040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23063881500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30760024500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17952495 # Number of BP lookups -system.cpu.branchPred.condPredicted 15650737 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 369298 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11540660 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5852648 # Number of BTB hits +system.cpu.branchPred.lookups 17977610 # Number of BP lookups +system.cpu.branchPred.condPredicted 15676073 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 370677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11479744 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5859077 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.713287 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 911814 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21176 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 51.038394 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 912903 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21206 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10266725 # DTB read hits -system.cpu.dtb.read_misses 41420 # DTB read misses -system.cpu.dtb.read_acv 529 # DTB read access violations -system.cpu.dtb.read_accesses 965767 # DTB read accesses -system.cpu.dtb.write_hits 6642195 # DTB write hits -system.cpu.dtb.write_misses 9809 # DTB write misses -system.cpu.dtb.write_acv 405 # DTB write access violations -system.cpu.dtb.write_accesses 342270 # DTB write accesses -system.cpu.dtb.data_hits 16908920 # DTB hits -system.cpu.dtb.data_misses 51229 # DTB misses -system.cpu.dtb.data_acv 934 # DTB access violations -system.cpu.dtb.data_accesses 1308037 # DTB accesses -system.cpu.itb.fetch_hits 1768997 # ITB hits -system.cpu.itb.fetch_misses 27603 # ITB misses +system.cpu.dtb.read_hits 10250294 # DTB read hits +system.cpu.dtb.read_misses 41452 # DTB read misses +system.cpu.dtb.read_acv 531 # DTB read access violations +system.cpu.dtb.read_accesses 965916 # DTB read accesses +system.cpu.dtb.write_hits 6642949 # DTB write hits +system.cpu.dtb.write_misses 9723 # DTB write misses +system.cpu.dtb.write_acv 398 # DTB write access violations +system.cpu.dtb.write_accesses 342082 # DTB write accesses +system.cpu.dtb.data_hits 16893243 # DTB hits +system.cpu.dtb.data_misses 51175 # DTB misses +system.cpu.dtb.data_acv 929 # DTB access violations +system.cpu.dtb.data_accesses 1307998 # DTB accesses +system.cpu.itb.fetch_hits 1771116 # ITB hits +system.cpu.itb.fetch_misses 27251 # ITB misses system.cpu.itb.fetch_acv 655 # ITB acv -system.cpu.itb.fetch_accesses 1796600 # ITB accesses +system.cpu.itb.fetch_accesses 1798367 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -356,692 +351,692 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122250725 # number of cpu cycles simulated +system.cpu.numCycles 153807945 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29590872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78035312 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17952495 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6764462 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 84736015 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1230846 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3604 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1246103 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 463506 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 270 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8988072 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271207 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 116683770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.668776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.983888 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29589963 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78082078 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17977610 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6771980 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115315004 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1233982 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2306 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 29550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1247451 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 470617 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 460 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8997640 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 271780 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 147272342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.530188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.786973 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102162821 87.56% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 926771 0.79% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1955000 1.68% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 905545 0.78% 90.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2771139 2.37% 93.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 614884 0.53% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 724459 0.62% 94.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009032 0.86% 95.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5614119 4.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132738967 90.13% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 930397 0.63% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1956016 1.33% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 907001 0.62% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772714 1.88% 94.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 615474 0.42% 95.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 727209 0.49% 95.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009346 0.69% 96.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5615218 3.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116683770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.146850 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.638322 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24065548 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80700938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9436968 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1906955 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 573360 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 582340 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42404 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68029803 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 132508 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 573360 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24987085 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50897393 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20868454 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10337136 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9020340 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65614260 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 203152 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2087104 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 150571 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4833262 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43733220 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79561709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79380946 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168313 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180223 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5552989 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1689330 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239361 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13544094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10376074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6949198 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1492318 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1087072 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58452380 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2137932 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57496742 # Number of instructions issued +system.cpu.fetch.rateDist::total 147272342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116883 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.507660 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24002291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 111345789 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9440793 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1908530 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 574938 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 581140 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42414 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68062016 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 132549 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 574938 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24926396 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78168566 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21593766 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10339140 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11669534 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65637228 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204564 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2092706 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 229144 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7400964 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43743792 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79597549 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79416724 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168373 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38181235 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5562549 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1689699 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239435 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13568621 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10378795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6951631 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1513940 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1098335 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58473138 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2139162 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57493462 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7609567 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3401604 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1476871 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116683770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.492757 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.231576 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 7630612 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3411321 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1477941 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147272342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.390389 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.114131 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93080109 79.77% 79.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10182698 8.73% 88.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4288903 3.68% 92.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3018996 2.59% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3082938 2.64% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1488362 1.28% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1011835 0.87% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 404754 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125175 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 123663895 83.97% 83.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10186331 6.92% 90.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4292878 2.91% 93.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3019293 2.05% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3081041 2.09% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1488323 1.01% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011420 0.69% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404091 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125070 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116683770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147272342 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 209669 18.63% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 542046 48.17% 66.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 373622 33.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210189 18.68% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 539111 47.92% 66.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375615 33.39% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39037181 67.89% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61834 0.11% 68.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38554 0.07% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10676723 18.57% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722717 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948811 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39049173 67.92% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61879 0.11% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10660314 18.54% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6723536 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949085 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57496742 # Type of FU issued -system.cpu.iq.rate 0.470318 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1125337 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 232146820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67882277 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55834928 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712827 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336508 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328971 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58232105 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382688 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 634703 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57493462 # Type of FU issued +system.cpu.iq.rate 0.373800 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1124915 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019566 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262728196 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67925320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55850502 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 713041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336604 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329051 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58228243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382848 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 635438 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1283936 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3373 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19308 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 571381 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1285740 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3115 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19427 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 573353 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18194 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 477327 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18203 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 457581 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 573360 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 47668673 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 853294 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64278853 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 140556 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10376074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6949198 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890343 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43583 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 606693 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19308 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 178271 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409117 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 587388 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56911436 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10335818 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 585305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 574938 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 74485816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1122121 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64302959 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140159 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10378795 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6951631 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1891041 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 44126 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 874685 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19427 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 179710 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409314 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 589024 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56907888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10319427 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 585573 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3688541 # number of nop insts executed -system.cpu.iew.exec_refs 17002933 # number of memory reference insts executed -system.cpu.iew.exec_branches 8971597 # Number of branches executed -system.cpu.iew.exec_stores 6667115 # Number of stores executed -system.cpu.iew.exec_rate 0.465530 # Inst execution rate -system.cpu.iew.wb_sent 56299831 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56163899 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28741573 # num instructions producing a value -system.cpu.iew.wb_consumers 39917507 # num instructions consuming a value +system.cpu.iew.exec_nop 3690659 # number of nop insts executed +system.cpu.iew.exec_refs 16987198 # number of memory reference insts executed +system.cpu.iew.exec_branches 8973802 # Number of branches executed +system.cpu.iew.exec_stores 6667771 # Number of stores executed +system.cpu.iew.exec_rate 0.369993 # Inst execution rate +system.cpu.iew.wb_sent 56315493 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56179553 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28757989 # num instructions producing a value +system.cpu.iew.wb_consumers 39945326 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.459416 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.720024 # average fanout of values written-back +system.cpu.iew.wb_rate 0.365258 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7990103 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661061 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 538190 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 115283305 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.430050 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8014233 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661221 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 539644 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 145865842 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.385097 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.287358 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95489644 82.83% 82.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7861367 6.82% 89.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4279666 3.71% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238986 1.94% 95.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1753667 1.52% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 610357 0.53% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475106 0.41% 97.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 479497 0.42% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2095015 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 126089885 86.44% 86.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7851403 5.38% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4272179 2.93% 94.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235192 1.53% 96.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1747101 1.20% 97.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615790 0.42% 97.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475839 0.33% 98.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 478833 0.33% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2099620 1.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 115283305 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56171345 # Number of instructions committed -system.cpu.commit.committedOps 56171345 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 145865842 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56172516 # Number of instructions committed +system.cpu.commit.committedOps 56172516 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15469955 # Number of memory references committed -system.cpu.commit.loads 9092138 # Number of loads committed -system.cpu.commit.membars 226307 # Number of memory barriers committed -system.cpu.commit.branches 8441356 # Number of branches committed +system.cpu.commit.refs 15471333 # Number of memory references committed +system.cpu.commit.loads 9093055 # Number of loads committed +system.cpu.commit.membars 226352 # Number of memory barriers committed +system.cpu.commit.branches 8440752 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52021098 # Number of committed integer instructions. -system.cpu.commit.function_calls 740502 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197878 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36220066 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60657 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52021823 # Number of committed integer instructions. +system.cpu.commit.function_calls 740586 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198106 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36219281 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60683 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9318445 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383767 11.36% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948811 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # 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The number of ROB writes -system.cpu.timesIdled 575678 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5566955 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599729822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52980740 # Number of Instructions Simulated -system.cpu.committedOps 52980740 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.307456 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.307456 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433378 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433378 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74560962 # number of integer regfile reads -system.cpu.int_regfile_writes 40515010 # number of integer regfile writes -system.cpu.fp_regfile_reads 167029 # number of floating regfile reads -system.cpu.fp_regfile_writes 167528 # number of floating regfile writes -system.cpu.misc_regfile_reads 2030483 # number of misc regfile reads -system.cpu.misc_regfile_writes 939256 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1402429 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994497 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11825966 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1402941 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.429411 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 26175500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994497 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 56172516 # Class of committed instruction +system.cpu.commit.bw_lim_events 2099620 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 207703277 # The number of ROB reads +system.cpu.rob.rob_writes 129775597 # The number of ROB writes +system.cpu.timesIdled 576321 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6535603 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3597682440 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52981683 # Number of Instructions Simulated +system.cpu.committedOps 52981683 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.903040 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.903040 # CPI: Total CPI of All Threads +system.cpu.ipc 0.344466 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.344466 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74566924 # number of integer regfile reads +system.cpu.int_regfile_writes 40527176 # number of integer regfile writes +system.cpu.fp_regfile_reads 167101 # number of floating regfile reads +system.cpu.fp_regfile_writes 167535 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985778 # number of misc regfile reads +system.cpu.misc_regfile_writes 939467 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1402095 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.992786 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11832212 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1402607 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.435871 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.992786 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63836458 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63836458 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7233922 # 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number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1957536 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1957536 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23327 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3759455 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3759455 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3759455 # number of overall misses -system.cpu.dcache.overall_misses::total 3759455 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41733061500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41733061500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80455809465 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80455809465 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376093000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 376093000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 485000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 485000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 122188870965 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 122188870965 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 122188870965 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 122188870965 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9035841 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116967363039 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116967363039 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 446591500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 446591500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 850000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 850000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 174166078539 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 174166078539 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 174166078539 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 174166078539 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9038267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9038267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147815 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147815 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209494 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209494 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215760 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215760 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15186082 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15186082 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15186082 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15186082 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318391 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318391 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247345 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247345 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247345 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247345 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31798.404429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31798.404429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59756.189577 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59756.189577 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19142.370339 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19142.370339 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 32692.307692 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 32692.307692 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46367.601779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46367.601779 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7156530 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5457 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133923 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437647 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 188.172414 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841625 # 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average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16321.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16321.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209344.588745 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209344.588745 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212141.517090 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44554526500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 44554526500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18468782348 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18468782348 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 228783500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 228783500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 824000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 824000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63023308848 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63023308848 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63023308848 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63023308848 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450570000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450570000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2036143500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2036143500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486713500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486713500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121042 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121042 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047295 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047295 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086141 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086141 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091187 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091187 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40725.885961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40725.885961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63518.774347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63518.774347 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12677.795633 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12677.795633 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 31692.307692 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 31692.307692 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209317.460317 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209317.460317 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.477599 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.477599 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210957.980397 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210957.980397 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 7904301 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1039458 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.604252 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42289841500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 507.834309 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.991864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.991864 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10027494 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10027494 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7895322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7895322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7895322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7895322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7895322 # number of overall hits -system.cpu.icache.overall_hits::total 7895322 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1092746 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1092746 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1092746 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1092746 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1092746 # number of overall misses -system.cpu.icache.overall_misses::total 1092746 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15273300993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15273300993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15273300993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15273300993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15273300993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15273300993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8988068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8988068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8988068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8988068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8988068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8988068 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121577 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121577 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121577 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121577 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121577 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121577 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13976.990987 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13976.990987 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6859 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10037466 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10037466 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7904302 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7904302 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7904302 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7904302 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16294267486 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16294267486 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8997638 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8997638 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8997638 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8997638 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8997638 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8997638 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121514 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3483 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3330 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55446 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39757210 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39757210 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 841276 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 841276 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 30 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 19 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 19 # 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mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248597 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165595 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165595 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.765625 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.765625 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.269231 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.269231 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383087 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383087 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014463 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248696 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248696 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165588 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71653.061224 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71653.061224 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71357.142857 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71357.142857 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129665.581633 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129665.581633 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124292.536916 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124292.536916 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114199.793686 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114199.793686 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196817.460317 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196817.460317 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.977079 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.977079 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199037.239835 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199037.239835 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4883718 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2441508 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2147969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 959201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1860011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 127 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 155 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101712 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 82 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2147995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 958852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1860290 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 154 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039828 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3116681 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7357295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66503296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143706404 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210209700 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422216 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5321857 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.079248 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270126 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3117755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4239617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7357372 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66528832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143662708 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210191540 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422209 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5321984 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032932 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4900109 92.08% 92.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 421748 7.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5316206 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5778 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5321857 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3296477500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5321984 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3296198000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1560615042 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1561216545 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2116394230 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2115809899 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1200,9 +1201,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51148 # Transaction distribution -system.iobus.trans_dist::WriteResp 51148 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5048 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51150 # Transaction distribution +system.iobus.trans_dist::WriteResp 51150 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1214,11 +1215,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116502 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1230,11 +1231,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44132 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705740 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4659000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1256,23 +1257,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216075504 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215079498 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23456000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.259061 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.249403 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711310965000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.259061 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078691 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078691 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1725991887000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.249403 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078088 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078088 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1286,14 +1287,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908771621 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4908771621 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21903883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21903883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427983615 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427983615 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21903883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21903883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21903883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21903883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1310,19 +1311,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118135.628153 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126612.040462 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126612.040462 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.103557 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130631.103557 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126612.040462 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126612.040462 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1336,14 +1337,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831171621 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2831171621 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13253883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13253883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350383615 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350383615 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13253883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13253883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13253883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13253883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1352,64 +1353,64 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76612.040462 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.103557 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.103557 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295925 # Transaction distribution -system.membus.trans_dist::WriteReq 9596 # Transaction distribution -system.membus.trans_dist::WriteResp 9596 # Transaction distribution -system.membus.trans_dist::Writeback 117554 # Transaction distribution -system.membus.trans_dist::CleanEvict 261799 # Transaction distribution -system.membus.trans_dist::UpgradeReq 335 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::ReadResp 295909 # Transaction distribution +system.membus.trans_dist::WriteReq 9598 # Transaction distribution +system.membus.trans_dist::WriteResp 9598 # Transaction distribution +system.membus.trans_dist::Writeback 117557 # Transaction distribution +system.membus.trans_dist::CleanEvict 261789 # Transaction distribution +system.membus.trans_dist::UpgradeReq 334 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution system.membus.trans_dist::UpgradeResp 341 # Transaction distribution -system.membus.trans_dist::ReadExReq 115266 # Transaction distribution -system.membus.trans_dist::ReadExResp 115266 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289077 # Transaction distribution -system.membus.trans_dist::BadAddressError 82 # Transaction distribution +system.membus.trans_dist::ReadExReq 115275 # Transaction distribution +system.membus.trans_dist::ReadExResp 115275 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289062 # Transaction distribution +system.membus.trans_dist::BadAddressError 83 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33052 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146409 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 164 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179625 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146388 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179610 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1304442 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754916 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1304427 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754676 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33412644 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33412404 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842297 # Request fanout histogram +system.membus.snoop_fanout::samples 842283 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842297 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842283 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842297 # Request fanout histogram -system.membus.reqLayer0.occupancy 28891000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842283 # Request fanout histogram +system.membus.reqLayer0.occupancy 28662500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313747676 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313672631 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 109000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 106500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139659662 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139416664 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69895667 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1443,28 +1444,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210955 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74645 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74668 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105533 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182187 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73278 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182251 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73301 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73278 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148565 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817526707500 97.66% 97.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62603000 0.00% 97.67% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 536431500 0.03% 97.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42863705000 2.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860989447000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981687 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73301 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148613 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818203066500 96.93% 96.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62700500 0.00% 96.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 538036000 0.03% 96.96% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 56940563000 3.04% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1875744366000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694361 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815453 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815430 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1503,29 +1504,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175074 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175134 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191916 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.callpal::total 191979 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1909 system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326325 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29189899500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2667621500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1829131918000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29901576500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2896080000 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842946701500 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 296ab434c..8f58e32e6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841535 # Number of seconds simulated -sim_ticks 1841535479500 # Number of ticks simulated -final_tick 1841535479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841615 # Number of seconds simulated +sim_ticks 1841615117500 # Number of ticks simulated +final_tick 1841615117500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156573 # Simulator instruction rate (inst/s) -host_op_rate 156573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3970842510 # Simulator tick rate (ticks/s) -host_mem_usage 369896 # Number of bytes of host memory used -host_seconds 463.76 # Real time elapsed on the host -sim_insts 72613172 # Number of instructions simulated -sim_ops 72613172 # Number of ops (including micro ops) simulated +host_inst_rate 220643 # Simulator instruction rate (inst/s) +host_op_rate 220643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5550131764 # Simulator tick rate (ticks/s) +host_mem_usage 377148 # Number of bytes of host memory used +host_seconds 331.81 # Real time elapsed on the host +sim_insts 73212541 # Number of instructions simulated +sim_ops 73212541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 466112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20058112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2156288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 305728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2656832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 495296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20794752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 141504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1560960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 279936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2513472 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25791040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 466112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 305728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7482432 # Number of bytes written to this memory -system.physmem.bytes_written::total 7482432 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7283 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33692 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41513 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25786880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 495296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 141504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 279936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 916736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7468864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7468864 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 324918 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24390 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4374 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39273 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402985 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116913 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116913 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 253111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10892058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1170919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 166018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1442726 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402920 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 268947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 11291584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 847604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 152006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1364819 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14005182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 253111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 166018 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4063148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4063148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4063148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 253111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10892058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1170919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 166018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1442726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14002318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 268947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 152006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 497789 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4055605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4055605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4055605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 268947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 11291584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 847604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 152006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1364819 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18068331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 82294 # Number of read requests accepted -system.physmem.writeReqs 47398 # Number of write requests accepted -system.physmem.readBursts 82294 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 47398 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5265472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue -system.physmem.bytesWritten 3032512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5266816 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3033472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 18057923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 70263 # Number of read requests accepted +system.physmem.writeReqs 43985 # Number of write requests accepted +system.physmem.readBursts 70263 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 43985 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 4495872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue +system.physmem.bytesWritten 2813888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 4496832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2815040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 17325 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5126 # Per bank write bursts -system.physmem.perBankRdBursts::1 5048 # Per bank write bursts -system.physmem.perBankRdBursts::2 4814 # Per bank write bursts -system.physmem.perBankRdBursts::3 4971 # Per bank write bursts -system.physmem.perBankRdBursts::4 5248 # Per bank write bursts -system.physmem.perBankRdBursts::5 5169 # Per bank write bursts -system.physmem.perBankRdBursts::6 5184 # Per bank write bursts -system.physmem.perBankRdBursts::7 5149 # Per bank write bursts -system.physmem.perBankRdBursts::8 5417 # Per bank write bursts -system.physmem.perBankRdBursts::9 4756 # Per bank write bursts -system.physmem.perBankRdBursts::10 5535 # Per bank write bursts -system.physmem.perBankRdBursts::11 5117 # Per bank write bursts -system.physmem.perBankRdBursts::12 4885 # Per bank write bursts -system.physmem.perBankRdBursts::13 5047 # Per bank write bursts -system.physmem.perBankRdBursts::14 5632 # Per bank write bursts -system.physmem.perBankRdBursts::15 5175 # Per bank write bursts -system.physmem.perBankWrBursts::0 2819 # Per bank write bursts -system.physmem.perBankWrBursts::1 2870 # Per bank write bursts -system.physmem.perBankWrBursts::2 2836 # Per bank write bursts -system.physmem.perBankWrBursts::3 2977 # Per bank write bursts -system.physmem.perBankWrBursts::4 3104 # Per bank write bursts -system.physmem.perBankWrBursts::5 2797 # Per bank write bursts -system.physmem.perBankWrBursts::6 3160 # Per bank write bursts -system.physmem.perBankWrBursts::7 2831 # Per bank write bursts -system.physmem.perBankWrBursts::8 3459 # Per bank write bursts -system.physmem.perBankWrBursts::9 2567 # Per bank write bursts -system.physmem.perBankWrBursts::10 3319 # Per bank write bursts -system.physmem.perBankWrBursts::11 2907 # Per bank write bursts -system.physmem.perBankWrBursts::12 2644 # Per bank write bursts -system.physmem.perBankWrBursts::13 2801 # Per bank write bursts -system.physmem.perBankWrBursts::14 3392 # Per bank write bursts -system.physmem.perBankWrBursts::15 2900 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 17213 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4359 # Per bank write bursts +system.physmem.perBankRdBursts::1 4121 # Per bank write bursts +system.physmem.perBankRdBursts::2 4307 # Per bank write bursts +system.physmem.perBankRdBursts::3 4650 # Per bank write bursts +system.physmem.perBankRdBursts::4 3946 # Per bank write bursts +system.physmem.perBankRdBursts::5 4779 # Per bank write bursts +system.physmem.perBankRdBursts::6 4258 # Per bank write bursts +system.physmem.perBankRdBursts::7 4152 # Per bank write bursts +system.physmem.perBankRdBursts::8 4721 # Per bank write bursts +system.physmem.perBankRdBursts::9 4422 # Per bank write bursts +system.physmem.perBankRdBursts::10 4675 # Per bank write bursts +system.physmem.perBankRdBursts::11 4103 # Per bank write bursts +system.physmem.perBankRdBursts::12 4083 # Per bank write bursts +system.physmem.perBankRdBursts::13 4580 # Per bank write bursts +system.physmem.perBankRdBursts::14 4738 # Per bank write bursts +system.physmem.perBankRdBursts::15 4354 # Per bank write bursts +system.physmem.perBankWrBursts::0 2794 # Per bank write bursts +system.physmem.perBankWrBursts::1 2415 # Per bank write bursts +system.physmem.perBankWrBursts::2 2758 # Per bank write bursts +system.physmem.perBankWrBursts::3 3153 # Per bank write bursts +system.physmem.perBankWrBursts::4 2458 # Per bank write bursts +system.physmem.perBankWrBursts::5 2922 # Per bank write bursts +system.physmem.perBankWrBursts::6 2626 # Per bank write bursts +system.physmem.perBankWrBursts::7 2424 # Per bank write bursts +system.physmem.perBankWrBursts::8 3273 # Per bank write bursts +system.physmem.perBankWrBursts::9 2590 # Per bank write bursts +system.physmem.perBankWrBursts::10 2930 # Per bank write bursts +system.physmem.perBankWrBursts::11 2458 # Per bank write bursts +system.physmem.perBankWrBursts::12 2433 # Per bank write bursts +system.physmem.perBankWrBursts::13 2833 # Per bank write bursts +system.physmem.perBankWrBursts::14 3042 # Per bank write bursts +system.physmem.perBankWrBursts::15 2858 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1840523607000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 1840603135000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 82294 # Read request sizes (log2) +system.physmem.readPktSize::6 70263 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 47398 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 64239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 43985 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 50096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -153,202 +153,195 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.991001 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.949703 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 378.684450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7216 33.13% 33.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4887 22.44% 55.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1962 9.01% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1034 4.75% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 848 3.89% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 523 2.40% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 452 2.08% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 368 1.69% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4490 20.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21780 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 39.592397 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 979.363215 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2076 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1682 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 1911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.690812 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.028180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 371.433574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7252 35.78% 35.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4628 22.84% 58.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1637 8.08% 66.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 935 4.61% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 704 3.47% 74.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 532 2.63% 77.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 447 2.21% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 402 1.98% 81.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3729 18.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20266 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1889 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.186342 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 837.829732 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1887 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2078 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.802214 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.584158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.825875 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 29 1.40% 1.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.29% 1.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 1.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 6 0.29% 2.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1724 82.96% 84.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 39 1.88% 86.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 91 4.38% 91.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 19 0.91% 92.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 9 0.43% 92.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 19 0.91% 93.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 4 0.19% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.10% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.14% 93.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.05% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 2 0.10% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.14% 94.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.14% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.19% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 8 0.38% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.19% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 76 3.66% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.29% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.10% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.05% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.14% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.10% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.05% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.10% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2078 # Writes before turning the bus around for reads -system.physmem.totQLat 922774500 # Total ticks spent queuing -system.physmem.totMemAccLat 2465393250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 411365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11216.01 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 1889 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.275278 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.746797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.833114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.80% 1.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.48% 2.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.11% 2.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.11% 2.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1521 80.52% 83.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 51 2.70% 85.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 9 0.48% 86.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 92 4.87% 91.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.11% 91.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 5 0.26% 91.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.90% 92.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.64% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.42% 93.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.05% 93.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.11% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.16% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.11% 93.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.21% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.53% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 16 0.85% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 73 3.86% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 6 0.32% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1889 # Writes before turning the bus around for reads +system.physmem.totQLat 866118250 # Total ticks spent queuing +system.physmem.totMemAccLat 2183268250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 351240000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12329.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29966.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.86 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31079.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 16.09 # Average write queue length when enqueuing -system.physmem.readRowHits 70442 # Number of row buffer hits during reads -system.physmem.writeRowHits 37434 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.98 # Row buffer hit rate for writes -system.physmem.avgGap 14191496.83 # Average gap between requests -system.physmem.pageHitRate 83.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 81065880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 44121000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 317530200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 151593120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35745647625 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 800947233750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 926343167415 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.792687 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1308857547000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.98 # Average write queue length when enqueuing +system.physmem.readRowHits 59265 # Number of row buffer hits during reads +system.physmem.writeRowHits 34684 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.85 # Row buffer hit rate for writes +system.physmem.avgGap 16110593.93 # Average gap between requests +system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75993120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 41365500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 269661600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 139644000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 36119290320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 800836482750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 926543498730 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.762999 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1308404512000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45532240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9287627500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9805597500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 83590920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 45449250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 324199200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 155448720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35447161140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 801537520500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 926649345570 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.749891 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1309278655250 # Time in different power states -system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states +system.physmem_1.actEnergy 77217840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41955375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 278272800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 145262160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35704397295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 801349556250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 926657723160 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.725709 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1308993682000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45532240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8857363000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9217388750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4774172 # DTB read hits -system.cpu0.dtb.read_misses 5959 # DTB read misses -system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 427834 # DTB read accesses -system.cpu0.dtb.write_hits 3388527 # DTB write hits -system.cpu0.dtb.write_misses 664 # DTB write misses -system.cpu0.dtb.write_acv 80 # DTB write access violations -system.cpu0.dtb.write_accesses 164366 # DTB write accesses -system.cpu0.dtb.data_hits 8162699 # DTB hits -system.cpu0.dtb.data_misses 6623 # DTB misses -system.cpu0.dtb.data_acv 189 # DTB access violations -system.cpu0.dtb.data_accesses 592200 # DTB accesses -system.cpu0.itb.fetch_hits 2715643 # ITB hits -system.cpu0.itb.fetch_misses 3015 # ITB misses -system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2718658 # ITB accesses +system.cpu0.dtb.read_hits 4860395 # DTB read hits +system.cpu0.dtb.read_misses 6162 # DTB read misses +system.cpu0.dtb.read_acv 126 # DTB read access violations +system.cpu0.dtb.read_accesses 428546 # DTB read accesses +system.cpu0.dtb.write_hits 3431856 # DTB write hits +system.cpu0.dtb.write_misses 685 # DTB write misses +system.cpu0.dtb.write_acv 84 # DTB write access violations +system.cpu0.dtb.write_accesses 164529 # DTB write accesses +system.cpu0.dtb.data_hits 8292251 # DTB hits +system.cpu0.dtb.data_misses 6847 # DTB misses +system.cpu0.dtb.data_acv 210 # DTB access violations +system.cpu0.dtb.data_accesses 593075 # DTB accesses +system.cpu0.itb.fetch_hits 2736971 # ITB hits +system.cpu0.itb.fetch_misses 3081 # ITB misses +system.cpu0.itb.fetch_acv 104 # ITB acv +system.cpu0.itb.fetch_accesses 2740052 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -361,87 +354,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928469977 # number of cpu cycles simulated +system.cpu0.numCycles 927057463 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30414467 # Number of instructions committed -system.cpu0.committedOps 30414467 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28351523 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 162419 # Number of float alu accesses -system.cpu0.num_func_calls 792250 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3751370 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28351523 # number of integer instructions -system.cpu0.num_fp_insts 162419 # number of float instructions -system.cpu0.num_int_register_reads 39201854 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20853832 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84043 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 85470 # number of times the floating registers were written -system.cpu0.num_mem_refs 8191763 # number of memory refs -system.cpu0.num_load_insts 4794790 # Number of load instructions -system.cpu0.num_store_insts 3396973 # Number of store instructions -system.cpu0.num_idle_cycles 905786099.867998 # Number of idle cycles -system.cpu0.num_busy_cycles 22683877.132002 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024431 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975569 # Percentage of idle cycles -system.cpu0.Branches 4797930 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1559380 5.13% 5.13% # Class of executed instruction -system.cpu0.op_class::IntAlu 19980835 65.68% 70.81% # Class of executed instruction -system.cpu0.op_class::IntMult 31353 0.10% 70.91% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.91% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12822 0.04% 70.95% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.95% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.95% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.95% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1598 0.01% 70.96% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.96% # Class of executed instruction -system.cpu0.op_class::MemRead 4924664 16.19% 87.15% # Class of executed instruction -system.cpu0.op_class::MemWrite 3400050 11.18% 98.32% # Class of executed instruction -system.cpu0.op_class::IprAccess 510577 1.68% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31701170 # Number of instructions committed +system.cpu0.committedOps 31701170 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29591762 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163845 # Number of float alu accesses +system.cpu0.num_func_calls 797475 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4044448 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29591762 # number of integer instructions +system.cpu0.num_fp_insts 163845 # number of float instructions +system.cpu0.num_int_register_reads 41150829 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21753171 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84843 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86199 # number of times the floating registers were written +system.cpu0.num_mem_refs 8322031 # number of memory refs +system.cpu0.num_load_insts 4881580 # Number of load instructions +system.cpu0.num_store_insts 3440451 # Number of store instructions +system.cpu0.num_idle_cycles 904905994.152015 # Number of idle cycles +system.cpu0.num_busy_cycles 22151468.847985 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023894 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976106 # Percentage of idle cycles +system.cpu0.Branches 5099323 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1600258 5.05% 5.05% # Class of executed instruction +system.cpu0.op_class::IntAlu 21086062 66.50% 71.55% # Class of executed instruction +system.cpu0.op_class::IntMult 31841 0.10% 71.65% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12946 0.04% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1618 0.01% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::MemRead 5012305 15.81% 87.50% # Class of executed instruction +system.cpu0.op_class::MemWrite 3443548 10.86% 98.36% # Class of executed instruction +system.cpu0.op_class::IprAccess 519649 1.64% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30421279 # Class of executed instruction +system.cpu0.op_class::total 31708227 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211362 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211399 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818807757000 98.77% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38797500 0.00% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357175000 0.02% 98.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22331016000 1.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841534745500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818498105000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39129500 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 356633500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22720515500 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841614383500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -480,7 +473,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -489,440 +482,442 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192209 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1906 -system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.callpal::total 192207 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322243 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29743380000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2567925500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809223438000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29940410000 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2625898500 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809048073000 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1392924 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13249026 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393436 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.508170 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1393243 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13232435 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393755 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.494090 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.335991 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 163.453449 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 171.208376 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.346359 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.319245 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.334391 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 242.565333 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 83.938780 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 185.493697 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.473760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.163943 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.362292 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63330121 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63330121 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 3955641 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1077876 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2532941 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7566458 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3102475 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 828519 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1367883 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5298877 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113517 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19685 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51083 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184285 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122198 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21798 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55320 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199316 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7058116 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1906395 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3900824 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12865335 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7058116 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1906395 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3900824 # number of overall hits -system.cpu0.dcache.overall_hits::total 12865335 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 705857 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 97562 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 561486 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1364905 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 162429 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43967 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 644644 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 851040 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9228 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2243 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7808 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19279 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 11 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 868286 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 141529 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1206130 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2215945 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101270 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.131021 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094507 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000072 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000025 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110500 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065521 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.239315 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.148709 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110500 # 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mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101270 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.104338 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040484 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000072 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070422 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032226 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070422 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6004498488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1711275000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4293223488 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6004498488 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011105 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011105 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011105 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13134.807605 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16739 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16739 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16739 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16739 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16739 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16739 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 123075 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329781 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 452856 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 123075 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 329781 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 452856 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 123075 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 329781 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 452856 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1746541000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4501465478 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6248006478 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1746541000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4501465478 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6248006478 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1746541000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4501465478 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6248006478 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010881 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010881 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13796.894549 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13796.894549 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13796.894549 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1195033 # DTB read hits -system.cpu1.dtb.read_misses 1325 # DTB read misses -system.cpu1.dtb.read_acv 35 # DTB read access violations -system.cpu1.dtb.read_accesses 141268 # DTB read accesses -system.cpu1.dtb.write_hits 894434 # DTB write hits -system.cpu1.dtb.write_misses 169 # DTB write misses -system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 56923 # DTB write accesses -system.cpu1.dtb.data_hits 2089467 # DTB hits -system.cpu1.dtb.data_misses 1494 # DTB misses -system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 198191 # DTB accesses -system.cpu1.itb.fetch_hits 856224 # ITB hits -system.cpu1.itb.fetch_misses 659 # ITB misses -system.cpu1.itb.fetch_acv 35 # ITB acv -system.cpu1.itb.fetch_accesses 856883 # ITB accesses +system.cpu1.dtb.read_hits 1115382 # DTB read hits +system.cpu1.dtb.read_misses 1270 # DTB read misses +system.cpu1.dtb.read_acv 33 # DTB read access violations +system.cpu1.dtb.read_accesses 123322 # DTB read accesses +system.cpu1.dtb.write_hits 822469 # DTB write hits +system.cpu1.dtb.write_misses 154 # DTB write misses +system.cpu1.dtb.write_acv 18 # DTB write access violations +system.cpu1.dtb.write_accesses 50514 # DTB write accesses +system.cpu1.dtb.data_hits 1937851 # DTB hits +system.cpu1.dtb.data_misses 1424 # DTB misses +system.cpu1.dtb.data_acv 51 # DTB access violations +system.cpu1.dtb.data_accesses 173836 # DTB accesses +system.cpu1.itb.fetch_hits 768661 # ITB hits +system.cpu1.itb.fetch_misses 636 # ITB misses +system.cpu1.itb.fetch_acv 28 # ITB acv +system.cpu1.itb.fetch_accesses 769297 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -935,64 +930,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953248779 # number of cpu cycles simulated +system.cpu1.numCycles 953409174 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7920155 # Number of instructions committed -system.cpu1.committedOps 7920155 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7379126 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45865 # Number of float alu accesses -system.cpu1.num_func_calls 207333 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1021718 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7379126 # number of integer instructions -system.cpu1.num_fp_insts 45865 # number of float instructions -system.cpu1.num_int_register_reads 10346831 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5362502 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24725 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 25053 # number of times the floating registers were written -system.cpu1.num_mem_refs 2096589 # number of memory refs -system.cpu1.num_load_insts 1199833 # Number of load instructions -system.cpu1.num_store_insts 896756 # Number of store instructions -system.cpu1.num_idle_cycles 922000099.418594 # Number of idle cycles -system.cpu1.num_busy_cycles 31248679.581406 # Number of busy cycles -system.cpu1.not_idle_fraction 0.032781 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.967219 # Percentage of idle cycles -system.cpu1.Branches 1295631 # Number of branches fetched -system.cpu1.op_class::No_OpClass 410705 5.18% 5.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 5234650 66.08% 71.26% # Class of executed instruction -system.cpu1.op_class::IntMult 8605 0.11% 71.37% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.37% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5163 0.07% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::MemRead 1228944 15.51% 86.96% # Class of executed instruction -system.cpu1.op_class::MemWrite 897985 11.34% 98.30% # Class of executed instruction -system.cpu1.op_class::IprAccess 134844 1.70% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7126126 # Number of instructions committed +system.cpu1.committedOps 7126126 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6614481 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 39892 # Number of float alu accesses +system.cpu1.num_func_calls 202987 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 849967 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6614481 # number of integer instructions +system.cpu1.num_fp_insts 39892 # number of float instructions +system.cpu1.num_int_register_reads 9205425 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4843983 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 21026 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21409 # number of times the floating registers were written +system.cpu1.num_mem_refs 1944596 # number of memory refs +system.cpu1.num_load_insts 1119921 # Number of load instructions +system.cpu1.num_store_insts 824675 # Number of store instructions +system.cpu1.num_idle_cycles 926242764.786654 # Number of idle cycles +system.cpu1.num_busy_cycles 27166409.213346 # Number of busy cycles +system.cpu1.not_idle_fraction 0.028494 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.971506 # Percentage of idle cycles +system.cpu1.Branches 1116663 # Number of branches fetched +system.cpu1.op_class::No_OpClass 388723 5.45% 5.45% # Class of executed instruction +system.cpu1.op_class::IntAlu 4626654 64.91% 70.37% # Class of executed instruction +system.cpu1.op_class::IntMult 7726 0.11% 70.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.47% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3756 0.05% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatDiv 538 0.01% 70.53% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.53% # Class of executed instruction +system.cpu1.op_class::MemRead 1147644 16.10% 86.64% # Class of executed instruction +system.cpu1.op_class::MemWrite 825879 11.59% 98.22% # Class of executed instruction +system.cpu1.op_class::IprAccess 126681 1.78% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7921706 # Class of executed instruction +system.cpu1.op_class::total 7127601 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1010,35 +1005,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 11475270 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10735483 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 123474 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 9110272 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 7311084 # Number of BTB hits +system.cpu2.branchPred.lookups 11557403 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10821969 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 122344 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 9245404 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 7393469 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.250996 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 301261 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7742 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.969128 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 299976 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7838 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3542926 # DTB read hits -system.cpu2.dtb.read_misses 12527 # DTB read misses -system.cpu2.dtb.read_acv 162 # DTB read access violations -system.cpu2.dtb.read_accesses 225242 # DTB read accesses -system.cpu2.dtb.write_hits 2156991 # DTB write hits -system.cpu2.dtb.write_misses 2860 # DTB write misses -system.cpu2.dtb.write_acv 147 # DTB write access violations -system.cpu2.dtb.write_accesses 84372 # DTB write accesses -system.cpu2.dtb.data_hits 5699917 # DTB hits -system.cpu2.dtb.data_misses 15387 # DTB misses -system.cpu2.dtb.data_acv 309 # DTB access violations -system.cpu2.dtb.data_accesses 309614 # DTB accesses -system.cpu2.itb.fetch_hits 534150 # ITB hits -system.cpu2.itb.fetch_misses 5562 # ITB misses -system.cpu2.itb.fetch_acv 158 # ITB acv -system.cpu2.itb.fetch_accesses 539712 # ITB accesses +system.cpu2.dtb.read_hits 3543723 # DTB read hits +system.cpu2.dtb.read_misses 12250 # DTB read misses +system.cpu2.dtb.read_acv 123 # DTB read access violations +system.cpu2.dtb.read_accesses 249931 # DTB read accesses +system.cpu2.dtb.write_hits 2185333 # DTB write hits +system.cpu2.dtb.write_misses 2753 # DTB write misses +system.cpu2.dtb.write_acv 125 # DTB write access violations +system.cpu2.dtb.write_accesses 92110 # DTB write accesses +system.cpu2.dtb.data_hits 5729056 # DTB hits +system.cpu2.dtb.data_misses 15003 # DTB misses +system.cpu2.dtb.data_acv 248 # DTB access violations +system.cpu2.dtb.data_accesses 342041 # DTB accesses +system.cpu2.itb.fetch_hits 552866 # ITB hits +system.cpu2.itb.fetch_misses 5354 # ITB misses +system.cpu2.itb.fetch_acv 182 # ITB acv +system.cpu2.itb.fetch_accesses 558220 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1051,304 +1046,304 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31796057 # number of cpu cycles simulated +system.cpu2.numCycles 33083271 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9294739 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 42846452 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 11475270 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 7612345 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 20400927 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 406592 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 934 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9632 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1958 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 201207 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 109893 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2820959 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 91095 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 30222906 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.417681 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.345063 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9301099 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 42932048 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 11557403 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 7693445 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 21583805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 404638 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 962 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10456 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1990 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 197395 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 92170 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2784665 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90858 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 31390787 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.367664 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.311444 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20065674 66.39% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 304778 1.01% 67.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 474119 1.57% 68.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5709833 18.89% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 849889 2.81% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 195244 0.65% 91.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 232616 0.77% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433559 1.43% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1957194 6.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 21183291 67.48% 67.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 297740 0.95% 68.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 468841 1.49% 69.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5764163 18.36% 88.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 882544 2.81% 91.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 193394 0.62% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 232558 0.74% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 434405 1.38% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1933851 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 30222906 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.360902 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.347540 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7641311 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13078900 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8781400 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 530431 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 190274 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 176731 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13389 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 39469462 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42545 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 190274 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7916618 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4614900 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6334560 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 9009266 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2156706 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 38654408 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 61763 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 395728 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57668 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1091797 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 25842385 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 48471958 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 48411597 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56430 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 23967156 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1875229 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 535043 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63361 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3828496 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3518120 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2250866 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 468779 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 334709 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 36116015 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 683906 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 35834403 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15167 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2521371 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1120007 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 489344 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 30222906 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.185670 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.632890 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 31390787 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.349343 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.297697 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7618981 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 14231209 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8576643 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 528584 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 189420 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 174742 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13252 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 39552027 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 41601 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 189420 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7898470 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4727919 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6647041 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8797977 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2884017 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 38737545 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 58522 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 372966 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 93481 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1809588 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 25849349 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 48570643 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 48506980 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 59488 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 23977354 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1871995 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 535640 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63418 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3866497 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3518835 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2279192 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 461417 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 331685 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 36218811 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 686292 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 35933838 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 15798 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2519858 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1130776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 490718 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 31390787 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.144726 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.617565 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17428882 57.67% 57.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2748935 9.10% 66.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1369590 4.53% 71.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 6435558 21.29% 92.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1033977 3.42% 96.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 595062 1.97% 97.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 394555 1.31% 99.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 169710 0.56% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 46637 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18577248 59.18% 59.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2723782 8.68% 67.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1358088 4.33% 72.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 6489843 20.67% 92.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1045865 3.33% 96.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 589790 1.88% 98.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 396015 1.26% 99.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 165397 0.53% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44759 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 30222906 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 31390787 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 86081 21.74% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 183352 46.31% 68.05% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126504 31.95% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 81235 20.78% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 20.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 183347 46.90% 67.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126357 32.32% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 29630335 82.69% 82.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21208 0.06% 82.75% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20533 0.06% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.81% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3671135 10.24% 93.06% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2181666 6.09% 99.15% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 305842 0.85% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2960 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 29699192 82.65% 82.66% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21615 0.06% 82.72% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 21814 0.06% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1480 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3672081 10.22% 93.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2209398 6.15% 99.15% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 305298 0.85% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 35834403 # Type of FU issued -system.cpu2.iq.rate 1.127008 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 395937 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.011049 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 102047941 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39206340 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 35210799 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 254875 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 120668 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117568 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36091226 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136658 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206130 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 35933838 # Type of FU issued +system.cpu2.iq.rate 1.086163 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 390939 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.010879 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 103401518 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39305388 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 35307106 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 263682 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 125410 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122335 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36181025 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 140792 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 202971 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 426126 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1149 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5847 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 179431 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 432355 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1077 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5954 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178558 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5057 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 224722 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4490 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 225000 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 190274 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4003128 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 196899 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 38192826 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 53825 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3518120 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2250866 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 608609 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12914 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 142416 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5847 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 60692 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 135198 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195890 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 35634663 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3564372 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 199740 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 189420 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4054480 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 208473 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 38277538 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51152 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3518835 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2279192 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 610930 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12812 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 160010 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5954 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 60508 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134714 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 35737943 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3564708 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 195895 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1392905 # number of nop insts executed -system.cpu2.iew.exec_refs 5729004 # number of memory reference insts executed -system.cpu2.iew.exec_branches 8402054 # Number of branches executed -system.cpu2.iew.exec_stores 2164632 # Number of stores executed -system.cpu2.iew.exec_rate 1.120726 # Inst execution rate -system.cpu2.iew.wb_sent 35371199 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 35328367 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 20848782 # num instructions producing a value -system.cpu2.iew.wb_consumers 24577214 # num instructions consuming a value +system.cpu2.iew.exec_nop 1372435 # number of nop insts executed +system.cpu2.iew.exec_refs 5757521 # number of memory reference insts executed +system.cpu2.iew.exec_branches 8471480 # Number of branches executed +system.cpu2.iew.exec_stores 2192813 # Number of stores executed +system.cpu2.iew.exec_rate 1.080242 # Inst execution rate +system.cpu2.iew.wb_sent 35472276 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 35429441 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 20887132 # num instructions producing a value +system.cpu2.iew.wb_consumers 24638595 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.111093 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.848297 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.070917 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.847740 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2641573 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194562 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 179155 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 29759977 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.193046 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.869762 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2638965 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 195574 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 178349 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 30927462 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.150843 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846358 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18187552 61.11% 61.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2254342 7.58% 68.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1186941 3.99% 72.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6165862 20.72% 93.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 562678 1.89% 95.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 198394 0.67% 95.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 165216 0.56% 96.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 166703 0.56% 97.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 872289 2.93% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 19331784 62.51% 62.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2240622 7.24% 69.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1164134 3.76% 73.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6211408 20.08% 93.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 591221 1.91% 95.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 197085 0.64% 96.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 163594 0.53% 96.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 163249 0.53% 97.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 864365 2.79% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 29759977 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 35505021 # Number of instructions committed -system.cpu2.commit.committedOps 35505021 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 30927462 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 35592650 # Number of instructions committed +system.cpu2.commit.committedOps 35592650 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5163429 # Number of memory references committed -system.cpu2.commit.loads 3091994 # Number of loads committed -system.cpu2.commit.membars 68344 # Number of memory barriers committed -system.cpu2.commit.branches 8230032 # Number of branches committed -system.cpu2.commit.fp_insts 115972 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 33980571 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241816 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1228927 3.46% 3.46% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 28694755 80.82% 84.28% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20756 0.06% 84.34% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.34% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20096 0.06% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.40% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3160338 8.90% 93.30% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2073079 5.84% 99.14% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 305842 0.86% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5187114 # Number of memory references committed +system.cpu2.commit.loads 3086480 # Number of loads committed +system.cpu2.commit.membars 68869 # Number of memory barriers committed +system.cpu2.commit.branches 8299152 # Number of branches committed +system.cpu2.commit.fp_insts 120520 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 34085086 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241488 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1210365 3.40% 3.40% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 28775352 80.85% 84.25% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 21144 0.06% 84.31% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.31% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21379 0.06% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1480 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.37% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3155349 8.87% 93.24% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2102283 5.91% 99.14% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 305298 0.86% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 35505021 # Class of committed instruction -system.cpu2.commit.bw_lim_events 872289 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 66956679 # The number of ROB reads -system.cpu2.rob.rob_writes 76754434 # The number of ROB writes -system.cpu2.timesIdled 177058 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1573151 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1744013124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 34278550 # Number of Instructions Simulated -system.cpu2.committedOps 34278550 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.927579 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.927579 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.078075 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.078075 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 46864030 # number of integer regfile reads -system.cpu2.int_regfile_writes 24760821 # number of integer regfile writes -system.cpu2.fp_regfile_reads 71108 # number of floating regfile reads -system.cpu2.fp_regfile_writes 71427 # number of floating regfile writes -system.cpu2.misc_regfile_reads 6062934 # number of misc regfile reads -system.cpu2.misc_regfile_writes 274246 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 35592650 # Class of committed instruction +system.cpu2.commit.bw_lim_events 864365 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 68219321 # The number of ROB reads +system.cpu2.rob.rob_writes 76925100 # The number of ROB writes +system.cpu2.timesIdled 177793 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1692484 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1742724515 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 34385245 # Number of Instructions Simulated +system.cpu2.committedOps 34385245 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.962136 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.962136 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.039354 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.039354 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 46956630 # number of integer regfile reads +system.cpu2.int_regfile_writes 24762728 # number of integer regfile writes +system.cpu2.fp_regfile_reads 74199 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74347 # number of floating regfile writes +system.cpu2.misc_regfile_reads 6109617 # number of misc regfile reads +system.cpu2.misc_regfile_writes 275370 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1397,37 +1392,33 @@ system.iobus.pkt_size_system.bridge.master::total 45568 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2232000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2206000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5366000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5525000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2084000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 58000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 7000 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 89821669 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 88878376 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 8844000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9362000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17358000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254132 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254039 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693892766000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254132 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078383 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078383 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693946387000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254039 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078377 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078377 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1441,14 +1432,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9418962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9418962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040972707 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2040972707 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9418962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9418962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9418962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9418962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9722962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9722962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2243179414 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2243179414 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9722962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9722962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9722962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9722962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1465,14 +1456,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54444.867052 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49118.519133 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 49118.519133 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54444.867052 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54444.867052 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56202.092486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 56202.092486 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 53984.872305 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 53984.872305 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 56202.092486 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 56202.092486 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1483,245 +1474,248 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5918962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5918962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176972707 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1176972707 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5918962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5918962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5918962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5918962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68111.846470 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68111.846470 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 71 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17168 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 17168 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 71 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 71 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 71 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 71 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6172962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6172962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1384779414 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1384779414 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 6172962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6172962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 6172962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6172962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.410405 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.413169 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.413169 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.410405 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.410405 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86943.126761 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80660.497088 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80660.497088 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 86943.126761 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 86943.126761 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337470 # number of replacements -system.l2c.tags.tagsinuse 65419.393999 # Cycle average of tags in use -system.l2c.tags.total_refs 4005329 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402632 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.947866 # Average number of references to valid blocks. +system.l2c.tags.replacements 337421 # number of replacements +system.l2c.tags.tagsinuse 65422.020035 # Cycle average of tags in use +system.l2c.tags.total_refs 4006967 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402583 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.953145 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54633.992785 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2282.515139 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2705.284872 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 536.585010 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 602.481810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2408.251048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2250.283336 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.833649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.034828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041279 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008188 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009193 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.036747 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.034337 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998221 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54749.853403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2632.785518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2879.050483 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 437.699618 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 303562500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 567210000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 333601500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 379751500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 713353000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 597249000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 683314000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1280563000 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.523810 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408930 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255830 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.140797 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007340 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157938 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061492 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030003 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034964 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034964 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 34272.727273 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 34272.727273 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 21000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 21000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66089.882641 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79053.307630 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73584.633614 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72726.745830 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64248.429867 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64555.503154 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64407.596407 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191860.885276 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202000.962773 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197788.930582 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203651.515152 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200421.522556 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.503699 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198415.964701 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201089.120998 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 200010.600421 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.619048 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.393939 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.367084 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.272781 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.136459 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006824 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.117863 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.045985 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020829 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.193201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.107622 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.029944 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017965 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.193201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.107622 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.029944 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70961.538462 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 70500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117392.867322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125466.345449 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 122724.652761 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122845.861807 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116726.778846 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117147.104153 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116954.769447 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117109.355816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122877.763756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120879.499993 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117109.355816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122877.763756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120879.499993 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196605.145414 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 192371.673004 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 194316.546763 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 205926.851852 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 199449.317227 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 202427.071510 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 201705.167173 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 196241.815049 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 198752.599721 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294907 # Transaction distribution +system.membus.trans_dist::ReadResp 294893 # Transaction distribution system.membus.trans_dist::WriteReq 9810 # Transaction distribution system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116913 # Transaction distribution -system.membus.trans_dist::CleanEvict 262319 # Transaction distribution +system.membus.trans_dist::Writeback 116701 # Transaction distribution +system.membus.trans_dist::CleanEvict 261800 # Transaction distribution system.membus.trans_dist::UpgradeReq 141 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 143 # Transaction distribution -system.membus.trans_dist::ReadExReq 115651 # Transaction distribution -system.membus.trans_dist::ReadExResp 115651 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287769 # Transaction distribution -system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 115600 # Transaction distribution +system.membus.trans_dist::ReadExResp 115600 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288004 # Transaction distribution +system.membus.trans_dist::BadAddressError 255 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144270 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1178190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125023 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125023 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303213 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143509 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 510 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177927 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1302846 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30626752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30672320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33336640 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 157 # Total snoops (count) -system.membus.snoop_fanout::samples 841369 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30608832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30654400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33318656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 161 # Total snoops (count) +system.membus.snoop_fanout::samples 840917 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 841369 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840917 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 841369 # Request fanout histogram -system.membus.reqLayer0.occupancy 11017000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840917 # Request fanout histogram +system.membus.reqLayer0.occupancy 11282500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 393892331 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 355534840 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 348500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 441141955 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 377985955 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 29902743 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 28782491 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 4716700 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2358029 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1601 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1128 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1128 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2061814 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2063159 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 883059 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1572257 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 879803 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1563697 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302698 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302698 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 963876 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1090815 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 17280 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2890767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4213603 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7104370 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61685760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142710656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204396416 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 141516 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4871742 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.029009 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.167832 # Request fanout histogram +system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 38 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302846 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302846 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 965048 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091237 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 255 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 17168 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2894139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214034 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7108173 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61761536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142741760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204503296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421014 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5154488 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000869 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.029472 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4730418 97.10% 97.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141324 2.90% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5150007 99.91% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4481 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4871742 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1371248000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5154488 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1335525500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 102462 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 686121188 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 679735096 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 778360963 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 746367473 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |